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Table 12-3855 lists the memory-mapped registers for the MMCSD1 TX RAM ECC Aggregator. All register offset addresses not listed in Table 12-3855 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9000h |
Offset | Acronym | Register Name | MMCSD1_ECC_AGGR_TXMEM Physical Address |
---|---|---|---|
0h | MMCSD1_TXECC_REV | Aggregator Revision Register | 0070 9000h |
8h | MMCSD1_TXECC_VECTOR | ECC Vector Register | 0070 9008h |
Ch | MMCSD1_TXECC_STAT | Misc Status Register | 0070 900Ch |
3Ch | MMCSD1_TXECC_SEC_EOI_REG | SEC EOI Register | 0070 903Ch |
40h | MMCSD1_TXECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 0070 9040h |
80h | MMCSD1_TXECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 0070 9080h |
C0h | MMCSD1_TXECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 0070 90C0h |
13Ch | MMCSD1_TXECC_DED_EOI_REG | DED EOI Register | 0070 913Ch |
140h | MMCSD1_TXECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 0070 9140h |
180h | MMCSD1_TXECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 0070 9180h |
1C0h | MMCSD1_TXECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 0070 91C0h |
200h | MMCSD1_TXECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 0070 9200h |
204h | MMCSD1_TXECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 0070 9204h |
208h | MMCSD1_TXECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 0070 9208h |
20Ch | MMCSD1_TXECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 0070 920Ch |
MMCSD1_TXECC_REV is shown in Figure 12-1986 and described in Table 12-3857.
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Aggregator Revision Register
Revision parameters.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MMCSD1_TXECC_VECTOR is shown in Figure 12-1987 and described in Table 12-3859.
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ECC Vector Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MMCSD1_TXECC_STAT is shown in Figure 12-1988 and described in Table 12-3861.
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Misc Status Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 900Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-1h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 1h | Indicates the number of RAMs serviced by the ECC aggregator. |
MMCSD1_TXECC_SEC_EOI_REG is shown in Figure 12-1989 and described in Table 12-3863.
Return to Summary Table.
SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 903Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | SEC EOI |
MMCSD1_TXECC_SEC_STATUS_REG0 is shown in Figure 12-1990 and described in Table 12-3865.
Return to Summary Table.
SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for txmem_pend |
MMCSD1_TXECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-1991 and described in Table 12-3867.
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SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for txmem_pend |
MMCSD1_TXECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-1992 and described in Table 12-3869.
Return to Summary Table.
SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 90C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for txmem_pend |
MMCSD1_TXECC_DED_EOI_REG is shown in Figure 12-1993 and described in Table 12-3871.
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DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 913Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | DED EOI |
MMCSD1_TXECC_DED_STATUS_REG0 is shown in Figure 12-1994 and described in Table 12-3873.
Return to Summary Table.
DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for txmem_pend |
MMCSD1_TXECC_DED_ENABLE_SET_REG0 is shown in Figure 12-1995 and described in Table 12-3875.
Return to Summary Table.
DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for txmem_pend |
MMCSD1_TXECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-1996 and described in Table 12-3877.
Return to Summary Table.
DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 91C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | TXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for txmem_pend |
MMCSD1_TXECC_AGGR_ENABLE_SET is shown in Figure 12-1997 and described in Table 12-3879.
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Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for serial ECC interface timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
MMCSD1_TXECC_AGGR_ENABLE_CLR is shown in Figure 12-1998 and described in Table 12-3881.
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Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for serial ECC interface timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
MMCSD1_TXECC_AGGR_STATUS_SET is shown in Figure 12-1999 and described in Table 12-3883.
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Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 9208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for serial ECC interface timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
MMCSD1_TXECC_AGGR_STATUS_CLR is shown in Figure 12-2000 and described in Table 12-3885.
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Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_TXMEM | 0070 920Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for serial ECC interface timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |