SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-3775 lists the memory-mapped registers for the MMCSD1 Subsystem. All register offset addresses not listed in Table 12-3775 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8000h |
Offset | Acronym | Register Name | MMCSD1_SS_CFG Physical Address |
---|---|---|---|
0h | MMCSD1_SS_SS_ID_REV_REG | Subsystem ID and Revision Register | 0FA0 8000h |
10h | MMCSD1_SS_CTL_CFG_1_REG | Controller Config 1 Register | 0FA0 8010h |
14h | MMCSD1_SS_CTL_CFG_2_REG | Controller Config 2 Register | 0FA0 8014h |
18h | MMCSD1_SS_CTL_CFG_3_REG | Controller Config 3 Register | 0FA0 8018h |
1Ch | MMCSD1_SS_CTL_CFG_4_REG | Controller Config 4 Register | 0FA0 801Ch |
20h | MMCSD1_SS_CTL_CFG_5_REG | Controller Config 5 Register | 0FA0 8020h |
24h | MMCSD1_SS_CTL_CFG_6_REG | Controller Config 6 Register | 0FA0 8024h |
28h | MMCSD1_SS_CTL_CFG_7_REG | Controller Config 7 Register | 0FA0 8028h |
2Ch | MMCSD1_SS_CTL_CFG_8_REG | Controller Config 8 Register | 0FA0 802Ch |
30h | MMCSD1_SS_CTL_CFG_9_REG | Controller Config 9 Register | 0FA0 8030h |
34h | MMCSD1_SS_CTL_CFG_10_REG | Controller Config 10 Register | 0FA0 8034h |
38h | MMCSD1_SS_CTL_CFG_11_REG | Controller Config 11 Register | 0FA0 8038h |
3Ch | MMCSD1_SS_CTL_CFG_12_REG | Controller Config 12 Register | 0FA0 803Ch |
40h | MMCSD1_SS_CTL_CFG_13_REG | Controller Config 13 Register | 0FA0 8040h |
60h | MMCSD1_SS_CTL_STAT_1_REG | Controller Status 1 Register | 0FA0 8060h |
64h | MMCSD1_SS_CTL_STAT_2_REG | Controller Status 2 Register | 0FA0 8064h |
68h | MMCSD1_SS_CTL_STAT_3_REG | Controller Status 3 Register | 0FA0 8068h |
6Ch | MMCSD1_SS_CTL_STAT_4_REG | Controller Status 4 Register | 0FA0 806Ch |
70h | MMCSD1_SS_CTL_STAT_5_REG | Controller Status 5 Register | 0FA0 8070h |
74h | MMCSD1_SS_CTL_STAT_6_REG | Controller Status 6 Register | 0FA0 8074h |
100h | MMCSD1_SS_PHY_CTRL_1_REG | PHY Control 1 Register | 0FA0 8100h |
10Ch | MMCSD1_SS_PHY_CTRL_4_REG | PHY Control 4 Register | 0FA0 810Ch |
110h | MMCSD1_SS_PHY_CTRL_5_REG | PHY Control 5 Register | 0FA0 8110h |
MMCSD1_SS_SS_ID_REV_REG is shown in Figure 12-1948 and described in Table 12-3777.
Return to Summary Table.
The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MOD_ID | |||||||||||||||
R-6840h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJ_REV | CUSTOM | MIN_REV | ||||||||||||
R-6h | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MOD_ID | R | 6840h | Module ID |
15-11 | RTL_VER | R | 6h | RTL Version |
10-8 | MAJ_REV | R | 2h | Major Revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MIN_REV | R | 0h | Minor Revision |
MMCSD1_SS_CTL_CFG_1_REG is shown in Figure 12-1949 and described in Table 12-3779.
Return to Summary Table.
The Controller Config 1 Register contains various fields to control the configuration ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | TUNINGCOUNT | ||||||
R-0h | R/W-20h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ASYNCWKUPENA | RESERVED | |||||
R-0h | R/W-1h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CQFMUL | RESERVED | CQFVAL | |||||
R/W-3h | R-0h | R/W-C8h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CQFVAL | |||||||
R/W-C8h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Reserved |
29-24 | TUNINGCOUNT | R/W | 20h | Configures the number of Taps (Phases) of the RX clock that is supported. |
23-21 | RESERVED | R | 0h | Reserved |
20 | ASYNCWKUPENA | R/W | 1h | Determines the Wakeup Signal Generation Mode. |
19-16 | RESERVED | R | 0h | Reserved |
15-12 | CQFMUL | R/W | 3h | FMUL for the CQ Internal Timer Clock Frequency |
11-10 | RESERVED | R | 0h | Reserved |
9-0 | CQFVAL | R/W | C8h | FVAL for the CQ Internal Timer Clock Frequency |
MMCSD1_SS_CTL_CFG_2_REG is shown in Figure 12-1950 and described in Table 12-3781.
Return to Summary Table.
The Controller Config 2 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the MMCSD1_CAPABILITIES register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SLOTTYPE | ASYNCHINTRSUPPORT | RESERVED | SUPPORT1P8VOLT | SUPPORT3P0VOLT | SUPPORT3P3VOLT | ||
R/W-0h | R/W-1h | R-0h | R/W-1h | R/W-1h | R/W-1h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SUSPRESSUPPORT | SDMASUPPORT | HIGHSPEEDSUPPORT | RESERVED | ADMA2SUPPORT | SUPPORT8BIT | MAXBLKLENGTH | |
R/W-1h | R/W-1h | R/W-1h | R-0h | R/W-1h | R/W-0h | R/W-0h | |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BASECLKFREQ | |||||||
R/W-C8h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMEOUTCLKUNIT | RESERVED | TIMEOUTCLKFREQ | |||||
R/W-0h | R-0h | R/W-1h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SLOTTYPE | R/W | 0h | Slot Type Should be set based on the final product usage. |
29 | ASYNCHINTRSUPPORT | R/W | 1h | Asynchronous Interrupt Support Suggested Value is 1h (The Core supports monitoring of Asynchronous Interrupt). |
28-27 | RESERVED | R | 0h | Reserved |
26 | SUPPORT1P8VOLT | R/W | 1h | 1.8 V Support Suggested Value is 1h (The 1.8 Volt Switching is supported by Core). |
25 | SUPPORT3P0VOLT | R/W | 1h | 3.0 V Support Should be set based on whether 3.0 V is supported on the SD Interface. |
24 | SUPPORT3P3VOLT | R/W | 1h | 3.3 V Support Suggested Value is 1h as the 3.3 V is the default voltage on the SD Interface. |
23 | SUSPRESSUPPORT | R/W | 1h | Suspend/Resume Support Suggested Value is 1h (The Suspend/Resume is supported by Core). |
22 | SDMASUPPORT | R/W | 1h | SDMA Support Suggested Value is 1h (The SDMA is supported by Core). |
21 | HIGHSPEEDSUPPORT | R/W | 1h | High Speed Support Suggested Value is 1h (The High Speed mode is supported by Core). |
20 | RESERVED | R | 0h | Reserved |
19 | ADMA2SUPPORT | R/W | 1h | ADMA2 Support Suggested Value is 1h (The ADMA2 is supported by Core). |
18 | SUPPORT8BIT | R/W | 0h | 8-bit Support for Embedded Device Suggested Value is 1h (The Core supports 8-bit Interface). |
17-16 | MAXBLKLENGTH | R/W | 0h | Max Block Length Maximum Block Length supported by the Core/Device. |
15-8 | BASECLKFREQ | R/W | C8h | Base Clock Frequency for SD Clock This is the frequency of the FCLK. |
7 | TIMEOUTCLKUNIT | R/W | 0h | Timeout Clock Unit Suggested Value is 0h (KHz). |
6 | RESERVED | R | 0h | Reserved |
5-0 | TIMEOUTCLKFREQ | R/W | 1h | Timeout Clock Frequency Suggested Value is 1 KHz. |
MMCSD1_SS_CTL_CFG_3_REG is shown in Figure 12-1951 and described in Table 12-3783.
Return to Summary Table.
The Controller Config 3 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the MMCSD1_CAPABILITIES register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SUPPORT1P8VDD2 | ADMA3SUPPORT | RESERVED | ||||
R-0h | R/W-1h | R/W-1h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLOCKMULTIPLIER | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RETUNINGMODES | TUNINGFORSDR50 | RESERVED | RETUNINGTIMERCNT | ||||
R/W-0h | R/W-0h | R-0h | R/W-4h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TYPE4SUPPORT | DDRIVERSUPPORT | CDRIVERSUPPORT | ADRIVERSUPPORT | RESERVED | DDR50SUPPORT | SDR104SUPPORT | SDR50SUPPORT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R/W-1h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | Reserved |
28 | SUPPORT1P8VDD2 | R/W | 1h | 1.8 V VDD2 Support |
27 | ADMA3SUPPORT | R/W | 1h | ADMA3 Support |
26-24 | RESERVED | R | 0h | Reserved |
23-16 | CLOCKMULTIPLIER | R/W | 0h | Clock Multiplier This field indicates clock multiplier value of programmable clock generator. |
15-14 | RETUNINGMODES | R/W | 0h | Re-Tuning Modes Should be set to 2h as the Core supports only the Software Timer based Re-Tuning. |
13 | TUNINGFORSDR50 | R/W | 0h | Use Tuning for SDR50 This bit should be set if the application wants Tuning be used for SDR50 Modes. |
12 | RESERVED | R | 0h | Reserved |
11-8 | RETUNINGTIMERCNT | R/W | 4h | Timer Count for Re-Tuning This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. |
7 | TYPE4SUPPORT | R/W | 0h | Driver Type 4 Support This bit should be set based on whether Driver Type 4 for 1.8 Signalling is supported or not. |
6 | DDRIVERSUPPORT | R/W | 0h | Driver Type D Support This bit should be set based on whether Driver Type D for 1.8 Signalling is supported or not. |
5 | CDRIVERSUPPORT | R/W | 0h | Driver Type C Support This bit should be set based on whether Driver Type C for 1.8 Signalling is supported or not. |
4 | ADRIVERSUPPORT | R/W | 0h | Driver Type A Support This bit should be set based on whether Driver Type A for 1.8 Signalling is supported or not. |
3 | RESERVED | R | 0h | Reserved |
2 | DDR50SUPPORT | R/W | 1h | DDR50 Support Suggested Value is 1h (The Core supports DDR50 mode of operation). |
1 | SDR104SUPPORT | R/W | 1h | SDR104 Support. |
0 | SDR50SUPPORT | R/W | 1h | SDR50 Support. |
MMCSD1_SS_CTL_CFG_4_REG is shown in Figure 12-1952 and described in Table 12-3785.
Return to Summary Table.
The Controller Config 4 Register contains various fields to control the configuration ports on the Host Controller. This register sets the LSB fields in the MMCSD1_MAX_CURRENT_CAP register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 801Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | MAXCURRENT1P8V | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXCURRENT3P0V | MAXCURRENT3P3V | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | MAXCURRENT1P8V | R/W | 0h | Maximum Current For 1.8 V |
15-8 | MAXCURRENT3P0V | R/W | 0h | Maximum Current For 3.0 V |
7-0 | MAXCURRENT3P3V | R/W | 0h | Maximum Current For 3.3 V |
MMCSD1_SS_CTL_CFG_5_REG is shown in Figure 12-1953 and described in Table 12-3787.
Return to Summary Table.
The Controller Config 5 Register contains various fields to control the configuration ports on the Host Controller. This register sets the MSB fields in the MMCSD1_MAX_CURRENT_CAP register inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAXCURRENTVDD2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | MAXCURRENTVDD2 | R/W | 0h | Maximum Current For 1.8 V (VDD2) |
MMCSD1_SS_CTL_CFG_6_REG is shown in Figure 12-1954 and described in Table 12-3789.
Return to Summary Table.
The Controller Config 6 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for Initialization inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-100h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | INITPRESETVAL | R/W | 100h | Preset Value For Initialization |
MMCSD1_SS_CTL_CFG_7_REG is shown in Figure 12-1955 and described in Table 12-3791.
Return to Summary Table.
The Controller Config 7 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for Default Speed inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DSPDPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | DSPDPRESETVAL | R/W | 4h | Preset Value For Default Speed |
MMCSD1_SS_CTL_CFG_8_REG is shown in Figure 12-1956 and described in Table 12-3793.
Return to Summary Table.
The Controller Config 8 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for High Speed inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 802Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSPDPRESETVAL | ||||||||||||||||||||||||||||||
R-0h | R/W-2h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | HSPDPRESETVAL | R/W | 2h | Preset Value For High Speed |
MMCSD1_SS_CTL_CFG_9_REG is shown in Figure 12-1957 and described in Table 12-3795.
Return to Summary Table.
The Controller Config 9 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for SDR12 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR12PRESETVAL | ||||||||||||||
R-0h | R/W-4h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR12PRESETVAL | R/W | 4h | Preset Value For SDR12 |
MMCSD1_SS_CTL_CFG_10_REG is shown in Figure 12-1958 and described in Table 12-3797.
Return to Summary Table.
The Controller Config 10 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for SDR25 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR25PRESETVAL | ||||||||||||||
R-0h | R/W-2h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR25PRESETVAL | R/W | 2h | Preset Value For SDR25 |
MMCSD1_SS_CTL_CFG_11_REG is shown in Figure 12-1959 and described in Table 12-3799.
Return to Summary Table.
The Controller Config 11 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for SDR50 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR50PRESETVAL | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR50PRESETVAL | R/W | 1h | Preset Value For SDR50 |
MMCSD1_SS_CTL_CFG_12_REG is shown in Figure 12-1960 and described in Table 12-3801.
Return to Summary Table.
The Controller Config 12 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for SDR104 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 803Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDR104PRESETVAL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | SDR104PRESETVAL | R/W | 0h | Preset Value For SDR104 |
MMCSD1_SS_CTL_CFG_13_REG is shown in Figure 12-1961 and described in Table 12-3803.
Return to Summary Table.
The Controller Config 13 Register contains various fields to control the configuration ports on the Host Controller. This register sets the fields in the Preset Values registers (MMCSD0_PRESET_VALUE1 to MMCSD0_PRESET_VALUE10) for DDR50 inside the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DDR50PRESETVAL | ||||||||||||||
R-0h | R/W-2h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12-0 | DDR50PRESETVAL | R/W | 2h | Preset Value For DDR50 |
MMCSD1_SS_CTL_STAT_1_REG is shown in Figure 12-1962 and described in Table 12-3805.
Return to Summary Table.
The Controller Status 1 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SDHC_CMDIDLE | RESERVED | ||||||
R-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMADEBUGBUS | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMADEBUGBUS | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SDHC_CMDIDLE | R | 1h | Idle signal to enable software to gate off the clocks |
30-16 | RESERVED | R | 0h | Reserved |
15-0 | DMADEBUGBUS | R | 0h | DMA_CTRL Debug Bus |
MMCSD1_SS_CTL_STAT_2_REG is shown in Figure 12-1963 and described in Table 12-3807.
Return to Summary Table.
The Controller Status 2 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CMDDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-10h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | CMDDEBUGBUS | R | 10h | CMD_CTRL Debug Bus |
MMCSD1_SS_CTL_STAT_3_REG is shown in Figure 12-1964 and described in Table 12-3809.
Return to Summary Table.
The Controller Status 3 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXDDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | TXDDEBUGBUS | R | 0h | TXD_CTRL Debug Bus |
MMCSD1_SS_CTL_STAT_4_REG is shown in Figure 12-1965 and described in Table 12-3811.
Return to Summary Table.
The Controller Status 4 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 806Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXDDEBUGBUS0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | RXDDEBUGBUS0 | R | 0h | RXD_CTRL Debug Bus (SD CLK) |
MMCSD1_SS_CTL_STAT_5_REG is shown in Figure 12-1966 and described in Table 12-3813.
Return to Summary Table.
The Controller Status 5 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXDDEBUGBUS1 | ||||||||||||||||||||||||||||||
R-0h | R-8h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | RXDDEBUGBUS1 | R | 8h | RXD_CTRL Debug Bus (RX CLK) |
MMCSD1_SS_CTL_STAT_6_REG is shown in Figure 12-1967 and described in Table 12-3815.
Return to Summary Table.
The Controller Status 6 Register contains various fields to reflect the status of the debug ports on the Host Controller.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TUNDEBUGBUS | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | TUNDEBUGBUS | R | 0h | TUN_CTRL Debug Bus |
MMCSD1_SS_PHY_CTRL_1_REG is shown in Figure 12-1968 and described in Table 12-3817.
Return to Summary Table.
The PHY Control 1 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IOMUX_ENABLE | RESERVED | ||||||
R/W-1h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOMUX_ENABLE | R/W | 1h | IO Mux Enable Set 1h for GPIO. |
30-0 | RESERVED | R | 0h | Reserved |
MMCSD1_SS_PHY_CTRL_4_REG is shown in Figure 12-1969 and described in Table 12-3819.
Return to Summary Table.
The PHY Control 4 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 810Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OTAPDLYENA | RESERVED | |||||
R-0h | R/W-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OTAPDLYSEL | RESERVED | ITAPCHGWIN | ITAPDLYENA | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ITAPDLYSEL | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R | 0h | Reserved |
20 | OTAPDLYENA | R/W | 0h | Output Tap Delay Enable Enables manual control of the TX clock tap delay, for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. |
19-16 | RESERVED | R | 0h | Reserved |
15-12 | OTAPDLYSEL | R/W | 0h | Output Tap Delay Select Manual control of the TX clock tap delay for clocking the final stage flops for maintaining Hold requirements on EMMC Interface. |
11-10 | RESERVED | R | 0h | Reserved |
9 | ITAPCHGWIN | R/W | 0h | Input Tap Change Window It gets asserted by the controller while changing the itapdlysel. |
8 | ITAPDLYENA | R/W | 0h | Input Tap Delay Enable This is used for the manual control of the RX clock Tap Delay in non HS200/HS400 modes. |
7-5 | RESERVED | R | 0h | Reserved |
4-0 | ITAPDLYSEL | R/W | 0h | Input Tap Delay Select Manual control of the RX clock Tap Delay in the non HS200/HS400 modes. |
MMCSD1_SS_PHY_CTRL_5_REG is shown in Figure 12-1970 and described in Table 12-3821.
Return to Summary Table.
The PHY Control 5 Register contains various fields to control the ports on the Host Controller PHY.
Instance | Physical Address |
---|---|
MMCSD1_SS_CFG | 0FA0 8110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLKBUFSEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | CLKBUFSEL | R/W | 0h | Clock Delay Buffer Select. |