SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Short Description: Map Register
Long Description: The Map Register defines the fields for the initiator MCU_R5FSS0 per channel.
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Instance Name | Physical Address |
---|---|
MCU_CBASS0 | 45D3 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPRIORITY | ASEL | ORDERID | RESERVED | RESERVED | ||||||||||
NONE | R/W | R/W | R/W | NONE | NONE | ||||||||||
7h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:15 | RESERVED | NONE | Reserved | |
14:12 | EPRIORITY | R/W | 7h | epriority signal for channel N. This is the strict priority arbitration priority at the destination Reset Source: domain_default_rst_mod_g_rst_n |
11:8 | ASEL | R/W | 0h | AM64x only uses this for PCIe, and cache coherency
with A53 ACP. So traffic to MSRAM or DDR with asel set to below values will be
routed via A53 cache controller.ASEL=0 | SOC
Address ASEL=1 | PCIe address space for the entire address ASEL=14 | W | cause L2 cache allocation: for cache warming feature ASEL=14 | R | does not cause L2 cache allocation ASEL=15 | R/W | does not cause L2 cache allocation Reset Source: domain_default_rst_mod_g_rst_n |
7:4 | ORDERID | R/W | 0h | orderid signal for channel N. Selects to route for load balancing (0-7 uses one route, 8-15 another). Also used by DDR4/LPDDR4 re-ordering to maximize throughput. Order of transactions is only guaranteed with the same orderid Reset Source: domain_default_rst_mod_g_rst_n |
3 | RESERVED | NONE | Reserved | |
2:0 | RESERVED | R/W | Reserved Reset Source: domain_default_rst_mod_g_rst_n |