SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-3273 lists the memory-mapped registers for the GPMC. All register offset addresses not listed in Table 12-3273 should be considered as reserved locations and the register contents should not be modified.
All GPMC registers are aligned to 32-bit address boundaries. All register file accesses, except to GPMC_NAND_DATA_i register, are little-endian. If the GPMC_NAND_DATA_i register location is accessed, the endianness is access-dependent.
Instance | Base Address |
---|---|
GPMC0_CFG | 3B00 0000h |
Offset | Acronym | Register Name | GPMC0_CFG Physical Address |
---|---|---|---|
0h | GPMC_REVISION | IP revision | 3B00 0000h |
10h | GPMC_SYSCONFIG | Module software reset and local power management register | 3B00 0010h |
14h | GPMC_SYSSTATUS | Module status information register | 3B00 0014h |
18h | GPMC_IRQSTATUS | Interrupt status register | 3B00 0018h |
1Ch | GPMC_IRQENABLE | Interrupt enable register | 3B00 001Ch |
40h | GPMC_TIMEOUT_CONTROL | Control register of timeout counter | 3B00 0040h |
44h | GPMC_ERR_ADDRESS | Error address register | 3B00 0044h |
48h | GPMC_ERR_TYPE | Error type register | 3B00 0048h |
50h | GPMC_CONFIG | Global configuration register | 3B00 0050h |
54h | GPMC_STATUS | Global status register | 3B00 0054h |
60h + formula | GPMC_CONFIG1_i | Configuration register 1 | 3B00 0060h + formula |
64h + formula | GPMC_CONFIG2_i | Configuration register 2 | 3B00 0064h + formula |
68h + formula | GPMC_CONFIG3_i | Configuration register 3 | 3B00 0068h + formula |
6Ch + formula | GPMC_CONFIG4_i | Configuration register 4 | 3B00 006Ch + formula |
70h + formula | GPMC_CONFIG5_i | Configuration register 5 | 3B00 0070h + formula |
74h + formula | GPMC_CONFIG6_i | Configuration register 6 | 3B00 0074h + formula |
78h + formula | GPMC_CONFIG7_i | Configuration register 7 | 3B00 0078h + formula |
7Ch + formula | GPMC_NAND_COMMAND_i | GPMC NAND COMMAND_i location register | 3B00 007Ch + formula |
80h + formula | GPMC_NAND_ADDRESS_i | GPMC NAND ADDRESS_i location register | 3B00 0080h + formula |
84h + formula | GPMC_NAND_DATA_i | GPMC NAND DATA_i location register | 3B00 0084h + formula |
1E0h | GPMC_PREFETCH_CONFIG1 | Prefetch engine configuration 1 | 3B00 01E0h |
1E4h | GPMC_PREFETCH_CONFIG2 | Prefetch engine configuration 2 | 3B00 01E4h |
1ECh | GPMC_PREFETCH_CONTROL | Prefetch engine control | 3B00 01ECh |
1F0h | GPMC_PREFETCH_STATUS | Prefetch engine status | 3B00 01F0h |
1F4h | GPMC_ECC_CONFIG | ECC configuration | 3B00 01F4h |
1F8h | GPMC_ECC_CONTROL | ECC control | 3B00 01F8h |
1FCh | GPMC_ECC_SIZE_CONFIG | ECC size | 3B00 01FCh |
200h + formula | GPMC_ECCj_RESULT | ECC result register | 3B00 0200h + formula |
240h + formula | GPMC_BCH_RESULT0_i | BCH ECC result (bits 0 to 31) | 3B00 0240h + formula |
244h + formula | GPMC_BCH_RESULT1_i | BCH ECC result (bits 32 to 63) | 3B00 0244h + formula |
248h + formula | GPMC_BCH_RESULT2_i | BCH ECC result (bits 64 to 95) | 3B00 0248h + formula |
24Ch + formula | GPMC_BCH_RESULT3_i | BCH ECC result (bits 96 to 127) | 3B00 024Ch + formula |
2D0h | GPMC_BCH_SWDATA | Data to BCH ECC calculator | 3B00 02D0h |
300h + formula | GPMC_BCH_RESULT4_i | BCH ECC result (bits 128 to 159) | 3B00 0300h + formula |
304h + formula | GPMC_BCH_RESULT5_i | BCH ECC result (bits 160 to 191) | 3B00 0304h + formula |
308h + formula | GPMC_BCH_RESULT6_i | BCH ECC result (bits 192 to 207) | 3B00 0308h + formula |
GPMC_REVISION is shown in Figure 12-1661 and described in Table 12-3275.
This register contains the IP revision code.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION | |||||||||||||||||||||||||||||||
R-60h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVISION | R | 60h | TI internal data. Identifies revision of peripheral. |
GPMC_SYSCONFIG is shown in Figure 12-1662 and described in Table 12-3277.
Register related to module software reset and local power management.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | RESERVED | RESERVED | AUTOIDLE | |||
R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
4-3 | IDLEMODE | R/W | 0h |
0h = Force-idle. A clock stop request is acknowledged unconditionally. 1h (R/W) = No-idle. A clock stop request is never acknowledged. 2h (R/W) = Smart-idle. Acknowledgment to a clock stop request is given based on the internal activity of the module. 3h (R/W) = Reserved. Do not use. |
2 | RESERVED | R | 0h |
Write 0 for future compatibility Read returns 0. |
1 | RESERVED | R/W | 0h |
This bit must be
kept 0 for normal functioning of the IP. |
0 | AUTOIDLE | R/W | 0h |
Internal interface clock-gating strategy 0h (R/W) = Interface clock is free-running. 1h (R/W) = Automatic Interface clock gating strategy is applied, based on the interconnect activity. |
GPMC_SYSSTATUS is shown in Figure 12-1663 and described in Table 12-3279.
This register provides status information about the module, excluding the interrupt status information.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESETDONE | ||||||
R-0h | R- | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h |
Read returns 0. |
7-1 | RESERVED | R | 0h |
Read returns 0 (reserved for interconnect-socket status information). |
0 | RESETDONE | R | -h |
Internal reset monitoring 0h (R) = Internal module reset is ongoing. 1h (R) = Reset is complete. |
GPMC_IRQSTATUS is shown in Figure 12-1664 and described in Table 12-3281.
This interrupt status register regroups all the status of the module internal events that can generate an interrupt.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WAIT1EDGEDETECTIONSTATUS | WAIT0EDGEDETECTIONSTATUS | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TERMINALCOUNTSTATUS | FIFOEVENTSTATUS | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
9 | WAIT1EDGEDETECTIONSTATUS | R/W | 0h |
Status of the Wait1 Edge Detection interrupt Write: 0h = WAIT1EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT1EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT1 input pin has not been detected. 1h = A transition on WAIT1 input pin has been detected. |
8 | WAIT0EDGEDETECTIONSTATUS | R/W | 0h |
Status of the Wait0 Edge Detection interrupt Write: 0h = WAIT0EDGEDETECTIONSTATUS bit is unchanged. 1h = WAIT0EDGEDETECTIONSTATUS bit is reset. Read: 0h = A transition on WAIT0 input pin has not been detected. 1h = A transition on WAIT0 input pin has been detected. |
7-2 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
1 | TERMINALCOUNTSTATUS | R/W | 0h |
Status of the TerminalCountEvent interrupt Write: 0h = TERMINALCOUNTSTATUS bit is unchanged. 1h = TERMINALCOUNTSTATUS bit is reset. Read: 0h = Indicates that CountValue is greater than 0. 1h = Indicates that CountValue is equal to 0. |
0 | FIFOEVENTSTATUS | R/W | 0h |
Status of the FIFOEvent interrupt Write: 0h = FIFOEVENTSTATUS bit is unchanged. 1h = FIFOEVENTSTATUS bit is reset. Read: 0h = Indicates that less than GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bytes are available in prefetch mode and less than FIFOTHRESHOLD bytes free places are available in write-posting mode. 1h = Indicates that at least GPMC_PREFETCH_STATUS[16] FIFOTHRESHOLDSTATUS bytes are available in prefetch mode and at least FIFOTHRESHOLD bytes free places are available in write-posting mode. |
GPMC_IRQENABLE is shown in Figure 12-1665 and described in Table 12-3283.
The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WAIT1EDGEDETECTIONENABLE | WAIT0EDGEDETECTIONENABLE | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TERMINALCOUNTEVENTENABLE | FIFOEVENTENABLE | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
9 | WAIT1EDGEDETECTIONENABLE | R/W | 0h |
Enables the Wait1 Edge Detection interrupt 0h (R/W) = Wait1EdgeDetection interrupt is masked. 1h (R/W) = Wait1EdgeDetection event generates an interrupt if occurs. |
8 | WAIT0EDGEDETECTIONENABLE | R/W | 0h |
Enables the Wait0 Edge Detection interrupt 0h (R/W) = Wait0EdgeDetection interrupt is masked. 1h (R/W) = Wait0EdgeDetection event generates an interrupt if occurs. |
7-2 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
1 | TERMINALCOUNTEVENTENABLE | R/W | 0h |
Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode 0h (R/W) = TerminalCountEvent interrupt is masked. 1h (R/W) = TerminalCountEvent interrupt is not masked. |
0 | FIFOEVENTENABLE | R/W | 0h |
Enables the FIFOEvent interrupt 0h (R/W) = FIFOEvent interrupt is masked. 1h (R/W) = FIFOEvent interrupt is not masked. |
GPMC_TIMEOUT_CONTROL is shown in Figure 12-1666 and described in Table 12-3285.
The GPMC_TIMEOUT_CONTROL register allows the user to set the start value of the timeout counter.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TIMEOUTSTARTVALUE | ||||||
R-0h | R/W-1FFh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIMEOUTSTARTVALUE | RESERVED | TIMEOUTENABLE | |||||
R/W-1FFh | R-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
12-4 | TIMEOUTSTARTVALUE | R/W | 1FFh |
Start value of the
time-out counter |
3-1 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
0 | TIMEOUTENABLE | R/W | 0h |
Enable bit of the TimeOut feature 0h (R/W) = TimeOut feature is disabled. 1h (R/W) = TimeOut feature is enabled. |
GPMC_ERR_ADDRESS is shown in Figure 12-1667 and described in Table 12-3287.
The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ILLEGALADD | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ILLEGALADD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ILLEGALADD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ILLEGALADD | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
30-0 | ILLEGALADD | R | 0h |
Address of illegal
access |
GPMC_ERR_TYPE is shown in Figure 12-1668 and described in Table 12-3289.
The GPMC_ERR_TYPE register stores the type of error when an error occurs.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ILLEGALMCMD | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERRORNOTSUPPADD | ERRORNOTSUPPMCMD | ERRORTIMEOUT | RESERVED | ERRORVALID | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R/W1C-0h | ||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
10-8 | ILLEGALMCMD | R | 0h |
System command of the transaction that caused the error |
7-5 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
4 | ERRORNOTSUPPADD | R | 0h |
Not supported address error 0h (R) = No error occurs. 1h (R) = The error is due to a non supported address. |
3 | ERRORNOTSUPPMCMD | R | 0h |
Not supported command error 0h (R) = No error occurs. 1h (R) = The error is due to a non supported command |
2 | ERRORTIMEOUT | R | 0h |
Time-out error 0h (R) = No error occurs. 1h (R) = The error is due to a timeout. |
1 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
0 | ERRORVALID | R/W1C | 0h |
Error validity status - Must be explicitly cleared with a write 1 transaction 0h (R/W) = All error fields no longer valid 1h (R/W) = Error detected and logged in the other error fields |
GPMC_CONFIG is shown in Figure 12-1669 and described in Table 12-3291.
The configuration register allows global configuration of the GPMC.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WAIT1PINPOLARITY | WAIT0PINPOLARITY | |||||
R-0h | R/W-1h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WRITEPROTECT | RESERVED | NANDFORCEPOSTEDWRITE | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
9 | WAIT1PINPOLARITY | R/W | 1h |
Selects the polarity of input pin WAIT1 0h (R/W) = WAIT1 active low 1h (R/W) = WAIT1 active high |
8 | WAIT0PINPOLARITY | R/W | 0h |
Selects the polarity of input pin WAIT0 0h (R/W) = WAIT0 active low 1h (R/W) = WAIT0 active high |
7-5 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
4 | WRITEPROTECT | R/W | 0h |
Controls the WP output pin level 0h (R/W) = nWP output pin is low 1h (R/W) = nWP output pin is high |
3-1 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
0 | NANDFORCEPOSTEDWRITE | R/W | 0h |
Enables the Force Posted Write feature to NAND Cmd/Add/Data location 0h (R/W) = Disables Force Posted Write 1h (R/W) = Enables Force Posted Write |
GPMC_STATUS is shown in Figure 12-1670 and described in Table 12-3293.
The status register provides global status bits of the GPMC.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WAIT1STATUS | WAIT0STATUS | |||||
R-0h | R- | R- | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EMPTYWRITEBUFFERSTATUS | ||||||
R-0h | R-1h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
9 | WAIT1STATUS | R | -h |
Is a copy of input pin WAIT1. (Reset value is WAIT1 input pin sampled at device reset.) 0h (R) = WAIT1 asserted (inactive state) 1h (R) = WAIT1 deasserted |
8 | WAIT0STATUS | R | -h |
Is a copy of input pin WAIT0. (Reset value is WAIT0 input pin sampled at device reset.) 0h (R) = WAIT0 asserted (inactive state) 1h (R) = WAIT0 deasserted |
7-1 | RESERVED | R | 0h |
Write 0s for future compatibility. Reads returns 0 |
0 | EMPTYWRITEBUFFERSTATUS | R | 1h |
Stores the empty status of the write buffer 0h (R) = Write buffer is not empty. 1h (R) = Write buffer is empty. |
GPMC_CONFIG1_i (where i = 0 to 3) is shown in Figure 12-1671 and described in Table 12-3295.
The configuration register 1 sets signal control parameters per chip-select.
Offset = 60h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0060h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WRAPBURST | READMULTIPLE | READTYPE | WRITEMULTIPLE | WRITETYPE | CLKACTIVATIONTIME | ATTACHEDDEVICEPAGELENGTH | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ATTACHEDDEVICEPAGELENGTH | WAITREADMONITORING | WAITWRITEMONITORING | RESERVED | WAITMONITORINGTIME | WAITPINSELECT | ||
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DEVICESIZE | DEVICETYPE | MUXADDDATA | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEPARAGRANULARITY | RESERVED | GPMCFCLKDIVIDER | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | WRAPBURST | R/W | 0h |
Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst 0h (R/W) = Synchronous wrapping burst not supported 1h (R/W) = Synchronous wrapping burst supported |
30 | READMULTIPLE | R/W | 0h |
Selects the read single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous, page if asynchronous) |
29 | READTYPE | R/W | 0h |
Selects the read mode operation 0h (R/W) = Read asynchronous 1h (R/W) = Read synchronous |
28 | WRITEMULTIPLE | R/W | 0h |
Selects the write single or multiple access 0h (R/W) = Single access 1h (R/W) = Multiple access (burst if synchronous, considered as single if asynchronous) |
27 | WRITETYPE | R/W | 0h |
Selects the write mode operation 0h (R/W) = Write asynchronous 1h (R/W) = Write synchronous |
26-25 | CLKACTIVATIONTIME | R/W | 0h |
Output GPMC CLK activation time 0h (R/W) = First rising edge of GPMC CLK at start access time 1h (R/W) = First rising edge of GPMC CLK one GPMC_FCLK cycle after start access time 2h (R/W) = First rising edge of GPMC CLK two GPMC_FCLK cycles after start access time 3h (R/W) = Reserved |
24-23 | ATTACHEDDEVICEPAGELENGTH | R/W | 0h |
Specifies the attached device page (burst) length 0h (R/W) = 4 words 1h (R/W) = 8 words 2h (R/W) = 16 words 3h (R/W) = 32 words |
22 | WAITREADMONITORING | R/W | 0h |
Selects the Wait monitoring configuration for Read accesses 0h (R/W) = WAIT pin is not monitored for read accesses. 1h (R/W) = WAIT pin is monitored for read accesses. |
21 | WAITWRITEMONITORING | R/W | 0h |
Selects the Wait monitoring configuration for Write accesses 0h (R/W) = WAIT pin is not monitored for write accesses. 1h (R/W) = WAIT pin is monitored for write accesses. |
20 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
19-18 | WAITMONITORINGTIME | R/W | 0h |
Selects input pin Wait monitoring time 0h (R/W) = WAIT pin is monitored with valid data. 1h (R/W) = WAIT pin is monitored one GPMC CLK cycle before valid data. 2h (R/W) = WAIT pin is monitored two GPMC CLK cycle before valid data. 3h (R/W) = Reserved |
17-16 | WAITPINSELECT | R/W | 0h |
Selects the input WAIT pin for this chip-select 0h (R/W) = Wait input pin is WAIT0. 1h (R/W) = Wait input pin is WAIT1. 2h (R/W) = Reserved 3h (R/W) = Reserved |
15-14 | RESERVED | R | 0h |
Write 0s for
future compatibility. |
13-12 | DEVICESIZE | R/W | 0h |
Selects the device
size attached 0h (R/W) = 8 bit 1h (R/W) = 16 bit 2h (R/W) = 32 bit 3h (R/W) = Reserved |
11-10 | DEVICETYPE | R/W | 0h |
Selects the attached device type 0h (R/W) = NOR flash-like, asynchronous and synchronous devices 1h (R/W) = Reserved 2h (R/W) = NAND flash-like devices, stream mode 3h (R/W) = Reserved |
9-8 | MUXADDDATA | R/W | 0h |
Enables the address and data multiplexed protocol 0h (R/W) = Nonmultiplexed attached device 1h (R/W) = AAD-multiplexed protocol device 2h (R/W) = Address and data multiplexed attached device 3h (R/W) = Reserved |
7-5 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
4 | TIMEPARAGRANULARITY | R/W | 0h |
Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS) 0h (R/W) = x1 latencies 1h (R/W) = x2 latencies |
3-2 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
1-0 | GPMCFCLKDIVIDER | R/W | 0h |
Divides the GPMC_FCLK clock 0h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency 1h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency / 2 2h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency / 3 3h (R/W) = GPMC CLK frequency = GPMC_FCLK frequency /4 |
GPMC_CONFIG2_i (where i = 0 to 3) is shown in Figure 12-1672 and described in Table 12-3297.
CS signal timing parameter configuration
Offset = 64h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0064h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CSWROFFTIME | ||||||
R-0h | R/W-10h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CSRDOFFTIME | ||||||
R-0h | R/W-10h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CSEXTRADELAY | RESERVED | CSONTIME | |||||
R/W-0h | R-0h | R/W-1h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R | 0h |
Write 0s for
future compatibility. |
20-16 | CSWROFFTIME | R/W | 10h |
CSi deassertion
time from start cycle time for write accesses |
15-13 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
12-8 | CSRDOFFTIME | R/W | 10h |
CSi de-assertion
time from start cycle time for read accesses |
7 | CSEXTRADELAY | R/W | 0h |
CSi Add extra half-GPMC_FCLK cycle 0h (R/W) = CSi Timing control signal is not delayed 1h (R/W) = CSi Timing control signal is delayed of half GPMC_FCLK clock cycle |
6-4 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
3-0 | CSONTIME | R/W | 1h |
CSi assertion time
from start cycle time |
GPMC_CONFIG3_i (where i = 0 to 3) is shown in Figure 12-1673 and described in Table 12-3299.
nADV signal timing parameter configuration
Offset = 68h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0068h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | ADVAADMUXWROFFTIME | RESERVED | ADVAADMUXRDOFFTIME | ||||
R-0h | R/W-2h | R-0h | R/W-2h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ADVWROFFTIME | ||||||
R-0h | R/W-6h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ADVRDOFFTIME | ||||||
R-0h | R/W-5h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADVEXTRADELAY | ADVAADMUXONTIME | ADVONTIME | |||||
R/W-0h | R/W-1h | R/W-4h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
30-28 | ADVAADMUXWROFFTIME | R/W | 2h |
nADV deassertion
for first address phase when using the AAD-multiplexed protocol
|
27 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
26-24 | ADVAADMUXRDOFFTIME | R/W | 2h |
nADV assertion for
first address phase when using the AAD-multiplexed protocol |
23-21 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
20-16 | ADVWROFFTIME | R/W | 6h |
nADV deassertion
time from start cycle time for write accesses |
15-13 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
12-8 | ADVRDOFFTIME | R/W | 5h |
nADV deassertion
time from start cycle time for read accesses |
7 | ADVEXTRADELAY | R/W | 0h |
nADV add extra half-GPMC_FCLK cycle 0h (R/W) = nADV timing control signal is not delayed 1h (R/W) = nADV timing control signal is delayed of half GPMC_FCLK clock cycle |
6-4 | ADVAADMUXONTIME | R/W | 1h |
nADV assertion for
first address phase when using the AAD-multiplexed protocol |
3-0 | ADVONTIME | R/W | 4h |
nADV assertion
time from start cycle time |
GPMC_CONFIG4_i (where i = 0 to 3) is shown in Figure 12-1674 and described in Table 12-3301.
nWE and nOE signals timing parameter configuration
Offset = 6Ch + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 006Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | WEOFFTIME | ||||||
R-0h | R/W-10h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WEEXTRADELAY | RESERVED | WEONTIME | |||||
R/W-0h | R-0h | R/W-5h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
OEAADMUX_OFFTIME | OEOFFTIME | ||||||
R/W-3h | R/W-10h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OEEXTRADELAY | OEAADMUX_ONTIME | OEONTIME | |||||
R/W-0h | R/W-1h | R/W-6h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
28-24 | WEOFFTIME | R/W | 10h |
nWE deassertion
time from start cycle time |
23 | WEEXTRADELAY | R/W | 0h |
nWE add extra half-GPMC_FCLK cycle 0h (R/W) = nWE timing control signal is not delayed 1h (R/W) = nWE timing control signal is delayed of half-GPMC_FCLK clock cycle |
22-20 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
19-16 | WEONTIME | R/W | 5h |
nWE assertion time
from start cycle time |
15-13 | OEAADMUX_OFFTIME | R/W | 3h |
nOE deassertion
time for the first address phase in an AAD-multiplexed access
|
12-8 | OEOFFTIME | R/W | 10h |
nOE deassertion
time from start cycle time |
7 | OEEXTRADELAY | R/W | 0h |
nOE add extra half-GPMC_FCLK cycle 0h (R/W) = nOE timing control signal is not delayed 1h (R/W) = nOE timing control signal is delayed of half-GPMC_FCLK clock cycle |
6-4 | OEAADMUX_ONTIME | R/W | 1h |
nOE assertion time
for the first address phase in an AAD-mux access |
3-0 | OEONTIME | R/W | 6h |
nOE assertion time
from start cycle time |
GPMC_CONFIG5_i (where i = 0 to 3) is shown in Figure 12-1675 and described in Table 12-3303.
RdAccessTime and CycleTime timing parameters configuration
Offset = 70h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0070h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PAGEBURSTACCESSTIME | ||||||
R-0h | R/W-1h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RDACCESSTIME | ||||||
R-0h | R/W-Fh | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WRCYCLETIME | ||||||
R-0h | R/W-11h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDCYCLETIME | ||||||
R-0h | R/W-11h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
27-24 | PAGEBURSTACCESSTIME | R/W | 1h |
Delay between
successive words in a multiple access |
23-21 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
20-16 | RDACCESSTIME | R/W | Fh |
Delay between
start cycle time and first data valid |
15-13 | RESERVED | R | 0h |
Write 0s for
future compatibility. |
12-8 | WRCYCLETIME | R/W | 11h |
Total write cycle
time |
7-5 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
4-0 | RDCYCLETIME | R/W | 11h |
Total read cycle
time |
GPMC_CONFIG6_i (where i = 0 to 3) is shown in Figure 12-1676 and described in Table 12-3305.
WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration
Offset = 74h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0074h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | WRACCESSTIME | |||||
R/W-1h | R-0h | R/W-Fh | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | WRDATAONADMUXBUS | ||||||
R-0h | R/W-7h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CYCLE2CYCLEDELAY | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CYCLE2CYCLESAMECSEN | CYCLE2CYCLEDIFFCSEN | RESERVED | BUSTURNAROUND | ||||
R/W-0h | R/W-0h | R-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | 1h |
TI Internal use - Do not modify. |
30-29 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
28-24 | WRACCESSTIME | R/W | Fh |
Delay from start
access time to the GPMC_FCLK rising edge corresponding the GPMC
CLK rising edge used by the attached memory for the first data
capture |
23-20 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
19-16 | WRDATAONADMUXBUS | R/W | 7h |
Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus |
15-12 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
11-8 | CYCLE2CYCLEDELAY | R/W | 0h |
Chip-select high
pulse delay between successive accesses |
7 | CYCLE2CYCLESAMECSEN | R/W | 0h |
Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY |
6 | CYCLE2CYCLEDIFFCSEN | R/W | 0h |
Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type) 0h (R/W) = No delay between the two accesses 1h (R/W) = Add CYCLE2CYCLEDELAY |
5-4 | RESERVED | R | 0h |
Write 0s for
future compatibility. |
3-0 | BUSTURNAROUND | R/W | 0h |
Bus turnaround
latency between successive accesses to the same chip-select
(read to write) or to a different chip-select (read to read and
read to write) |
GPMC_CONFIG7_i (where i = 0 to 3) is shown in Figure 12-1677 and described in Table 12-3307.
CS address mapping configuration
Offset = 78h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0078h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MASKADDRESS | ||||||
R-0h | R/W-Fh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSVALID | BASEADDRESS | |||||
R-0h | R/W-1h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
11-8 | MASKADDRESS | R/W | Fh |
CS mask address.
|
7 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
6 | CSVALID | R/W | 1h |
CS enable 0h (R/W) = CS disabled 1h (R/W) = CS enabled |
5-0 | BASEADDRESS | R/W | 0h |
CSi base address where i = 0 to 3 (16-MB minimum granularity) bits [5-0] corresponds to A29, A28, A27, A26, A25, and A24. See Chip-Select Address Mapping and Decoding Mask. |
GPMC_NAND_COMMAND_i (where i = 0 to 3) is shown in Figure 12-1678 and described in Table 12-3309.
This register is not a true register, only an address location.
Offset = 7Ch + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 007Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPMC_NAND_COMMAND | |||||||||||||||||||||||||||||||
W- | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GPMC_NAND_COMMAND | W | -h |
This register is not a true register, only an address location. Writing data at the GPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access. |
GPMC_NAND_ADDRESS_i (where i = 0 to 3) is shown in Figure 12-1679 and described in Table 12-3311.
This register is not a true register, only an address location.
Offset = 80h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPMC_NAND_ADDRESS | |||||||||||||||||||||||||||||||
W- | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GPMC_NAND_ADDRESS | W | -h |
This register is not a true register, only an address location. Writing data at the GPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access. |
GPMC_NAND_DATA_i (where i = 0 to 3) is shown in Figure 12-1680 and described in Table 12-3313.
This register is not a true register, only an address location.
Offset = 84h + (i * 30h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0084h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPMC_NAND_DATA | |||||||||||||||||||||||||||||||
R/W- | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | GPMC_NAND_DATA | R/W | -h |
This register is not a true register, only an address location. Reading data from the GPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access. |
GPMC_PREFETCH_CONFIG1 is shown in Figure 12-1681 and described in Table 12-3315.
Prefetch engine configuration 1
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CYCLEOPTIMIZATION | ENABLEOPTIMIZEDACCESS | ENGINECSSELECTOR | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PFPWENROUNDROBIN | RESERVED | PFPWWEIGHTEDPRIO | |||||
R/W-0h | R-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FIFOTHRESHOLD | ||||||
R-0h | R/W-40h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLEENGINE | RESERVED | WAITPINSELECTOR | SYNCHROMODE | DMAMODE | ENDIANISMTYPE | ACCESSMODE | |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
30-28 | CYCLEOPTIMIZATION | R/W | 0h |
Define the number
of GPMC_FCLK cycles to be subtracted from RDCYCLETIME,
WRCYCLETIME, RDACCESSTIME, CSRDOFFTIME, CSWROFFTIME,
ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, WEOFFTIME |
27 | ENABLEOPTIMIZEDACCESS | R/W | 0h |
Enables access cycle optimization 0h (R/W) = Access cycle optimization is disabled. 1h (R/W) = Access cycle optimization is enabled. |
26-24 | ENGINECSSELECTOR | R/W | 0h |
Selects the
chip-select where Prefetch Postwrite engine is active |
23 | PFPWENROUNDROBIN | R/W | 0h |
Enables the PFPW RoundRobin arbitration 0h (R/W) = Prefetch Postwrite engine round robin arbitration is disabled. 1h (R/W) = Prefetch Postwrite engine round robin arbitration is enabled. |
22-20 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
19-16 | PFPWWEIGHTEDPRIO | R/W | 0h |
When an
arbitration occurs between a DMA and a PFPW engine access, the
DMA is always serviced. If the PFPWEnRoundRobin is enabled, |
15 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
14-8 | FIFOTHRESHOLD | R/W | 40h |
Selects the
maximum number of bytes read from the FIFO or written to the
FIFO by the host on a DMA or interrupt request |
7 | ENABLEENGINE | R/W | 0h |
Enables the Prefetch Postwite engine 0h (R/W) = Prefetch Postwrite engine is disabled. 1h (R/W) = Prefetch Postwrite engine is enabled. |
6 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
5-4 | WAITPINSELECTOR | R/W | 0h |
Select which wait pin edge detector should start the engine in synchronized mode 0h (R/W) = Selects Wait0 EdgeDetection 1h (R/W) = Selects Wait1 EdgeDetection 2h (R/W) = Reserved 3h (R/W) = Reserved |
3 | SYNCHROMODE | R/W | 0h |
Selects when the engine starts the access to chip-select 0h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set 1h (R/W) = Engine starts the access to chip-select as soon as STARTENGINE is set AND wait to nonwait edge detection on the selected WAIT pin |
2 | DMAMODE | R/W | 0h |
Selects interrupt synchronization or DMA request synchronization 0h (R/W) = Interrupt synchronization is enabled. Only interrupt line is activated on FIFO threshold crossing. 1h (R/W) = DMA request synchronization is enabled. A DMA request protocol is used. |
1 | ENDIANISMTYPE | R/W | 0h | Selects endianism for prefetch data 0h = Little endian 1h = Big endian |
0 | ACCESSMODE | R/W | 0h |
Selects prefetch read or write-posting accesses 0h (R/W) = Prefetch read mode 1h (R/W) = Write-posting mode |
GPMC_PREFETCH_CONFIG2 is shown in Figure 12-1682 and described in Table 12-3317.
Prefetch engine configuration 2
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TRANSFERCOUNT | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
13-0 | TRANSFERCOUNT | R/W | 0h |
Selects the number
of bytes to be read or written by the engine to the selected
chip-select |
GPMC_PREFETCH_CONTROL is shown in Figure 12-1683 and described in Table 12-3319.
Prefetch engine control
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STARTENGINE | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
0 | STARTENGINE | R/W | 0h |
Resets the FIFO pointer and starts the engine Write: 0h = Stops the engine. 1h = Resets the FIFO pointer to 0h in prefetch mode and 40h in Postwrite mode and starts the engine. Read: 0h = Engine is stopped. 1h = Engine is running. |
GPMC_PREFETCH_STATUS is shown in Figure 12-1684 and described in Table 12-3321.
Prefetch engine status
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FIFOPOINTER | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FIFOTHRESHOLDSTATUS | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | COUNTVALUE | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNTVALUE | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0. |
30-24 | FIFOPOINTER | R | 0h |
Number of
available bytes to be read or number of free empty byte places
to be written |
23-17 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
16 | FIFOTHRESHOLDSTATUS | R | 0h |
Set when FIFOPointer exceeds FIFOThreshold value 0h (R) = FIFOPointer smaller or equal to FIFOThreshold. Writing to this bit has no effect. 1h (R) = FIFOPointer greater than FIFOThreshold. Writing to this bit has no effect. |
15-14 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
13-0 | COUNTVALUE | R | 0h |
Number of
remaining bytes to be read or to be written by the engine
according to the TransferCount value |
GPMC_ECC_CONFIG is shown in Figure 12-1685 and described in Table 12-3323.
ECC configuration
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ECCALGORITHM | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ECCBCHTSEL | ECCWRAPMODE | |||||
R-0h | R/W-1h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC16B | ECCTOPSECTOR | ECCCS | ECCENABLE | ||||
R/W-0h | R/W-3h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
16 | ECCALGORITHM | R/W | 0h |
ECC algorithm used 0h (R/W) = Hamming code 1h (R/W) = BCH code |
15-14 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
13-12 | ECCBCHTSEL | R/W | 1h |
Error correction capability used for BCH 0h (R/W) = Up to 4 bits error correction (t = 4) 1h (R/W) = Up to 8 bits error correction (t = 8) 2h (R/W) = Up to 16 bits error correction (t = 16) 3h (R/W) = Reserved |
11-8 | ECCWRAPMODE | R/W | 0h |
Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details |
7 | ECC16B | R/W | 0h |
Selects an ECC calculated on 16 columns 0h (R/W) = ECC calculated on 8 columns 1h (R/W) = ECC calculated on 16 columns |
6-4 | ECCTOPSECTOR | R/W | 3h |
Number of sectors
to process with the BCH algorithm 1h = 2 sectors |
3-1 | ECCCS | R/W | 0h |
Selects the CS where ECC is computed 0h (R/W) = CS0 1h (R/W) = CS1 2h (R/W) = CS2 3h (R/W) = CS3 Other: Reserved |
0 | ECCENABLE | R/W | 0h |
Enables the ECC feature 0h (R/W) = ECC disabled 1h (R/W) = ECC enabled |
GPMC_ECC_CONTROL is shown in Figure 12-1686 and described in Table 12-3325.
ECC control
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ECCCLEAR | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ECCPOINTER | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
8 | ECCCLEAR | R/W | 0h |
Clear all ECC
result registers |
7-4 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
3-0 | ECCPOINTER | R/W | 0h |
Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Writing other values disables the ECC engine (ECCENABLE bit of GPMC_ECC_CONFIG set to 0) 0h (R/W) = Writing 0h disables the ECC engine (ECCENABLE bit of GPMC_ECC_CONFIG set to 0) 1h (R/W) = ECC result register 1 selected 2h (R/W) = ECC result register 2 selected 3h (R/W) = ECC result register 3 selected 4h (R/W) = ECC result register 4 selected 5h (R/W) = ECC result register 5 selected 6h (R/W) = ECC result register 6 selected 7h (R/W) = ECC result register 7 selected 8h (R/W) = ECC result register 8 selected 9h (R/W) = ECC result register 9 selected |
GPMC_ECC_SIZE_CONFIG is shown in Figure 12-1687 and described in Table 12-3327.
ECC size
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 01FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECCSIZE1 | |||||||
R/W-3FFh | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ECCSIZE1 | ECCSIZE0 | ||||||
R/W-3FFh | R/W-3FFh | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ECCSIZE0 | RESERVED | ECC9RESULTSIZE | |||||
R/W-3FFh | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC8RESULTSIZE | ECC7RESULTSIZE | ECC6RESULTSIZE | ECC5RESULTSIZE | ECC4RESULTSIZE | ECC3RESULTSIZE | ECC2RESULTSIZE | ECC1RESULTSIZE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | ECCSIZE1 | R/W | 3FFh |
Defines ECC size
1. |
21-12 | ECCSIZE0 | R/W | 3FFh |
Defines ECC size
0. |
11-9 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
8 | ECC9RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 9 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
7 | ECC8RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 8 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
6 | ECC7RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 7 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
5 | ECC6RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 6 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
4 | ECC5RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 5 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
3 | ECC4RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 4 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
2 | ECC3RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 3 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
1 | ECC2RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 2 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
0 | ECC1RESULTSIZE | R/W | 0h |
Selects ECC size for ECC 1 result register 0h (R/W) = ECCSIZE0 selected 1h (R/W) = ECCSIZE1 selected |
GPMC_ECCj_RESULT (where j = 0 to 8) is shown in Figure 12-1688 and described in Table 12-3329.
ECC result register
Offset = 200h + (j * 4h), where: j = 0 to 8
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0200h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | P2048O | P1024O | P512O | P256O | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
P128O | P64O | P32O | P16O | P8O | P4O | P2O | P1O |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | P2048E | P1024E | P512E | P256E | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P128E | P64E | P32E | P16E | P8E | P4E | P2E | P1E |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
27 | P2048O | R | 0h |
Odd row parity bit 2048, only used for ECC computed on 512 bytes |
26 | P1024O | R | 0h |
Odd row parity bit 1024 |
25 | P512O | R | 0h |
Odd row parity bit 512 |
24 | P256O | R | 0h |
Odd row parity bit 256 |
23 | P128O | R | 0h |
Odd row parity bit 128 |
22 | P64O | R | 0h |
Odd row parity bit 64 |
21 | P32O | R | 0h |
Odd row parity bit 32 |
20 | P16O | R | 0h |
Odd row parity bit 16 |
19 | P8O | R | 0h |
Odd row parity bit 8 |
18 | P4O | R | 0h |
Odd Column Parity bit 4 |
17 | P2O | R | 0h |
Odd Column Parity bit 2 |
16 | P1O | R | 0h |
Odd Column Parity bit 1 |
15-12 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
11 | P2048E | R | 0h |
Even row parity bit 2048, only used for ECC computed on 512 bytes |
10 | P1024E | R | 0h |
Even row parity bit 1024 |
9 | P512E | R | 0h |
Even row parity bit 512 |
8 | P256E | R | 0h |
Even row parity bit 256 |
7 | P128E | R | 0h |
Even row parity bit 128 |
6 | P64E | R | 0h |
Even row parity bit 64 |
5 | P32E | R | 0h |
Even row parity bit 32 |
4 | P16E | R | 0h |
Even row parity bit 16 |
3 | P8E | R | 0h |
Even row parity bit 8 |
2 | P4E | R | 0h |
Even column parity bit 4 |
1 | P2E | R | 0h |
Even column parity bit 2 |
0 | P1E | R | 0h |
Even column parity bit 1 |
GPMC_BCH_RESULT0_i (where i = 0 to 3) is shown in Figure 12-1689 and described in Table 12-3331.
BCH ECC result (bits 0 to 31)
Offset = 240h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0240h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_0 | R | 0h |
BCH ECC result (bits 0 to 31) |
GPMC_BCH_RESULT1_i (where i = 0 to 3) is shown in Figure 12-1690 and described in Table 12-3333.
BCH ECC result (bits 32 to 63)
Offset = 244h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0244h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_1 | R | 0h |
BCH ECC result (bits 32 to 63) |
GPMC_BCH_RESULT2_i (where i = 0 to 3) is shown in Figure 12-1691 and described in Table 12-3335.
BCH ECC result (bits 64 to 95)
Offset = 248h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0248h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_2 | R | 0h |
BCH ECC result (bits 64 to 95) |
GPMC_BCH_RESULT3_i (where i = 0 to 3) is shown in Figure 12-1692 and described in Table 12-3337.
BCH ECC result (bits 96 to 127)
Offset = 24Ch + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 024Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_3 | R | 0h |
BCH ECC result (bits 96 to 127) |
GPMC_BCH_SWDATA is shown in Figure 12-1693 and described in Table 12-3339.
This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface.
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 02D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BCH_DATA | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
15-0 | BCH_DATA | W | 0h |
Data to be
included in the BCH calculation |
GPMC_BCH_RESULT4_i (where i = 0 to 3) is shown in Figure 12-1694 and described in Table 12-3341.
BCH ECC result (bits 128 to 159)
Offset = 300h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0300h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_4 | R | 0h |
BCH ECC result (bits 128 to 159) |
GPMC_BCH_RESULT5_i (where i = 0 to 3) is shown in Figure 12-1695 and described in Table 12-3343.
BCH ECC result (bits 160 to 191)
Offset = 304h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0304h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCH_RESULT_5 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BCH_RESULT_5 | R | 0h |
BCH ECC result (bits 160 to 191) |
GPMC_BCH_RESULT6_i (where i = 0 to 3) is shown in Figure 12-1696 and described in Table 12-3345.
BCH ECC result (bits 192 to 207)
Offset = 308h + (i * 10h), where: i = 0 to 3
Instance | Physical Address |
---|---|
GPMC0_CFG | 3B00 0308h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BCH_RESULT_6 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h |
Write 0s for future compatibility. Read returns 0s. |
15-0 | BCH_RESULT_6 | R | 0h |
BCH ECC result (bits 192 to 207) |