SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes the PCIe subsystem and related application fields from an external system environment point of view.
The PCIe subsystem does not have any direct external interface pins. PCIe data transactions are implemented through the corresponding SERDES interface pins.
Table 12-1451 describes the SERDES signal names at device level related to PCIe subsystem and specifies their functions. For more information on the SERDES operation and interface signals, refer to Section 12.2.3, Serializer/Deserializer (SerDes).
Device Level Signal | I/O(1) | Description |
---|---|---|
PCIE1 Subsystem | ||
PCIE0_RX0_N | I | PCIe Lane 0 Receive Differential Data (-) |
PCIE0_RX0_P | I | PCIe Lane 0 Receive Differential Data (+) |
PCIE0_TX0_N | O | PCIe Lane 0 Transmit Differential Data (-) |
PCIE0_TX0_P | O | PCIe Lane 0 Transmit Differential Data (+) |
PCIE0_CLKREQn | I/O(2) | PCIe sideband signal for negotiation of L1 Substate entry/exit. The CLKREQn pin operates as an active low open-drain bi directional reference clock request pin. 1 = no request for clock; 0 = request for clock |
The PCIe interface signals are implemented through additional use of a SERDESn interface. For more information on the SERDES operation and interface signals, refer to Section 12.2.3, Serializer/Deserializer (SerDes).
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.