SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-759 lists the memory-mapped registers for the PRU_ECAP_ECAP0 registers. All register offset addresses not listed in Table 6-759 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0000h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0000h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV Physical Address | PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV Physical Address |
---|---|---|---|---|
0h | ECAP_TSCNT | Time Stamp Counter Register | 3003 0000h | 300B 0000h |
4h | ECAP_CNTPHS | Counter Phase Control Register | 3003 0004h | 300B 0004h |
8h | ECAP_CAP1 | Capture-1 Register | 3003 0008h | 300B 0008h |
Ch | ECAP_CAP2 | Capture-2 Register | 3003 000Ch | 300B 000Ch |
10h | ECAP_CAP3 | Capture-3 Register | 3003 0010h | 300B 0010h |
14h | ECAP_CAP4 | Capture-4 Register | 3003 0014h | 300B 0014h |
28h | ECAP_ECCTL2_ECCTL1 | ECAP Control Register 1 | 3003 0028h | 300B 0028h |
2Ch | ECAP_ECFLG_ECEINT | ECAP Interrupt Enable Register | 3003 002Ch | 300B 002Ch |
30h | ECAP_ECCLR | ECAP Interrupt Clear Register | 3003 0030h | 300B 0030h |
34h | ECAP_ECFRC | ECAP Interrupt Forcing Register | 3003 0034h | 300B 0034h |
5Ch | ECAP_PID | ECAP Peripheral Id Register | 3003 005Ch | 300B 005Ch |
ECAP_TSCNT is shown in Figure 6-391 and described in Table 6-761.
Return to Summary Table.
Time Stamp Counter Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0000h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TSCNT | R/W | 0h | Active 32-bit counter register which is used as the capture time-base. |
ECAP_CNTPHS is shown in Figure 6-392 and described in Table 6-763.
Return to Summary Table.
Counter Phase Control Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0004h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNTPHS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CNTPHS | R/W | 0h | Counter phase value register that can be programmed for phase lag/lead. This register shadows ECAP_TSCNT and is loaded into ECAP_TSCNT upon either a SYNCI event or software force via a control bit. Used to achieve phase control synchronization with respect to other ECAP and EPWM time-bases. |
ECAP_CAP1 is shown in Figure 6-393 and described in Table 6-765.
Return to Summary Table.
Capture-1 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0008h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP1 | R/W | 0h | This register can be loaded (written) by the following: a) Time-stamp (that is, counter value) during a capture event. b) Software may be useful for test purposes/initialization. c) APRD shadow register (that is, ECAP_CAP3) when used in APWM mode. |
ECAP_CAP2 is shown in Figure 6-394 and described in Table 6-767.
Return to Summary Table.
Capture-2 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 000Ch |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP2 | R/W | 0h | This register can be loaded (written) by the following: a) Time-stamp (that is, counter value) during a capture event. b) Software may be useful for test purposes. c) ACMP shadow register (that is, ECAP_CAP4) when used in APWM mode. |
ECAP_CAP3 is shown in Figure 6-395 and described in Table 6-769.
Return to Summary Table.
Capture-3 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0010h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP3 | R/W | 0h | In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APER) register. User updates the PWM period value via this register. In this mode ECAP_CAP3 (APRD) shadows ECAP_CAP1. |
ECAP_CAP4 is shown in Figure 6-396 and described in Table 6-771.
Return to Summary Table.
Capture-4 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0014h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP4 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP4 | R/W | 0h | In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. User updates the PWM compare value via this register. In this mode ECAP_CAP4 (ACMP) shadows ECAP_CAP2. |
ECAP_ECCTL2_ECCTL1 is shown in Figure 6-397 and described in Table 6-773.
Return to Summary Table.
ECAP Control Register 1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0028h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FILTER | APWMPOL | CAP_APWM | SWSYNC | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SYNCO_SEL | SYNCI_EN | TSCNTSTP | REARM_RESET | STOPVALUE | CONT_ONESHT | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-3h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FREE | SOFT | EVTFLTPS | CAPLDEN | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRRST4 | CAP4POL | CTRRST3 | CAP3POL | CTRRST2 | CAP2POL | CTRRST1 | CAP1POL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | FILTER | R | 0h | |
26 | APWMPOL | R/W | 0h | APWM output polarity select: 0h = Output is active high (that is, compare value defines high time) 1h = Output is active low (that is, compare value defines low time) Note: This is applicable only in APWM operating mode. |
25 | CAP_APWM | R/W | 0h | CAP/APWM operating mode select: 0h = ECAP module operates in capture mode. This mode forces the following configuration: a) Inhibits ECAP_TSCNT resets via CTR = PRD event b) Inhibits shadow loads on ECAP_CAP1 and ECAP_CAP2 registers. c) Permits user to enable ECAP_CAP1 to ECAP_CAP4 register load. d) ECAP input/APWM output pin operates as a capture input. 1h = ECAP module operates in APWM mode. This mode forces the following configuration: a) Resets TSCNT on CTR = PRD event (period boundary). b) Permits shadow loading on ECAP_CAP1 and ECAP_CAP2 registers. c) Disables loading of time-stamps into ECAP_CAP1 to ECAP_CAP4 registers. d) ECAP input/APWM output pin operates as a APWM output. |
24 | SWSYNC | R/W | 0h | Software forced counter (ECAP_TSCNT) synchronizing: 0h = Writing a zero has no effect will always return a zero 1h = Writing a one will force a ECAP_TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0b00. After writing a one this bit returns to a zero. Note: This provides a convenient software method to synchronize some or all ECAP timebases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. |
23-22 | SYNCO_SEL | R/W | 0h | Sync-out select: 0h = Select sync-in event to be the sync-out signal (pass through) 1h = Select CTR = PRD event to be the sync-out signal 2h = Disable sync out signal 3h = Disable sync out signal Note: Selection CTR = PRD is meaningful only in APWM mode, however can still be chosen in CAP mode, if user believes it to be useful. |
21 | SYNCI_EN | R/W | 0h | Counter (ECAP_TSCNT) sync-in select mode: 0h = Disable sync-in option 1h = Enable counter (ECAP_TSCNT) to be loaded from ECAP_CNTPHS register upon either a SYNCI signal or a software force event |
20 | TSCNTSTP | R/W | 0h | Counter stop (freeze) control: 0h = Counter stopped 1h = Counter free running |
19 | REARM_RESET | R/W | 0h | One-shot re-arming, that is, wait for stop trigger: 0h = Writing a zero has no effect (reading always returns a 0) 1h = Writing a one arms the one-shot sequence as follows: 1) resets the mod4 counter to zero 2) un-freezes the mod4 counter 3) enables capture register loads Note: The re-arm function is valid in oneshot or continuous mode. |
18-17 | STOPVALUE | R/W | 3h | Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen, that is, capture sequence is stopped. 0h = Stop after capture event 1 1h = Stop after capture event 2 2h = Stop after capture event 3 3h = Stop after capture event 4 Note: STOPVALUE is compared to mod4 counter, and when equal, the following two actions occur: (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. Note: In one shot mode, further interrupt events are blocked until re-armed, once the number of events captured has been reached . |
16 | CONT_ONESHT | R/W | 0h | Continuous or one-shot mode control (applicable only in capture mode): 0h = Operate in continuous mode 1h = Operate in one-shot mode |
15 | FREE | R/W | 0h | Emulation control. 0h = ECAP_TSCNT counter stops immediately on emulation suspend 1h = ECAP_TSCNT counter runs until = 0 0b1x = ECAP_TSCNT counter is unaffected by emulation suspend (run free) |
14 | SOFT | R/W | 0h | Emulation control. 0h = ECAP_TSCNT counter stops immediately on emulation suspend 1h = ECAP_TSCNT counter runs until = 0 0b1x = ECAP_TSCNT counter is unaffected by emulation suspend (run free) |
13-9 | EVTFLTPS | R/W | 0h | Event filter prescale select: 0h = Divide by 1 (that is, no prescale, by-pass the prescaler) 1h = Divide by 2 2h = Divide by 4 3h = Divide by 6 4h = Divide by 8 5h = Divide by 10 1Eh = Divide by 60 1Fh = Divide by 62 |
8 | CAPLDEN | R/W | 0h | Enable loading of CAP(1-4) registers on a capture event: 0h = Disable CAP (1-4) register loads at capture event time 1h = Enable CAP(1-4) register loads at capture event time |
7 | CTRRST4 | R/W | 0h | Counter reset on capture event 4: 0h = Do not reset counter on capture event 4 (absolute time stamp) 1h = Reset counter after event 4 time-stamp has been captured (used in difference mode operation) |
6 | CAP4POL | R/W | 0h | Capture event 4 polarity select: 0h = Capture event 4 triggered on a rising edge (RE) 1h = Capture event 4 triggered on a falling edge (FE) |
5 | CTRRST3 | R/W | 0h | Counter reset on capture event 3: 0h = Do not reset counter on capture event 3 (absolute time stamp) 1h = Reset counter after event 3 time-stamp has been captured (used in difference mode operation) |
4 | CAP3POL | R/W | 0h | Capture event 3 polarity select: 0h = Capture event 3 triggered on a rising edge (RE) 1h = Capture event 3 triggered on a falling edge (FE) |
3 | CTRRST2 | R/W | 0h | Counter reset on capture event 2: 0h = Do not reset counter on capture event 2 (absolute time stamp) 1h = Reset counter after event 2 time-stamp has been captured (used in difference mode operation) |
2 | CAP2POL | R/W | 0h | Capture event 2 polarity select: 0h = Capture event 2 triggered on a rising edge (RE) 1h = Capture event 2 triggered on a falling edge (FE) |
1 | CTRRST1 | R/W | 0h | Counter reset on capture event 1: 0h = Do not reset counter on capture event 1 (absolute time stamp) 1h = Reset counter after event 1 time-stamp has been captured (used in difference mode operation) |
0 | CAP1POL | R/W | 0h | Capture event 1 polarity select: 0h = Capture event 1 triggered on a rising edge (RE) 1h = Capture event 1 triggered on a falling edge (FE) |
ECAP_ECFLG_ECEINT is shown in Figure 6-398 and described in Table 6-775.
Return to Summary Table.
ECAP Interrupt Enable Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 002Ch |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FLAG_RESV0 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLAG_CMPEQ | FLAG_PRDEQ | FLAG_CNTOVF | FLAG_CEVT4 | FLAG_CEVT3 | FLAG_CEVT2 | FLAG_CEVT1 | FLAG_INT |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EN__RESV1 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_CMPEQ | EN_PRDEQ | EN_CNTOVF | EN_CEVT4 | EN_CEVT3 | EN_CEVT2 | EN_CEVT1 | EN_RESV0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | FLAG_RESV0 | R | 0h | |
23 | FLAG_CMPEQ | R | 0h | Compare equal status flag: 0h = Indicates no event occurred 1h = Indicates the counter (ECAP_TSCNT) reached the compare register value (ACMP) Note: This flag is only active in APWM mode. |
22 | FLAG_PRDEQ | R | 0h | Period equal status flag: 0h = Indicates no event occurred 1h = Indicates the counter (ECAP_TSCNT) reached the period register value (APER) and was reset Note: This flag is only active in APWM mode. |
21 | FLAG_CNTOVF | R | 0h | Counter overflow status flag: 0h = Indicates no event occurred 1h = Indicates the counter (ECAP_TSCNT) has made the transition from FFFFFFFFh to 00000000h Note: This flag is active in CAP and APWM mode. |
20 | FLAG_CEVT4 | R | 0h | Capture event 4 status flag: 0h = Indicates no event occurred 1h = Indicates the fourth event occurred at ECAPx pin Note: This flag is only active in CAP mode. |
19 | FLAG_CEVT3 | R | 0h | Capture event 3 status flag: 0h = Indicates no event occurred 1h = Indicates the third event occurred at ECAPx pin Note: This flag is only active in CAP mode. |
18 | FLAG_CEVT2 | R | 0h | Capture event 2 status flag: 0h = Indicates no event occurred 1h = Indicates the second event occurred at ECAPx pin Note: This flag is only active in CAP mode. |
17 | FLAG_CEVT1 | R | 0h | Capture event 1 status flag: 0h = Indicates no event occurred 1h = Indicates the first event occurred at ECAPx pin Note: This flag is only active in CAP mode. |
16 | FLAG_INT | R | 0h | Global interrupt status flag: 0h = Indicates no interrupt generated 1h = Indicates that an interrupt was generated from one of the following events |
15-8 | EN__RESV1 | R | 0h | |
7 | EN_CMPEQ | R/W | 0h | Compare equal interrupt enable: 0h = Disable compare equal as an interrupt source 1h = Enable compare equal as an interrupt source |
6 | EN_PRDEQ | R/W | 0h | Period equal interrupt enable: 0h = Disable period equal as an interrupt source 1h = Enable period equal as an interrupt source |
5 | EN_CNTOVF | R/W | 0h | Counter overflow interrupt enable: 0h = Disable counter overflow as an interrupt source 1h = Enable counter overflow as an interrupt source |
4 | EN_CEVT4 | R/W | 0h | Capture event 4 interrupt enable: 0h = Disable capture event 1 as an interrupt source 1h = Enable capture event 1 as an interrupt source |
3 | EN_CEVT3 | R/W | 0h | Capture event 3 interrupt enable: 0h = Disable capture event 1 as an interrupt source 1h = Enable capture event 1 as an interrupt source |
2 | EN_CEVT2 | R/W | 0h | Capture event 2 interrupt enable: 0h = Disable capture event 1 as an interrupt source 1h = Enable capture event 1 as an interrupt source |
1 | EN_CEVT1 | R/W | 0h | Capture event 1 interrupt enable: 0h = Disable capture event 1 as an interrupt source 1h = Enable capture event 1 as an interrupt source |
0 | EN_RESV0 | R | 0h |
ECAP_ECCLR is shown in Figure 6-399 and described in Table 6-777.
Return to Summary Table.
ECAP Interrupt Clear Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0030h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
_RESV0 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | INT |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | _RESV0 | R | 0h | |
7 | CMPEQ | R/W | 0h | Compare equal status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
6 | PRDEQ | R/W | 0h | Period equal status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
5 | CNTOVF | R/W | 0h | Counter overflow status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
4 | CEVT4 | R/W | 0h | Capture event 4 status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
3 | CEVT3 | R/W | 0h | Capture event 3 status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
2 | CEVT2 | R/W | 0h | Capture event 2 status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
1 | CEVT1 | R/W | 0h | Capture event 1 status flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the status flag condition |
0 | INT | R/W | 0h | Global interrupt clear flag: 0h = Writing a 0 has no effect. Always reads back a 0. 1h = Writing a 1 clears the clear flag and enable further interrupts to be generated if any of the clear flags are set to 1 |
ECAP_ECFRC is shown in Figure 6-400 and described in Table 6-779.
Return to Summary Table.
ECAP Interrupt Forcing Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 0034h |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
_RESV1 | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPEQ | PRDEQ | CNTOVF | CEVT4 | CEVT3 | CEVT2 | CEVT1 | _RESV0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | _RESV1 | R | 0h | |
7 | CMPEQ | R/W | 0h | Force compare equal: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the the CMPEQ flag bit |
6 | PRDEQ | R/W | 0h | Force period equal: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the PRDEQ flag bit |
5 | CNTOVF | R/W | 0h | Force counter overflow: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the CNTOVF flag bit |
4 | CEVT4 | R/W | 0h | Force capture event 4: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the CEVT4 flag bit |
3 | CEVT3 | R/W | 0h | Force capture event 3: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the CEVT3 flag bit |
2 | CEVT2 | R/W | 0h | Force capture event 2: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the CEVT2 flag bit |
1 | CEVT1 | R/W | 0h | Force capture event 1: 0h = Writing of 0 is ignored. Always reads back a 0. 1h = Writing a 1 sets the CEVT1 flag bit |
0 | _RESV0 | R | 0h |
ECAP_PID is shown in Figure 6-401 and described in Table 6-781.
Return to Summary Table.
ECAP Peripheral Id Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV | 3003 005Ch |
PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV | 300B 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVID | |||||||||||||||||||||||||||||||
R-44D22100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVID | R | 44D22100h | TI internal data. |