SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The Peripheral Interface’s I/Os are multiplexed with the PRU GPI/GPO signals, as shown in Table 6-422. The PR1_PRU<n>_GP_MUX_SEL bitfield in the ICSSG_GPCFG0_REG register (PRU0 or PRU1) must be set to 1h for configure the GPI/GPO signals for Peripheral I/F mode.
Pad Names at Device Level(2)(3) | Peripheral I/F Mode (ICSSG_GPCFG0_REG[29-26] PR1_PRU0_GP_MUX_SEL = 1h) |
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PRG<k>_PRU<n>_GPI0 | |
PRG<k>_PRU<n>_GPI1 | |
PRG<k>_PRU<n>_GPI2 | |
PRG<k>_PRU<n>_GPI3 | |
PRG<k>_PRU<n>_GPI4 | |
PRG<k>_PRU<n>_GPI5 | |
PRG<k>_PRU<n>_GPI6 | |
PRG<k>_PRU<n>_GPI7 | |
PRG<k>_PRU<n>_GPI8 | |
PRG<k>_PRU<n>_GPI9 | PERIF0_IN |
PRG<k>_PRU<n>_GPI10 | PERIF1_IN |
PRG<k>_PRU<n>_GPI11 | PERIF2_IN |
PRG<k>_PRU<n>_GPI12 | |
PRG<k>_PRU<n>_GPI13 | |
PRG<k>_PRU<n>_GPI14 | |
PRG<k>_PRU<n>_GPI15 | |
PRG<k>_PRU<n>_GPI16 | |
PRG<k>_PRU<n>_GPI17 | |
PRG<k>_PRU<n>_GPI18 | |
PRG<k>_PRU<n>_GPI19 | |
PRG<k>_PRU<n>_GPO0 | PERIF0_CLK |
PRG<k>_PRU<n>_GPO1 | PERIF0_OUT |
PRG<k>_PRU<n>_GPO2 | PERIF0_OUT_EN |
PRG<k>_PRU<n>_GPO3 | PERIF1_CLK |
PRG<k>_PRU<n>_GPO4 | PERIF1_OUT |
PRG<k>_PRU<n>_GPO5 | PERIF1_OUT_EN |
PRG<k>_PRU<n>_GPO6 | PERIF2_CLK |
PRG<k>_PRU<n>_GPO7 | PERIF2_OUT |
PRG<k>_PRU<n>_GPO8 | PERIF2_OUT_EN |
PRG<k>_PRU<n>_GPO9 | |
PRG<k>_PRU<n>_GPO10 | |
PRG<k>_PRU<n>_GPO11 | |
PRG<k>_PRU<n>_GPO12 | |
PRG<k>_PRU<n>_GPO13 | |
PRG<k>_PRU<n>_GPO14 | |
PRG<k>_PRU<n>_GPO15 | |
PRG<k>_PRU<n>_GPO16 | |
PRG<k>_PRU<n>_GPO17 | |
PRG<k>_PRU<n>_GPO18 | |
PRG<k>_PRU<n>_GPO19 |
A block diagram for the Peripheral I/F is included in Figure 6-195. As shown, each channel is composed of four I/Os: