SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
A single SDIO_LDO module is integrated in the device MAIN domain - SDIO_LDO0.
Figure 5-407 shows module top-level overview.
Control of SDIO_LDO to enable 1.8 V signaling is based upon the V1P8_SIGNAL_ENA input value. SDIO_LDO generates a 1.8v or 3.3v output depending on V1P8_SIGNAL_ENA. When V1P8_SIGNAL_ENA = 0, CAP_VDDS_MMC1 = 3.3V (Switch Mode) and when V1P8_SIGNAL_ENA = 1, CAP_VDDS_MMC1 = 1.8V (LDO Mode). See MMCSD1_HOST_CONTROL2 Register.