SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Spread Spectrum Modulation (SSMOD) modules on the device reduces Electro Magnetic Interference (EMI). It is a fully-digital circuit, used to modulate the frequency of the selected fractional PLLs. Programming options include selection of center spread or down spread, modulation depth, and modulation shape. The default modulation profile is triangular.
All PLLs in this family of device have SSMOD module.
SSMOD in the PLL is performed by changing the feedback divider (FRAC and FB_DIV) in a triangular pattern. This varies the frequency of the output clock in a triangular pattern. The frequency of this pattern is the modulation frequency (fm). It is programmed as a ratio of the CLKIN/4.
Figure 5-496 shows a diagram of the spreading generation block.
Δf is the deviation from the center frequency. The total spreading deviation is equal to twice Δf. The peak (ΔM) or the amplitude of the triangular/square pattern as a percent of M would be equal to the percent of the frequency spread (Δf), ΔM/M = Δf/fc.
fc is the original output clock frequency.
fm is the spreading frequency.
This additional block generates the required waveform used to reduce EMI. This waveform is then modulated with the initial signal to add some controlled deviation to the clock signal frequency, which spreads the energy of the clock and its harmonics into a band of frequencies, and then reduces EMI. SSMOD_DOWNSPREAD can control the position of the generated signal. It is controlled by the <PLL_name>_CTRL[4] DOWNSPREAD_EN bit of the corresponding registers. If the DOWNSPREAD_EN bit is set to 1, the frequency spread on the lower side is twice the programmed value. The frequency spread on the higher side is 0.
The
value of SSMOD_FREQ controls the rate of the
generated signal. It can be programmed as a ratio
of the reference clock: fref / 4. The
value that must be programmed is calculated as
follows:
ModFreqDivider = fref / (4 ×
fm), where fm <
fref / 70, fref =
finp / (1+N), and finp is
the input clock for the PLL.