The IEP timer supports the following
features:
- One controller 64-bit
count-up counter with an overflow status bit.
- Runs on ICSSG_IEP_CLK or
ICSSG_ICLK clock.
- Write 1h to clear
status.
- Supports a programmable
increment value from 1 to 16 (default 5).
- An optional compensation
method allows the increment value to apply compensation increment value
from 1 to 16 count up to 224 ICSSG_IEP_CLK events with
additional slow compensation mode.
- 10× 64-bit capture
registers:
- 8 capture inputs, with
optional synchronous or asynchronous mode:
- 16× 64-bit
compare registers: IEP_CMPj_REG0/ IEP_CMPj_REG1 (where j = 0 to 15) and
IEP_CMP_STATUS_REG[15-0] CMP_STATUS
- 16 status bits,
write 1h to clear
- 16 individual
event outputs
- One global event output
for interrupt generation triggered by any compare event
- 32 outputs, one
high-level and one high-pulse for each compare hit event
- IEP_CMP_CFG_REG[0]
CMP0_RST_CNT_EN, if enabled, will reset the controller counter on the next
ICSSG_IEP_CLK/ ICSSG_ICLK cycle
- EHRPWM0_SYNCO/ EHRPWM3_SYNCO, if
enabled, will reset the controller counter on the next ICSSG_IEP_CLK/ ICSSG_ICLK
cycle
- Controller counter reset-state is
programmable
- Optional 32-bit shadow mode of
operation, which can be configured through IEP_CMP_CFG_REG[17]
SHADOW_EN bit
- Self-clear CMP_STATUS_REG if
ICSSG_SA_MX_REG[16] PWM_EFC_EN is set