SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
MCU_OBSCLK0 output is controlled by CTRLMMR_MCU_OBSCLK_CTRL register in the MCU_CTRL_MMR0 module; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR). Two muxes are connected in series - MCU_OBSCLK0_MUX0 and MCU_OBSCLK0_MUX1, see Figure 5-488.
How to select the output of MCU_OBSCLK0_MUX1 is described in Table 5-983.
CTRLMMR_MCU_OBSCLK_CTRL(2)[2-0] CLK_SEL | MCU_OBSCLK0_MUX1 Output Clock Selection(1) |
---|---|
0x0 | MCU_CLK_12M_RC |
0x1 | 0 (GND)(3) |
0x2 | MCU_PLL0_HSDIV0_CLKOUT |
0x3 | MCU_PLL0_HSDIV4_CLKOUT |
0x4 | MCU_PLLCTRL_OBSCLK |
0x5 | CLK_32K |
0x6 | MCU_HFOSC0_CLKOUT |
0x7 | MCU_HFOSC0_CLKOUT_32K |
The value of the software-controlled 4-bit divider is determined by the CTRLMMR_MCU_OBSCLK_CTRL[11-8] CLK _DIV field; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR).