SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
For detailed DCC compute calculations, refer to Continuous Monitor of the PLL Frequency With the DCC App Note.
The DCC has two parallel counters that count clock pulses for two independent clock sources:
The error signal is generated by any one of the following conditions:
Any of these errors causes the counters to stop counting. An application must then read out the counter values to determine what caused the error. Once the error is detected, the counters are stopped. It would take multiple clocks(2-3 in each clock domain i.e. source & VBUSP_CLK) to stop the counters due the cross clock domain synchronisations. Counters can be configured in a mode to reload and continue down-counting despite error so successive error event is not missed. Error is reported as exception and application is expected to read the counter values for determining quantum & direction of error.
Reloads or restarts occur under two conditions:
The DCC module does not check jitter for Clock0 or Clock1.
As the counter preset signal is synchronized to either of the source clock domains, the counters begin downcounting after two corresponding source clock cycles.
The error signal is to be captured to the VBUSP_CLK domain. There is 1 VBUSP_CLK period uncertainty on either side of the fixed width counting window (VALID0) in generating the error signal since the counters work in a different clock domain. This should be accounted for, when setting the count value for VALID0.
Operating the DCC with ‘0’ in the COUNTSEED1 or COUNTSEED0 or VALIDSEED0 register will result in undefined operation
Figure 12-2506 through Figure 12-2510 shows examples of counters relationship and error generation.