SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 12-2195 shows the ECAP integration.
There are three instances of the Enhanced Capture (ECAP) module integrated in the device.
Table 12-4267 through Table 12-4270 summarize the integration of ECAP0, ECAP1 and ECAP2 modules in device MAIN domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
ECAP0 | PSC0 | PD0 | LPSC0 | CBASS0 |
ECAP1 | PSC0 | PD0 | LPSC0 | CBASS0 |
ECAP2 | PSC0 | PD0 | LPSC0 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
ECAP0 | ECAP0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | ECAP0 functional and interface clock |
ECAP1 | ECAP1_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | ECAP1 functional and interface clock |
ECAP2 | ECAP2_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | ECAP2 functional and interface clock |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
ECAP0 | ECAP0_RST | MOD_G_RST | LPSC0 | Module Reset |
ECAP1 | ECAP1_RST | MOD_G_RST | LPSC0 | Module Reset |
ECAP2 | ECAP2_RST | MOD_G_RST | LPSC0 | Module Reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
ECAP0 | ECAP0_ECAP_INT_0 | GICSS0_SPI_IN_145 | COMPUTE_CLUSTER0 | ECAP0 interrupt | Pulse |
PRU_ICSSG0_PR1_SLV_IN_8 | PRU_ICSSG0 | ||||
PRU_ICSSG1_PR1_SLV_IN_8 | PRU_ICSSG1 | ||||
R5FSS0_CORE0_INTR_IN_140 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_140 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_140 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_140 | R5FSS1_CORE1 | ||||
ECAP1 | ECAP1_ECAP_INT_0 | GICSS0_SPI_IN_146 | COMPUTE_CLUSTER0 | ECAP1 interrupt | Pulse |
PRU_ICSSG0_PR1_SLV_IN_9 | PRU_ICSSG0 | ||||
PRU_ICSSG1_PR1_SLV_IN_9 | PRU_ICSSG1 | ||||
R5FSS0_CORE0_INTR_IN_141 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_141 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_141 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_141 | R5FSS1_CORE1 | ||||
ECAP2 | ECAP2_ECAP_INT_0 | GICSS0_SPI_IN_147 | COMPUTE_CLUSTER0 | ECAP2 interrupt | Pulse |
PRU_ICSSG0_PR1_SLV_IN_10 | PRU_ICSSG0 | ||||
PRU_ICSSG1_PR1_SLV_IN_10 | PRU_ICSSG1 | ||||
R5FSS0_CORE0_INTR_IN_142 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_142 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_142 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_142 | R5FSS1_CORE1 |
For more information about interrupts, see Section 12.4.2.4.1.1.6, ECAP Interrupt Control.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.