SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The PRU_ICSSG UART0 peripheral is based on the industry standard TL16C550 asynchronous communications element, which in turn is a functional upgrade of the TL16C450. The information in this chapter assumes that user is familiar with these standards.
Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the PRU_ICSSG UART0 can be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.
The PRU_ICSSG UART0 performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The CPU can read the PRU_ICSSG UART0 status at any time. The PRU_ICSSG UART0 includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
The PRU_ICSSG UART0 includes a programmable baud generator capable of dividing the PRU_ICSSG UART0 input clock by divisors from 1 to 65535 and producing a 16× reference clock or a 13× reference clock for the internal transmitter and receiver logic.