SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes the A53SS integration in the device, including information about clocks, resets, and hardware requests.
A53SS Integration shows the A53SS integration.
A53SS Integration Attributes through A53SS Hardware Request summarize the A53SS integration.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
A53SS0 | Arm A53 Cluster 0 | MAIN_PSC | PD1 | LPSC20 | CBASS0 |
Arm A53 Cluster 0 Core 0 | MAIN_PSC | PD2 | LPSC22 | CBASS0 | |
Arm A53 Cluster 0 Core 1 | MAIN_PSC | PD3 | LPSC23 | CBASS0 |
Clocks | ||||
---|---|---|---|---|
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
A53SS | ARM_COREPAC_CLK | MAIN_PLL8_HSDIV0_CLKOUT | MAIN_PLL8 | A53SS clock |
Resets | |||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description | |
A53SS0 | Arm A53 Cluster 0 | ARM_COREPAC_RST | MOD_G_RST | LPSC20 | Arm A53 Cluster 0 reset |
Arm A53 Cluster 0 Core 0 | A53_CORE0_RST | MOD_G_RST | LPSC22 | Arm A53 Cluster 0 Core 0 reset | |
Arm A53 Cluster 0 Core 1 | A53_CORE1_RST | MOD_G_RST | LPSC23 | Arm A53 Cluster 0 Core 1 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
A53SS0 | A53_CORE0_DCCIRQ | GIC500_PPI0_0_INT_IN_22 | GIC0 | A53 Cluster 0 Core 0 DCC Comms Channel interrupt | Level |
A53_CORE0_PMUIRQ | GIC500_PPI0_0_INT_IN_23 | GIC0 | A53 Cluster 0 Core 0 PMU Counter Overflow interrupt | Level | |
A53_CORE0_CTIIRQ | GIC500_PPI0_0_INT_IN_24 | GIC0 | A53 Cluster 0 Core 0 Cross Trigger Interface interrupt | Level | |
GIC500_PPI0_0_INT_IN_31 | |||||
A53_CORE0_VCPUMNTIRQ | GIC500_PPI0_0_INT_IN_25 | GIC0 | A53 Cluster 0 Core 0 Virtual CPU Maintenance interrupt | Level | |
A53_CORE0_CNTHPIRQ | GIC500_PPI0_0_INT_IN_26 | GIC0 | A53 Cluster 0 Core 0 Hypervisor Timer interrupt | Level | |
A53_CORE0_CNTVIRQ | GIC500_PPI0_0_INT_IN_27 | GIC0 | A53 Cluster 0 Core 0 Virtual Timer interrupt | Level | |
A53_CORE0_CNTPSIRQ | GIC500_PPI0_0_INT_IN_29 | GIC0 | A53 Cluster 0 Core 0 Secure Physical Timer interrupt | Level | |
A53_CORE0_CNTPNSIRQ | GIC500_PPI0_0_INT_IN_30 | GIC0 | A53 Cluster 0 Core 0 Non-secure Physical Timer interrupt | Level | |
A53_CORE1_DCCIRQ | GIC500_PPI0_1_INT_IN_22 | GIC0 | A53 Cluster 0 Core 1 DCC Comms Channel interrupt | Level | |
A53_CORE1_PMUIRQ | GIC500_PPI0_1_INT_IN_23 | GIC0 | A53 Cluster 0 Core 1 PMU Counter Overflow interrupt | Level | |
A53_CORE1_CTIIRQ | GIC500_PPI0_1_INT_IN_31 | GIC0 | A53 Cluster 0 Core 1 Cross Trigger Interface interrupt | Level | |
GIC500_PPI0_1_INT_IN_24 | |||||
A53_CORE1_VCPUMNTIRQ | GIC500_PPI0_1_INT_IN_25 | GIC0 | A53 Cluster 0 Core 1 Virtual CPU Maintenance interrupt | Level | |
A53_CORE1_CNTHPIRQ | GIC500_PPI0_1_INT_IN_26 | GIC0 | A53 Cluster 0 Core 1 Hypervisor Timer interrupt | Level | |
A53_CORE1_CNTVIRQ | GIC500_PPI0_1_INT_IN_27 | GIC0 | A53 Cluster 0 Core 1 Virtual Timer interrupt | Level | |
A53_CORE1_CNTPSIRQ | GIC500_PPI0_1_INT_IN_29 | GIC0 | A53 Cluster 0 Core 1 Secure Physical Timer interrupt | Level | |
A53_CORE1_CNTPNSIRQ | GIC500_PPI0_1_INT_IN_30 | GIC0 | A53 Cluster 0 Core 1 Non-secure Physical Timer interrupt | Level | |
ARM_COREPAC_EXTERRIRQ | MAIN_ESM_LVL_EVT_IN_144 | ESM0 | Arm Cluster 0 Cache ECC Error interrupt | Level | |
ARM_COREPAC_INTERRIRQ | MAIN_ESM_LVL_EVT_IN_145 | ESM0 | Arm Cluster 0 Memory Bus Error interrupt | Level |
A53SS interrupts are further described in A53SS Interrupt Outputs, A53SS Interrupt Outputs
For more information on the interconnects, see System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Device Configuration.