Table 6-1782 lists the memory-mapped registers for the PRU_RAT_SLICE_RAT_SLICE registers. All register offset addresses not listed in Table 6-1782 should be considered as reserved locations and the register contents should not be modified.
Table 6-1781 PRU_RAT_SLICE_RAT_SLICE InstancesInstance | Base Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8000h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9000h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8000h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9000h |
Table 6-1782 PRU_ICSSG0_RAT_SLICE Registers Table 6-1783 PRU_ICSSG1_RAT_SLICE Registers 4.14.17.1 RAT_SLICE_PID Register (Offset = 0h) [reset = 66802900h]
RAT_SLICE_PID is shown in Figure 6-891 and described in Table 6-1785.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Table 6-1784 RAT_SLICE_PID InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8000h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9000h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8000h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9000h |
Figure 6-891 RAT_SLICE_PID Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1785 RAT_SLICE_PID Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-30 | SCHEME | R | 1h | RAT_SLICE_PID register scheme |
29-28 | BU | R | 2h | Business Unit: 10 = Processors |
27-16 | FUNC | R | 680h | Module ID |
15-11 | RTL | R | 5h | RTL revision. Will vary depending on release. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |
4.14.17.2 RAT_SLICE_CONFIG Register (Offset = 4h) [reset = X]
RAT_SLICE_CONFIG is shown in Figure 6-892 and described in Table 6-1787.
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The Config Register contains the configuration values for the module.
Table 6-1786 RAT_SLICE_CONFIG InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8004h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9004h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8004h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9004h |
Figure 6-892 RAT_SLICE_CONFIG Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1787 RAT_SLICE_CONFIG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-24 | RESERVED | R | X | |
23-16 | ADDR_WIDTH | R | 30h | Number of address bits |
15-8 | ADDRS | R | 3h | Number of addresses |
7-0 | REGIONS | R | 4h | Number of regions |
4.14.17.3 RAT_SLICE_CTRL_j Register (Offset = 20h + formula) [reset = X]
RAT_SLICE_CTRL_j is shown in Figure 6-893 and described in Table 6-1789.
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The Control for Region a.
Offset = 20h + (j * 10h); where j = 0h to 3h
Table 6-1788 RAT_SLICE_CTRL_j InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8020h + formula |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9020h + formula |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8020h + formula |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9020h + formula |
Figure 6-893 RAT_SLICE_CTRL_j Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1789 RAT_SLICE_CTRL_j Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31 | EN | R/W | 0h | Enable for the Region |
30-6 | RESERVED | R/W | X | |
5-0 | SIZE | R/W | 0h | Size of the Region in Address Bits. 0 = 1 byte, 1 = 2 B, 2 = 4 B, 3 = 8 B, etc. up to
32 = 4 GB.Note: The Size of the Region in Address Bits is 2 to
the power of N, where N is 0..32 |
4.14.17.4 RAT_SLICE_BASE_j Register (Offset = 24h + formula) [reset = 0h]
RAT_SLICE_BASE_j is shown in Figure 6-894 and described in Table 6-1791.
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The Base Address for Region a. This is the source address for matching to a region.
Offset = 24h + (j * 10h); where j = 0h to 3h
Table 6-1790 RAT_SLICE_BASE_j InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8024h + formula |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9024h + formula |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8024h + formula |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9024h + formula |
Figure 6-894 RAT_SLICE_BASE_j Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1791 RAT_SLICE_BASE_j Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | BASE | R/W | 0h | Base Address for the Region. It must be aligned to the programmed size. |
4.14.17.5 RAT_SLICE_TRANS_l_j Register (Offset = 28h + formula) [reset = 0h]
RAT_SLICE_TRANS_l_j is shown in Figure 6-895 and described in Table 6-1793.
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The Translated Lower Address Bits for Region a.
Offset = 28h + (j * 10h); where j = 0h to 3h
Table 6-1792 RAT_SLICE_TRANS_l_j InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8028h + formula |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9028h + formula |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8028h + formula |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9028h + formula |
Figure 6-895 RAT_SLICE_TRANS_l_j Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1793 RAT_SLICE_TRANS_l_j Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | LOWER | R/W | 0h | Translated Lower Address Bits for the Region. It must be aligned to the programmed size. |
4.14.17.6 RAT_SLICE_TRANS_U_j Register (Offset = 2Ch + formula) [reset = X]
RAT_SLICE_TRANS_U_j is shown in Figure 6-896 and described in Table 6-1795.
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The Translated Upper Address Bits for Region a.
Offset = 2Ch + (j * 10h); where j = 0h to 3h
Table 6-1794 RAT_SLICE_TRANS_U_j InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 802Ch + formula |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 902Ch + formula |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 802Ch + formula |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 902Ch + formula |
Figure 6-896 RAT_SLICE_TRANS_U_j Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1795 RAT_SLICE_TRANS_U_j Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-16 | RESERVED | R/W | X | |
15-0 | UPPER | R/W | 0h | Translated Upper Address Bits for the Region |
4.14.17.7 RAT_SLICE_DESTINATION_ID Register (Offset = 804h) [reset = X]
RAT_SLICE_DESTINATION_ID is shown in Figure 6-897 and described in Table 6-1797.
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The Destination ID Register defines the destination ID value for error messages.
Table 6-1796 RAT_SLICE_DESTINATION_ID InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8804h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9804h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8804h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9804h |
Figure 6-897 RAT_SLICE_DESTINATION_ID Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1797 RAT_SLICE_DESTINATION_ID Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-8 | RESERVED | R/W | X | |
7-0 | DEST_ID | R/W | 0h | The destination ID. |
4.14.17.8 RAT_SLICE_EXCEPTION_LOGGING_CONTROL Register (Offset = 820h) [reset = X]
RAT_SLICE_EXCEPTION_LOGGING_CONTROL is shown in
Figure 6-898 and described in Table 6-1799.
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The Exception Logging Control Register controls the exception logging.
Table 6-1798 RAT_SLICE_EXCEPTION_LOGGING_CONTROL InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8820h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9820h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8820h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9820h |
Figure 6-898 RAT_SLICE_EXCEPTION_LOGGING_CONTROL Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1799 RAT_SLICE_EXCEPTION_LOGGING_CONTROL Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R/W | X | |
1 | DISABLE_INTR | R/W | 0h | Disables logging interrupt when set. |
0 | DISABLE_F | R/W | 0h | Disables logging when set. |
4.14.17.11 RAT_SLICE_EXCEPTION_LOGGING_DATA0 Register (Offset = 82Ch) [reset = 0h]
RAT_SLICE_EXCEPTION_LOGGING_DATA0 is shown in
Figure 6-901 and described in Table 6-1805.
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The Exception Logging Data 0 Register contains the first word of the data.
Table 6-1804 RAT_SLICE_EXCEPTION_LOGGING_DATA0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 882Ch |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 982Ch |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 882Ch |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 982Ch |
Figure 6-901 RAT_SLICE_EXCEPTION_LOGGING_DATA0 Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1805 RAT_SLICE_EXCEPTION_LOGGING_DATA0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | ADDR_L | R | 0h | Address lower 32 bits. |
4.14.17.12 RAT_SLICE_EXCEPTION_LOGGING_DATA1 Register (Offset = 830h) [reset = X]
RAT_SLICE_EXCEPTION_LOGGING_DATA1 is shown in
Figure 6-902 and described in Table 6-1807.
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The Exception Logging Data 1 Register contains the second word of the data.
Table 6-1806 RAT_SLICE_EXCEPTION_LOGGING_DATA1 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8830h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9830h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8830h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9830h |
Figure 6-902 RAT_SLICE_EXCEPTION_LOGGING_DATA1 Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1807 RAT_SLICE_EXCEPTION_LOGGING_DATA1 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-16 | RESERVED | R | X | |
15-0 | ADDR_H | R | 0h | Address upper 12 bits. |
4.14.17.13 RAT_SLICE_EXCEPTION_LOGGING_DATA2 Register (Offset = 834h) [reset = X]
RAT_SLICE_EXCEPTION_LOGGING_DATA2 is shown in
Figure 6-903 and described in Table 6-1809.
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The Exception Logging Data 2 Register contains the third word of the data.
Table 6-1808 RAT_SLICE_EXCEPTION_LOGGING_DATA2 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8834h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9834h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8834h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9834h |
Figure 6-903 RAT_SLICE_EXCEPTION_LOGGING_DATA2 Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1809 RAT_SLICE_EXCEPTION_LOGGING_DATA2 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-28 | RESERVED | R | X | |
27-16 | ROUTEID | R | 0h | Route ID. |
15-14 | RESERVED | R | X | |
13 | WRITE | R | 0h | Write. |
12 | READ | R | 0h | Read. |
11 | DEBUG | R | 0h | Debug. |
10 | CACHEABLE | R | 0h | Cacheable. |
9 | PRIV | R | 0h | Priv. |
8 | SECURE | R | 0h | Secure. |
7-0 | PRIV_ID | R | 0h | Priv ID. |
4.14.17.14 RAT_SLICE_EXCEPTION_LOGGING_DATA3 Register (Offset = 838h) [reset = X]
RAT_SLICE_EXCEPTION_LOGGING_DATA3 is shown in
Figure 6-904 and described in Table 6-1811.
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The Exception Logging Data 3 Register contains the fourth word of the data. Reading this register will clear the error pending bit.
Table 6-1810 RAT_SLICE_EXCEPTION_LOGGING_DATA3 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8838h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9838h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8838h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9838h |
Figure 6-904 RAT_SLICE_EXCEPTION_LOGGING_DATA3 Register LEGEND: R = Read Only; -n = value after reset |
Table 6-1811 RAT_SLICE_EXCEPTION_LOGGING_DATA3 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-10 | RESERVED | R | X | |
9-0 | BYTECNT | R | 0h | Byte count. |
4.14.17.15 RAT_SLICE_EXCEPTION_PEND_SET Register (Offset = 840h) [reset = X]
RAT_SLICE_EXCEPTION_PEND_SET is shown in Figure 6-905 and described in Table 6-1813.
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The Exception Logging Interrupt Pending Set Register allows to set the pend signal.
Table 6-1812 RAT_SLICE_EXCEPTION_PEND_SET InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8840h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9840h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8840h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9840h |
Figure 6-905 RAT_SLICE_EXCEPTION_PEND_SET Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-1813 RAT_SLICE_EXCEPTION_PEND_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | PEND_SET | R/W1S | 0h | Write a 1 to set the exception pend signal. |
4.14.17.16 RAT_SLICE_EXCEPTION_PEND_CLEAR Register (Offset = 844h) [reset = X]
RAT_SLICE_EXCEPTION_PEND_CLEAR is shown in Figure 6-906 and described in Table 6-1815.
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The Exception Logging Interrupt Pending Clear Register allows to clear the pend signal.
Table 6-1814 RAT_SLICE_EXCEPTION_PEND_CLEAR InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8844h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9844h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8844h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9844h |
Figure 6-906 RAT_SLICE_EXCEPTION_PEND_CLEAR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 6-1815 RAT_SLICE_EXCEPTION_PEND_CLEAR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | PEND_CLR | R/W1C | 0h | Write a 1 to clear the exception pend signal. |
4.14.17.17 RAT_SLICE_EXCEPTION_ENABLE_SET Register (Offset = 848h) [reset = X]
RAT_SLICE_EXCEPTION_ENABLE_SET is shown in Figure 6-907 and described in Table 6-1817.
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The Exception Logging Interrupt Enable Set Register allows to set the interrupt enable signal.
Table 6-1816 RAT_SLICE_EXCEPTION_ENABLE_SET InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8848h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9848h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8848h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9848h |
Figure 6-907 RAT_SLICE_EXCEPTION_ENABLE_SET Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-1817 RAT_SLICE_EXCEPTION_ENABLE_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | ENABLE_SET | R/W1S | 0h | Write a 1 to set the exception interrupt enable signal. |
4.14.17.18 RAT_SLICE_EXCEPTION_ENABLE_CLEAR Register (Offset = 84Ch) [reset = X]
RAT_SLICE_EXCEPTION_ENABLE_CLEAR is shown in Figure 6-908 and described in Table 6-1819.
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The Exception Logging Interrupt Enable Clear Register allows to clear the interrupt enable signal.
Table 6-1818 RAT_SLICE_EXCEPTION_ENABLE_CLEAR InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 884Ch |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 984Ch |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 884Ch |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 984Ch |
Figure 6-908 RAT_SLICE_EXCEPTION_ENABLE_CLEAR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 6-1819 RAT_SLICE_EXCEPTION_ENABLE_CLEAR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | ENABLE_CLR | R/W1C | 0h | Write a 1 to clear the exception interrupt enable signal. |
4.14.17.19 RAT_SLICE_EOI_REG Register (Offset = 850h) [reset = X]
RAT_SLICE_EOI_REG is shown in Figure 6-909 and described in Table 6-1821.
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EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 6-1820 RAT_SLICE_EOI_REG InstancesInstance | Physical Address |
---|
PRU_ICSSG0_RAT_SLICE0_CFG | 3000 8850h |
PRU_ICSSG0_RAT_SLICE1_CFG | 3000 9850h |
PRU_ICSSG1_RAT_SLICE0_CFG | 3008 8850h |
PRU_ICSSG1_RAT_SLICE1_CFG | 3008 9850h |
Figure 6-909 RAT_SLICE_EOI_REG Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-1821 RAT_SLICE_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-16 | RESERVED | R/W | X | |
15-0 | EOI_WR | R/W | 0h | EOI Register |