SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-124 lists the memory-mapped registers for the R5FSS_CPU0_ECC_AGGR_CFG_REGS. All register offset addresses not listed in Table 6-124 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D000h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E000h |
Offset | Acronym | Register Name | R5FSS0_CORE0_ ECC_AGGR Physical Address |
---|---|---|---|
0h | R5FSS_CPU0_REV | Revision register | 3F00 D000h |
8h | R5FSS_CPU0_VECTOR | ECC vector register | 3F00 D008h |
Ch | R5FSS_CPU0_STAT | Misc status register | 3F00 D00Ch |
3Ch | R5FSS_CPU0_SEC_EOI_REG | SEC EOI register | 3F00 D03Ch |
40h | R5FSS_CPU0_SEC_STATUS_REG0 | SEC interrupt status register 0 | 3F00 D040h |
44h | R5FSS_CPU0_SEC_STATUS_REG1 | SEC interrupt status register 1 | 3F00 D044h |
80h | R5FSS_CPU0_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 3F00 D080h |
84h | R5FSS_CPU0_SEC_ENABLE_SET_REG1 | SEC interrupt enable set register 1 | 3F00 D084h |
C0h | R5FSS_CPU0_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 3F00 D0C0h |
C4h | R5FSS_CPU0_SEC_ENABLE_CLR_REG1 | SEC interrupt enable clear register 1 | 3F00 D0C4h |
13Ch | R5FSS_CPU0_DED_EOI_REG | DED EOI register | 3F00 D13Ch |
140h | R5FSS_CPU0_DED_STATUS_REG0 | DED interrupt status register 0 | 3F00 D140h |
144h | R5FSS_CPU0_DED_STATUS_REG1 | DED interrupt status register 1 | 3F00 D144h |
180h | R5FSS_CPU0_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 3F00 D180h |
184h | R5FSS_CPU0_DED_ENABLE_SET_REG1 | DED interrupt enable set register 1 | 3F00 D184h |
1C0h | R5FSS_CPU0_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 3F00 D1C0h |
1C4h | R5FSS_CPU0_DED_ENABLE_CLR_REG1 | DED interrupt enable clear register 1 | 3F00 D1C4h |
200h | R5FSS_CPU0_AGGR_ENABLE_SET | AGGR interrupt enable set register | 3F00 D200h |
204h | R5FSS_CPU0_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 3F00 D204h |
208h | R5FSS_CPU0_AGGR_STATUS_SET | AGGR interrupt status set register | 3F00 D208h |
20Ch | R5FSS_CPU0_AGGR_STATUS_CLR | AGGR interrupt status clear register | 3F00 D20Ch |
Offset | Acronym | Register Name | R5FSS1_CORE0_ ECC_AGGR Physical Address |
---|---|---|---|
0h | R5FSS_CPU0_REV | Revision register | 3F00 E000h |
8h | R5FSS_CPU0_VECTOR | ECC vector register | 3F00 E008h |
Ch | R5FSS_CPU0_STAT | Misc status register | 3F00 E00Ch |
3Ch | R5FSS_CPU0_SEC_EOI_REG | SEC EOI register | 3F00 E03Ch |
40h | R5FSS_CPU0_SEC_STATUS_REG0 | SEC interrupt status register 0 | 3F00 E040h |
44h | R5FSS_CPU0_SEC_STATUS_REG1 | SEC interrupt status register 1 | 3F00 E044h |
80h | R5FSS_CPU0_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 3F00 E080h |
84h | R5FSS_CPU0_SEC_ENABLE_SET_REG1 | SEC interrupt enable set register 1 | 3F00 E084h |
C0h | R5FSS_CPU0_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 3F00 E0C0h |
C4h | R5FSS_CPU0_SEC_ENABLE_CLR_REG1 | SEC interrupt enable clear register 1 | 3F00 E0C4h |
13Ch | R5FSS_CPU0_DED_EOI_REG | DED EOI register | 3F00 E13Ch |
140h | R5FSS_CPU0_DED_STATUS_REG0 | DED interrupt status register 0 | 3F00 E140h |
144h | R5FSS_CPU0_DED_STATUS_REG1 | DED interrupt status register 1 | 3F00 E144h |
180h | R5FSS_CPU0_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 3F00 E180h |
184h | R5FSS_CPU0_DED_ENABLE_SET_REG1 | DED interrupt enable set register 1 | 3F00 E184h |
1C0h | R5FSS_CPU0_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 3F00 E1C0h |
1C4h | R5FSS_CPU0_DED_ENABLE_CLR_REG1 | DED interrupt enable clear register 1 | 3F00 E1C4h |
200h | R5FSS_CPU0_AGGR_ENABLE_SET | AGGR interrupt enable set register | 3F00 E200h |
204h | R5FSS_CPU0_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 3F00 E204h |
208h | R5FSS_CPU0_AGGR_STATUS_SET | AGGR interrupt status set register | 3F00 E208h |
20Ch | R5FSS_CPU0_AGGR_STATUS_CLR | AGGR interrupt status clear register | 3F00 E20Ch |
R5FSS_CPU0_REV is shown in Figure 6-61 and described in Table 6-127.
Return to Summary Table.
Revision register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D000h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0E200h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0E200h | TI internal data. Identifies revision of peripheral. |
R5FSS_CPU0_VECTOR is shown in Figure 6-62 and described in Table 6-129.
Return to Summary Table.
ECC vector register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D008h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved. |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address. |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS. |
14-11 | RESERVED | R | 0h | Reserved. |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status. |
R5FSS_CPU0_STAT is shown in Figure 6-63 and described in Table 6-131.
Return to Summary Table.
Misc status register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D00Ch |
R5FSS1_CORE0_ECC_AGGR | 3F00 E00Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-24h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved. |
10-0 | NUM_RAMS | R | 24h | Indicates the number of RAMS serviced by the ECC aggregator. |
R5FSS_CPU0_SEC_EOI_REG is shown in Figure 6-64 and described in Table 6-133.
Return to Summary Table.
SEC EOI register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D03Ch |
R5FSS1_CORE0_ECC_AGGR | 3F00 E03Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved. |
0 | EOI_WR | R/W1S | 0h | EOI value. |
R5FSS_CPU0_SEC_STATUS_REG0 is shown in Figure 6-65 and described in Table 6-135.
Return to Summary Table.
SEC interrupt status register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D040h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | CPU0_VBUSM2AXI_EDC_PEND | CPU0_KS_VIM_RAMECC_PEND | B1TCM0_BANK1_PEND | B1TCM0_BANK0_PEND | B0TCM0_BANK1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_PEND | ATCM0_BANK1_PEND | ATCM0_BANK0_PEND | CPU0_DDATA_RAM7_PEND | CPU0_DDATA_RAM6_PEND | CPU0_DDATA_RAM5_PEND | CPU0_DDATA_RAM4_PEND | CPU0_DDATA_RAM3_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_PEND | CPU0_DDATA_RAM1_PEND | CPU0_DDATA_RAM0_PEND | CPU0_DDIRTY_RAM_PEND | CPU0_DTAG_RAM3_PEND | CPU0_DTAG_RAM2_PEND | CPU0_DTAG_RAM1_PEND | CPU0_DTAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_PEND | CPU0_IDATA_BANK2_PEND | CPU0_IDATA_BANK1_PEND | CPU0_IDATA_BANK0_PEND | CPU0_ITAG_RAM3_PEND | CPU0_ITAG_RAM2_PEND | CPU0_ITAG_RAM1_PEND | CPU0_ITAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for atcm0_bank1_pend |
21 | ATCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram0_pend |
R5FSS_CPU0_SEC_STATUS_REG1 is shown in Figure 6-66 and described in Table 6-137.
Return to Summary Table.
SEC interrupt status register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D044h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_PEND | SCRP_EDC_PEND | CPU0_AHB2VBUSP_EDC_PEND | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_PEND | R/W1S | 0h | Interrupt pending status for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_PEND | R/W1S | 0h | Interrupt pending status for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_SEC_ENABLE_SET_REG0 is shown in Figure 6-67 and described in Table 6-139.
Return to Summary Table.
SEC Interrupt enable set register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D080h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | CPU0_VBUSM2AXI_EDC_ENABLE_SET | CPU0_KS_VIM_RAMECC_ENABLE_SET | B1TCM0_BANK1_ENABLE_SET | B1TCM0_BANK0_ENABLE_SET | B0TCM0_BANK1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_ENABLE_SET | ATCM0_BANK1_ENABLE_SET | ATCM0_BANK0_ENABLE_SET | CPU0_DDATA_RAM7_ENABLE_SET | CPU0_DDATA_RAM6_ENABLE_SET | CPU0_DDATA_RAM5_ENABLE_SET | CPU0_DDATA_RAM4_ENABLE_SET | CPU0_DDATA_RAM3_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_ENABLE_SET | CPU0_DDATA_RAM1_ENABLE_SET | CPU0_DDATA_RAM0_ENABLE_SET | CPU0_DDIRTY_RAM_ENABLE_SET | CPU0_DTAG_RAM3_ENABLE_SET | CPU0_DTAG_RAM2_ENABLE_SET | CPU0_DTAG_RAM1_ENABLE_SET | CPU0_DTAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_ENABLE_SET | CPU0_IDATA_BANK2_ENABLE_SET | CPU0_IDATA_BANK1_ENABLE_SET | CPU0_IDATA_BANK0_ENABLE_SET | CPU0_ITAG_RAM3_ENABLE_SET | CPU0_ITAG_RAM2_ENABLE_SET | CPU0_ITAG_RAM1_ENABLE_SET | CPU0_ITAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for atcm0_bank1_pend |
21 | ATCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram0_pend |
R5FSS_CPU0_SEC_ENABLE_SET_REG1 is shown in Figure 6-68 and described in Table 6-141.
Return to Summary Table.
SEC interrupt enable set register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D084h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_ENABLE_SET | SCRP_EDC_ENABLE_SET | CPU0_AHB2VBUSP_EDC_ENABLE_SET | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_SEC_ENABLE_CLR_REG0 is shown in Figure 6-69 and described in Table 6-143.
Return to Summary Table.
SEC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D0C0h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E0C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | CPU0_VBUSM2AXI_EDC_ENABLE_CLR | CPU0_KS_VIM_RAMECC_ENABLE_CLR | B1TCM0_BANK1_ENABLE_CLR | B1TCM0_BANK0_ENABLE_CLR | B0TCM0_BANK1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_ENABLE_CLR | ATCM0_BANK1_ENABLE_CLR | ATCM0_BANK0_ENABLE_CLR | CPU0_DDATA_RAM7_ENABLE_CLR | CPU0_DDATA_RAM6_ENABLE_CLR | CPU0_DDATA_RAM5_ENABLE_CLR | CPU0_DDATA_RAM4_ENABLE_CLR | CPU0_DDATA_RAM3_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_ENABLE_CLR | CPU0_DDATA_RAM1_ENABLE_CLR | CPU0_DDATA_RAM0_ENABLE_CLR | CPU0_DDIRTY_RAM_ENABLE_CLR | CPU0_DTAG_RAM3_ENABLE_CLR | CPU0_DTAG_RAM2_ENABLE_CLR | CPU0_DTAG_RAM1_ENABLE_CLR | CPU0_DTAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_ENABLE_CLR | CPU0_IDATA_BANK2_ENABLE_CLR | CPU0_IDATA_BANK1_ENABLE_CLR | CPU0_IDATA_BANK0_ENABLE_CLR | CPU0_ITAG_RAM3_ENABLE_CLR | CPU0_ITAG_RAM2_ENABLE_CLR | CPU0_ITAG_RAM1_ENABLE_CLR | CPU0_ITAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for atcm0_bank1_pend |
21 | ATCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram0_pend |
R5FSS_CPU0_SEC_ENABLE_CLR_REG1 is shown in Figure 6-70 and described in Table 6-145.
Return to Summary Table.
SEC interrupt enable clear register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D0C4h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E0C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_ENABLE_CLR | SCRP_EDC_ENABLE_CLR | CPU0_AHB2VBUSP_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_DED_EOI_REG is shown in Figure 6-71 and described in Table 6-147.
Return to Summary Table.
DED EOI register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D13Ch |
R5FSS1_CORE0_ECC_AGGR | 3F00 E13Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved. |
0 | EOI_WR | R/W1S | 0h | EOI value. |
R5FSS_CPU0_DED_STATUS_REG0 is shown in Figure 6-72 and described in Table 6-149.
Return to Summary Table.
DED interrupt status register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D140h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | CPU0_VBUSM2AXI_EDC_PEND | CPU0_KS_VIM_RAMECC_PEND | B1TCM0_BANK1_PEND | B1TCM0_BANK0_PEND | B0TCM0_BANK1_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_PEND | ATCM0_BANK1_PEND | ATCM0_BANK0_PEND | CPU0_DDATA_RAM7_PEND | CPU0_DDATA_RAM6_PEND | CPU0_DDATA_RAM5_PEND | CPU0_DDATA_RAM4_PEND | CPU0_DDATA_RAM3_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_PEND | CPU0_DDATA_RAM1_PEND | CPU0_DDATA_RAM0_PEND | CPU0_DDIRTY_RAM_PEND | CPU0_DTAG_RAM3_PEND | CPU0_DTAG_RAM2_PEND | CPU0_DTAG_RAM1_PEND | CPU0_DTAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_PEND | CPU0_IDATA_BANK2_PEND | CPU0_IDATA_BANK1_PEND | CPU0_IDATA_BANK0_PEND | CPU0_ITAG_RAM3_PEND | CPU0_ITAG_RAM2_PEND | CPU0_ITAG_RAM1_PEND | CPU0_ITAG_RAM0_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_PEND | R/W1S | 0h | Interrupt pending status for atcm0_bank1_pend |
21 | ATCM0_BANK0_PEND | R/W1S | 0h | Interrupt pending status for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_PEND | R/W1S | 0h | Interrupt pending status for cpu0_itag_ram0_pend |
R5FSS_CPU0_DED_STATUS_REG1 is shown in Figure 6-73 and described in Table 6-151.
Return to Summary Table.
DED interrupt status register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D144h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E144h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_PEND | SCRP_EDC_PEND | CPU0_AHB2VBUSP_EDC_PEND | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_PEND | R/W1S | 0h | Interrupt pending status for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_PEND | R/W1S | 0h | Interrupt pending status for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_PEND | R/W1S | 0h | Interrupt pending status for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_DED_ENABLE_SET_REG0 is shown in Figure 6-74 and described in Table 6-153.
Return to Summary Table.
DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D180h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | CPU0_VBUSM2AXI_EDC_ENABLE_SET | CPU0_KS_VIM_RAMECC_ENABLE_SET | B1TCM0_BANK1_ENABLE_SET | B1TCM0_BANK0_ENABLE_SET | B0TCM0_BANK1_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_ENABLE_SET | ATCM0_BANK1_ENABLE_SET | ATCM0_BANK0_ENABLE_SET | CPU0_DDATA_RAM7_ENABLE_SET | CPU0_DDATA_RAM6_ENABLE_SET | CPU0_DDATA_RAM5_ENABLE_SET | CPU0_DDATA_RAM4_ENABLE_SET | CPU0_DDATA_RAM3_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_ENABLE_SET | CPU0_DDATA_RAM1_ENABLE_SET | CPU0_DDATA_RAM0_ENABLE_SET | CPU0_DDIRTY_RAM_ENABLE_SET | CPU0_DTAG_RAM3_ENABLE_SET | CPU0_DTAG_RAM2_ENABLE_SET | CPU0_DTAG_RAM1_ENABLE_SET | CPU0_DTAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_ENABLE_SET | CPU0_IDATA_BANK2_ENABLE_SET | CPU0_IDATA_BANK1_ENABLE_SET | CPU0_IDATA_BANK0_ENABLE_SET | CPU0_ITAG_RAM3_ENABLE_SET | CPU0_ITAG_RAM2_ENABLE_SET | CPU0_ITAG_RAM1_ENABLE_SET | CPU0_ITAG_RAM0_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for atcm0_bank1_pend |
21 | ATCM0_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_itag_ram0_pend |
R5FSS_CPU0_DED_ENABLE_SET_REG1 is shown in Figure 6-75 and described in Table 6-155.
Return to Summary Table.
DED interrupt enable set register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D184h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E184h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_ENABLE_SET | SCRP_EDC_ENABLE_SET | CPU0_AHB2VBUSP_EDC_ENABLE_SET | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_DED_ENABLE_CLR_REG0 is shown in Figure 6-76 and described in Table 6-157.
Return to Summary Table.
DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D1C0h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E1C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | CPU0_VBUSM2AXI_EDC_ENABLE_CLR | CPU0_KS_VIM_RAMECC_ENABLE_CLR | B1TCM0_BANK1_ENABLE_CLR | B1TCM0_BANK0_ENABLE_CLR | B0TCM0_BANK1_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_ENABLE_CLR | ATCM0_BANK1_ENABLE_CLR | ATCM0_BANK0_ENABLE_CLR | CPU0_DDATA_RAM7_ENABLE_CLR | CPU0_DDATA_RAM6_ENABLE_CLR | CPU0_DDATA_RAM5_ENABLE_CLR | CPU0_DDATA_RAM4_ENABLE_CLR | CPU0_DDATA_RAM3_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_ENABLE_CLR | CPU0_DDATA_RAM1_ENABLE_CLR | CPU0_DDATA_RAM0_ENABLE_CLR | CPU0_DDIRTY_RAM_ENABLE_CLR | CPU0_DTAG_RAM3_ENABLE_CLR | CPU0_DTAG_RAM2_ENABLE_CLR | CPU0_DTAG_RAM1_ENABLE_CLR | CPU0_DTAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_ENABLE_CLR | CPU0_IDATA_BANK2_ENABLE_CLR | CPU0_IDATA_BANK1_ENABLE_CLR | CPU0_IDATA_BANK0_ENABLE_CLR | CPU0_ITAG_RAM3_ENABLE_CLR | CPU0_ITAG_RAM2_ENABLE_CLR | CPU0_ITAG_RAM1_ENABLE_CLR | CPU0_ITAG_RAM0_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | CPU0_AXI2VBUSM_PERIPH_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_write_edc_pend |
30 | CPU0_AXI2VBUSM_MEM_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_read_edc_pend |
29 | CPU0_AXI2VBUSM_MEM_MST_WRITE_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_mem_mst_write_edc_pend |
28 | CPU0_VBUSM2AXI_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_vbusm2axi_edc_pend |
27 | CPU0_KS_VIM_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for atcm0_bank1_pend |
21 | ATCM0_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_itag_ram0_pend |
R5FSS_CPU0_DED_ENABLE_CLR_REG1 is shown in Figure 6-77 and described in Table 6-159.
Return to Summary Table.
DED interrupt enable clear register 1.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D1C4h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E1C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPU0_EDC_CTRL_ENABLE_CLR | SCRP_EDC_ENABLE_CLR | CPU0_AHB2VBUSP_EDC_ENABLE_CLR | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CPU0_EDC_CTRL_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_edc_ctrl_pend |
2 | SCRP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for scrp_edc_pend |
1 | CPU0_AHB2VBUSP_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_ahb2vbusp_edc_pend |
0 | CPU0_AXI2VBUSM_PERIPH_MST_READ_EDC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for cpu0_axi2vbusm_periph_mst_read_edc_pend |
R5FSS_CPU0_AGGR_ENABLE_SET is shown in Figure 6-78 and described in Table 6-161.
Return to Summary Table.
AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D200h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
R5FSS_CPU0_AGGR_ENABLE_CLR is shown in Figure 6-79 and described in Table 6-163.
Return to Summary Table.
AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D204h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
R5FSS_CPU0_AGGR_STATUS_SET is shown in Figure 6-80 and described in Table 6-165.
Return to Summary Table.
AGGR interrupt status set register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D208h |
R5FSS1_CORE0_ECC_AGGR | 3F00 E208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/W | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/W | 0h | interrupt status set for parity errors |
R5FSS_CPU0_AGGR_STATUS_CLR is shown in Figure 6-81 and described in Table 6-167.
Return to Summary Table.
AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
R5FSS0_CORE0_ECC_AGGR | 3F00 D20Ch |
R5FSS1_CORE0_ECC_AGGR | 3F00 E20Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/W | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/W | 0h | interrupt status clear for parity errors |