SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 5-986 describes the output clocks of PLLTS16FFCLAFRACF.
Output | Description | Frequency |
---|---|---|
FOUTP | Positive phase VCO output (no post divider) | (FREF / REF_DIV) * (FB_DIV + FB_DIV_FRAC) |
FOUTN | Negative phase VCO output (no post divider) | (FREF / REF_DIV) * (FB_DIV + FB_DIV_FRAC) |
FOUTPOSTDIV | VCO-divided clock output. | FOUTP / (POST_DIV1*POST_DIV2) |
CLKSSCG | Clock to SSMOD | (FREF / REF_DIV) |
Where:
POST_DIV1 and POST_DIV2 valid values are from 1 to 7. To ensure correct operation, POST_DIV1 must always be programmed to a value equal to or greater than POST_DIV2.
For device-specific information about clock output parameters and syntesized clocks, see Table 5-991 and Table 5-992.