SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-2590 lists the memory-mapped registers for the USB3P0SS_MMR_MMRVBP_USBSS_CMN registers. All register offset addresses not listed in Table 12-2590 should be considered as reserved locations and the register contents should not be modified.
Global Control Registers
Instance | Base Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 4000h |
Offset | Acronym | Register Name | USB0_MMR_MMRVBP_USBSS_CMN Physical Address |
---|---|---|---|
0h | USB3P0SS_PID | Revision Register | 0410 4000h |
4h | USB3P0SS_W1 | Wrapper Register 1 | 0410 4004h |
8h | USB3P0SS_STATIC_CONFIG | Static Configuration Register | 0410 4008h |
Ch | USB3P0SS_PHY_TEST | USB2 PHY Test Control and Status | 0410 400Ch |
1Ch | USB3P0SS_DEVICE_CTRL | Register for device control | 0410 401Ch |
USB3P0SS_PID is shown in Figure 12-1306 and described in Table 12-2592.
Return to Table 12-2590.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-823h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
3h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Register scheme |
29-28 | BU | R | 2h | BU |
27-16 | MODULE_ID | R | 823h | Module ID |
15-11 | RTL | R | 3h | RTL revision. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |
USB3P0SS_W1 is shown in Figure 12-1307 and described in Table 12-2594.
Return to Table 12-2590.
Wrapper register containing soft reset, mode selection, and overcurrent indicator.
Instance | Physical Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 4004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | USB2_ONLY_MODE | MODESTRAP | OVERCURRENT_N | ||||
R-0h | R/W-0h | R/W-0h | R/W-1h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MODESTRAP_SEL | OVERCURRENT_SEL | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWRUP_RST_N | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19 | USB2_ONLY_MODE | R/W | 0h | Selects USB2 only mode. |
18-17 | MODESTRAP | R/W | 0h | Modestrap input to the Controller. |
16 | OVERCURRENT_N | R/W | 1h | Overcurrent indicator to the controller. Software writes 0 when overcurrent was detected by external circuitry. |
15-10 | RESERVED | R | 0h | Reserved |
9 | MODESTRAP_SEL | R/W | 0h |
This bit has to be always set to 1. |
8 | OVERCURRENT_SEL | R/W | 0h | Overcurrent select. |
7-1 | RESERVED | R | 0h | Reserved |
0 | PWRUP_RST_N | R/W | 0h | Power up reset for the controller. |
USB3P0SS_STATIC_CONFIG is shown in Figure 12-1308 and described in Table 12-2596.
Return to Table 12-2590.
Wrapper register containing static settings. All bits in this register have to be written before setting PWRUP_RST_N bit in USB3P0SS_W1 register.
Instance | Physical Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PLL_REF_SEL | ||||||
R-0h | R/W-4h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_REF_SEL | RESERVED | VBUS_SEL | LANE_REVERSE | ||||
R/W-4h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8-5 | PLL_REF_SEL | R/W | 4h | This register directly drives the pllrefsel[3:0] input to USB2 PHY. Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should match the frequency value of either the HFOSC0 or HFOSC1 oscillator as selected by the USB0_CLKSEL register. Field values (Others are reserved): 4'b0000 - 9.6 MHz 4'b0001 - 10 MHz 4'b0010 - 12 MHz 4'b0011 - 18.2 MHz 4'b0100 - 20 MHz 4'b0101 - 24 MHz 4'b0110 - 25 MHz 4'b0111 - 26 MHz 4'b1000 - 38.4 MHz 4'b1001 - 40 MHz 4'b1010 - 48 MHz 4'b1011 - 50 MHz 4'b1100 - 52 MHz |
4-3 | RESERVED | R/W | 0h | Reserved. Always keep at 0x0 |
2-1 | VBUS_SEL | R/W | 0h | VBUS select. Always set to 0x1 |
0 | LANE_REVERSE | R/W | 0h | USB2PHY D+/D- reverse selection. |
USB3P0SS_PHY_TEST is shown in Figure 12-1309 and described in Table 12-2598.
Return to Table 12-2590.
Register containing PLL bypass select, BIST control and status
Instance | Physical Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 400Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BIST_MODE | BIST_ERROR_COUNT | |||||
R-0h | R/W-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BIST_ERROR_COUNT | BIST_ERROR | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BIST_COMPLETE | BIST_ON | BIST_MODE_EN | BIST_MODE_SEL | RESERVED | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved bits |
17 | BIST_MODE | R/W | 0h | Set
for bist mode. |
16-9 | BIST_ERROR_COUNT | R | 0h | Number of bytes that have errors while running BIST. |
8 | BIST_ERROR | R | 0h | If set, this bit indicates that BIST completed with error. |
7 | BIST_COMPLETE | R | 0h | If set, this bit indicates that the BIST operation is completed. |
6 | BIST_ON | R/W | 0h | Setting this bit starts the BIST operation. |
5 | BIST_MODE_EN | R/W | 0h | BIST
Mode Enable. |
4-1 | BIST_MODE_SEL | R/W | 0h | BIST
Mode Selection. |
0 | RESERVED | R/W | 0h | Reserved. Keep at 0x0 |
USB3P0SS_DEVICE_CTRL is shown in Figure 12-1310 and described in Table 12-2600.
Return to Table 12-2590.
Register for device control
Instance | Physical Address |
---|---|
USB0_MMR_MMRVBP_USBSS_CMN | 0410 401Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DEV_WAKEUP | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved bits |
0 | DEV_WAKEUP | R/W | 0h | Set this bit to trigger device wakeup interrupt on IRQ[7] |