SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | DMASS0_RINGACC_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 32 | DMASS0_RINGACC_0_RING_control_j | ISC a Region b Control Register | 4584 8000h+ Formula |
4h+ Formula | 32 | DMASS0_RINGACC_0_RING_control2_j | ISC a Region b Control Register 2 | 4584 8004h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_RINGACC_0 Physical Address |
---|---|---|---|---|
0h | 32 | DMASS0_RINGACC_0_revision | Revision Register | 4824 0000h |
10h | 32 | DMASS0_RINGACC_0_trace_ctl | Trace Control Register | 4824 0010h |
20h | 32 | DMASS0_RINGACC_0_ovrflow | Overflow Queue Register | 4824 0020h |
40h | 32 | DMASS0_RINGACC_0_error_evt | Error Event Register | 4824 0040h |
44h | 32 | DMASS0_RINGACC_0_error_log | Error Log Register | 4824 0044h |
Offset | Length | Acronym | Register Name | DMASS0_RINGACC_0 Physical Address |
---|---|---|---|---|
10h+ Formula | 32 | DMASS0_RINGACC_0_RINGRT_db_j | Realtime Ring N Doorbell Register | 4900 0010h+ Formula |
18h+ Formula | 32 | DMASS0_RINGACC_0_RINGRT_occ_j | Realtime Ring N Occupancy Register | 4900 0018h+ Formula |
1Ch+ Formula | 32 | DMASS0_RINGACC_0_RINGRT_indx_j | Realtime Ring N Current Index Register | 4900 001Ch+ Formula |
20h+ Formula | 32 | DMASS0_RINGACC_0_RINGRT_hwocc_j | Realtime Ring N Hardware Occupancy Register | 4900 0020h+ Formula |
24h+ Formula | 32 | DMASS0_RINGACC_0_RINGRT_hwindx_j | Realtime Ring N Current Index Register | 4900 0024h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_RINGACC_0 Physical Address |
---|---|---|---|---|
40h+ Formula | 32 | DMASS0_RINGACC_0_RING_ba_lo_j | Ring Base Address Lo Register | 4980 0040h+ Formula |
44h+ Formula | 32 | DMASS0_RINGACC_0_RING_ba_hi_j | Ring Base Address Hi Register | 4980 0044h+ Formula |
48h+ Formula | 32 | DMASS0_RINGACC_0_RING_size_j | Ring Size Register | 4980 0048h+ Formula |
4Ch+ Formula | 32 | DMASS0_RINGACC_0_RING_event_j | Ring Event Register | 4980 004Ch+ Formula |
50h+ Formula | 32 | DMASS0_RINGACC_0_RING_orderid_j | Ring OrderID Register | 4980 0050h+ Formula |
Offset | Length | Acronym | Register Name | DMASS0_RINGACC_0 Physical Address |
---|---|---|---|---|
0h+ Formula | 32 | DMASS0_RINGACC_0_FIFO_ringheaddata_j | Ring Head Entry Data Registers | 4E00 0000h+ Formula |
200h+ Formula | 32 | DMASS0_RINGACC_0_FIFO_ringtaildata_j | Ring Tail Entry Data Registers | 4E00 0200h+ Formula |
400h+ Formula | 32 | DMASS0_RINGACC_0_FIFO_peekheaddata_j | Ring Peek Head Entry Data Registers | 4E00 0400h+ Formula |
600h+ Formula | 32 | DMASS0_RINGACC_0_FIFO_peektaildata_j | Ring Peek Tail Entry Data Registers | 4E00 0600h+ Formula |
Short Description: ISC a Region b Control Register
Long Description:
Return to Summary Table
Offset = 0h + (j * 20h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4584 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NOPRIV | PRIV | RESERVED | PASS | NONSEC | SEC | |||||||||
NONE | R/W | R/W | NONE | R/W | R/W | R/W | |||||||||
0 | 0 | 0 | 0 | 0 | |||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRIV_ID | RESERVED | LOCK | ENABLE | ||||||||||||
R/W | NONE | R/W1TS | R/W | ||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
27 - 26 | NOPRIV | R/W | 0h | Clear output priv attribute. If each bit is set then the outgoing priv bit is cleared. Has precedence over priv set bits. |
25 - 24 | PRIV | R/W | 0h | Set outgoing priv attribute. If each bit is set then the outgoing priv bit is set. |
RESERVED | NONE | Reserved | ||
21 | PASS | R/W | 0h | No privID replacement, pass through value. |
20 | NONSEC | R/W | 0h | Make outgoing non-secure. Has precedence over secure enable bits. |
19 - 16 | SEC | R/W | 0h | Make outgoing secure. A value of 0xA enables, others disable. |
15 - 8 | PRIV_ID | R/W | 0h | Priv ID. |
RESERVED | NONE | Reserved | ||
4 | LOCK | R/W1TS | 0h | Lock region. Once set the region values cannot be modified. |
3 - 0 | ENABLE | R/W | 0h | Enable region. A value of 0xA enables, others disable. |
Short Description: ISC a Region b Control Register 2
Long Description:
Return to Summary Table
Offset = 4h + (j * 20h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4584 8004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PASS_V | RESERVED | ATYPE | VIRTID | ||||||||||||
R/W | NONE | R/W | R/W | ||||||||||||
0 | 0 | 0 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PASS_V | R/W | 0h | No virtID replacement, pass through value. |
RESERVED | NONE | Reserved | ||
29 - 28 | ATYPE | R/W | 0h | Defines the output address type. 0 = physical no memory attributes. 1 = intermediate. 2 = virtual. 3 = physical with memory attributes. |
27 - 16 | VIRTID | R/W | 0h | Virt ID. |
RESERVED | NONE | Reserved |
Short Description: Revision Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4824 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R | |||||||||||||||
110011000111100 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R | R | R | R | ||||||||||||
0 | 1 | 0 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 16 | MODID | R | 663Ch | Module ID field |
15 - 11 | REVRTL | R | 0h | RTL revision. Will vary depending on release. |
10 - 8 | REVMAJ | R | 1h | Major revision |
7 - 6 | CUSTOM | R | 0h | Custom |
5 - 0 | REVMIN | R | 1h | Minor revision |
Short Description: Trace Control Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4824 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EN | ALL_QUEUES | MSG | RESERVED | ||||||||||||
R/W | R/W | R/W | NONE | ||||||||||||
0 | 0 | 0 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EN | R/W | 0h | Trace enable 0 = disable 1 = enable. |
30 | ALL_QUEUES | R/W | 0h | Trace everything 0 = only the selected queue 1 = every queue. |
29 | MSG | R/W | 0h | Trace message data 0 = include only the operation 1 = include message data. |
RESERVED | NONE | Reserved | ||
15 - 0 | QUEUE | R/W | 0h | Queue number when tracing a single queue. |
Short Description: Overflow Queue Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4824 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | QUEUE | R/W | 0h | Queue to send overflow messages. A value of 0xffff will disable the overflow function. |
Short Description: Error Event Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4824 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVT | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | EVT | R/W | FFFFh | Event to send when detecting a bus error. |
Short Description: Error Log Register
Long Description:
Return to Summary Table
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4824 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PUSH | RESERVED | ||||||||||||||
R | NONE | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PUSH | R | 0h | Bus error was caused by a push. 0 = pop. 1 = push. |
RESERVED | NONE | Reserved | ||
15 - 0 | QUEUE | R | 0h | Queue that received the bus error. |
Short Description: Realtime Ring N Doorbell Register
Long Description:
Return to Summary Table
Offset = 10h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4900 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENTRY_CNT | ||||||||||||||
NONE | NA/W | ||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
7 - 0 | ENTRY_CNT | NA/W | 0h | Signed number of entries by which to increment the ring occupancy. For normal Tx Ring operation, this value should be a positive number. This occ value for the ring is increased by this value each time the doorbell register is written (occ absolute value will increase or decrease based on the sign of the tentry_cnt). |
Short Description: Realtime Ring N Occupancy Register
Long Description:
Return to Summary Table
Offset = 18h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4900 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OCC | ||||||||||||||
NONE | R/NA | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCC | |||||||||||||||
R/NA | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
20 - 0 | OCC | R/NA | 0h | Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed. |
Short Description: Realtime Ring N Current Index Register
Long Description:
Return to Summary Table
Offset = 1ch + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4900 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INDX | ||||||||||||||
NONE | R/NA | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INDX | |||||||||||||||
R/NA | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
19 - 0 | INDX | R/NA | 0h | Current SW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by SW each time SW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size Register for the ring the index will be reset back to 0. |
Short Description: Realtime Ring N Hardware Occupancy Register
Long Description:
Return to Summary Table
Offset = 20h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4900 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | OCC | ||||||||||||||
NONE | R/NA | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OCC | |||||||||||||||
R/NA | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
20 - 0 | OCC | R/NA | 0h | Total number of valid entries on the ring. This value is generally intended to be incremented by doorbell pokes from software and is decremented by the DMA engine as entries are completed. |
Short Description: Realtime Ring N Current Index Register
Long Description:
Return to Summary Table
Offset = 24h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4900 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | INDX | ||||||||||||||
NONE | R/NA | ||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INDX | |||||||||||||||
R/NA | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
19 - 0 | INDX | R/NA | 0h | Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size Register for the ring the index will be reset back to 0. |
Short Description: Ring Base Address Lo Register
Long Description:
Return to Summary Table
Offset = 40h + (j * 100h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4980 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ADDR_LO | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_LO | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | ADDR_LO | R/W | 0h | Tx Ring base address (LSBs) |
Short Description: Ring Base Address Hi Register
Long Description:
Return to Summary Table
Offset = 44h + (j * 100h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4980 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_HI | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | ADDR_HI | R/W | 0h | Tx Ring base address (MSBs) |
Short Description: Ring Size Register
Long Description:
Return to Summary Table
Offset = 48h + (j * 100h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4980 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
QMODE | RESERVED | ELSIZE | RESERVED | SIZE | |||||||||||
R/W | NONE | R/W | NONE | R/W | |||||||||||
0 | 0 | 0 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SIZE | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 30 | QMODE | R/W | 0h | Defines the mode for this ring or queue. |
RESERVED | NONE | Reserved | ||
26 - 24 | ELSIZE | R/W | 0h | Ring element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = RESERVED |
RESERVED | NONE | Reserved | ||
19 - 0 | SIZE | R/W | 0h | Tx Ring element count. This field configures the size of the ring in elements. For rings in CREDENTIALS or QM modes the size must be an even number. |
Short Description: Ring Event Register
Long Description:
Return to Summary Table
Offset = 4ch + (j * 100h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4980 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVT | |||||||||||||||
R/W | |||||||||||||||
1111111111111111 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | EVT | R/W | FFFFh | Defines the event for this ring or queue. |
Short Description: Ring OrderID Register
Long Description:
Return to Summary Table
Offset = 50h + (j * 100h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4980 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REPLACE | ORDERID | |||||||||||||
NONE | R/W | R/W | |||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
4 | REPLACE | R/W | 0h | Indicates to replace the bus orderid value for this ring or queue with the orderid MMR field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source transaction for the destination transaction. 1 = use the orderid MMR field value for the destination transaction. |
3 - 0 | ORDERID | R/W | 0h | Defines the bus orderid value for this ring or queue. |
Short Description: Ring Head Entry Data Registers
Long Description:
Return to Summary Table
Offset = 0h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4E00 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Block of ring head or tail element data |
Short Description: Ring Tail Entry Data Registers
Long Description:
Return to Summary Table
Offset = 200h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4E00 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Block of ring head or tail element data |
Short Description: Ring Peek Head Entry Data Registers
Long Description:
Return to Summary Table
Offset = 400h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4E00 0400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Block of ring head or tail element data. Reserved for rings in ring mode. |
Short Description: Ring Peek Tail Entry Data Registers
Long Description:
Return to Summary Table
Offset = 600h + (j * 1000h); where j = 0h to 1Fh
Instance Name | Base Address |
---|---|
DMASS0_RINGACC_0 | 4E00 0600h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | DATA | R/W | 0h | Block of ring head or tail element data. Reserved for rings in ring mode. |
Access Type | Code | Description |
---|---|---|
R/W | R/W | Read / Write |
R/W1TS | R/W1TS | Read/Write 1 To Set |
R | R | Read |
NA/W | NA/W | Undefined |
R/NA | R/NA | Undefined |