SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-4285 lists the memory-mapped registers for the ECAP modules. All register offset addresses not listed in Table 12-4285 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
ECAP0_CTL_STS | 2310 0000h |
ECAP1_CTL_STS | 2311 0000h |
ECAP2_CTL_STS | 2312 0000h |
Offset | Acronym | Register Name | ECAP0_CTL_STS Physical Address | ECAP1_CTL_STS Physical Address | ECAP2_CTL_STS Physical Address |
---|---|---|---|---|---|
0h | ECAP_TSCNT | Time Stamp Counter Register | 2310 0000h | 2311 0000h | 2312 0000h |
4h | ECAP_CNTPHS | Counter Phase Control Register | 2310 0004h | 2311 0004h | 2312 0004h |
8h | ECAP_CAP1 | Capture-1 Register | 2310 0008h | 2311 0008h | 2312 0008h |
Ch | ECAP_CAP2 | Capture-2 Register | 2310 000Ch | 2311 000Ch | 2312 000Ch |
10h | ECAP_CAP3 | Capture-3 Register | 2310 0010h | 2311 0010h | 2312 0010h |
14h | ECAP_CAP4 | Capture-4 Register | 2310 0014h | 2311 0014h | 2312 0014h |
28h | ECAP_ECCTL | ECAP Control Register | 2310 0028h | 2311 0028h | 2312 0028h |
2Ch | ECAP_ECINT_EN_FLG | ECAP Interrupt Enable and Flag Register | 2310 002Ch | 2311 002Ch | 2312 002Ch |
30h | ECAP_ECINT_CLR_FRC | ECAP Interrupt Clear and Forcing Register | 2310 0030h | 2311 0030h | 2312 0030h |
5Ch | ECAP_PID | Peripheral ID Register | 2310 005Ch | 2311 005Ch | 2312 005Ch |
ECAP_TSCNT is shown in Figure 12-2213 and described in Table 12-4287.
Return to Summary Table.
Time Stamp Counter register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0000h |
ECAP1_CTL_STS | 2311 0000h |
ECAP2_CTL_STS | 2312 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSCNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TSCNT | R/W | 0h | Active 32-bit counter register which is used as the capture time-base. |
ECAP_CNTPHS is shown in Figure 12-2214 and described in Table 12-4289.
Return to Summary Table.
Counter Phase Control register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0004h |
ECAP1_CTL_STS | 2311 0004h |
ECAP2_CTL_STS | 2312 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNTPHS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CNTPHS | R/W | 0h | Counter phase value register that can be
programmed for phase Lag/Lead. |
ECAP_CAP1 is shown in Figure 12-2215 and described in Table 12-4291.
Return to Summary Table.
Capture-1 register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0008h |
ECAP1_CTL_STS | 2311 0008h |
ECAP2_CTL_STS | 2312 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP1 | R/W | 0h | This register can be loaded (written) by: |
ECAP_CAP2 is shown in Figure 12-2216 and described in Table 12-4293.
Return to Summary Table.
Capture-2 register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 000Ch |
ECAP1_CTL_STS | 2311 000Ch |
ECAP2_CTL_STS | 2312 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP2 | R/W | 0h | This register can be loaded (written) by: |
ECAP_CAP3 is shown in Figure 12-2217 and described in Table 12-4295.
Return to Summary Table.
Capture-3 register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0010h |
ECAP1_CTL_STS | 2311 0010h |
ECAP2_CTL_STS | 2312 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP3 | R/W | 0h | In CMP mode this is a time-stamp capture register.
In APMW mode this is the period shadow (APER) register. |
ECAP_CAP4 is shown in Figure 12-2218 and described in Table 12-4297.
Return to Summary Table.
Capture-4 register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0014h |
ECAP1_CTL_STS | 2311 0014h |
ECAP2_CTL_STS | 2312 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAP4 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CAP4 | R/W | 0h | In CMP mode this is a time-stamp capture register.
In APMW mode this is the compare shadow (ACMP) register. |
ECAP_ECCTL is shown in Figure 12-2219 and described in Table 12-4299.
Return to Summary Table.
ECAP Control register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0028h |
ECAP1_CTL_STS | 2311 0028h |
ECAP2_CTL_STS | 2312 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FILTER | APWMPOL | CAP_APWM | SWSYNC | ||||
R-0h | R/W-0h | R/W-0h | WCap-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SYNCO_SEL | SYNCI_EN | TSCNTSTP | REARM_RESET | STOPVALUE | CONT_ONESHT | ||
R/W-0h | R/W-0h | R/W-0h | WCap-0h | R/W-3h | R/W-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FREE_SOFT | EVTFLTPS | CAPLDEN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRRST4 | CAP4POL | CTRRST3 | CAP3POL | CTRRST2 | CAP2POL | CTRRST1 | CAP1POL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; WCap = Write to Capture; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | FILTER | R | 0h | |
26 | APWMPOL | R/W | 0h | APWM Output Polarity Select: |
25 | CAP_APWM | R/W | 0h | CAP/APWM Operating Mode Select: |
24 | SWSYNC | WCap | 0h | Software Forced Counter (ECAP_TSCNT)
Synchronizing: |
23-22 | SYNCO_SEL | R/W | 0h | SyncOut Select: |
21 | SYNCI_EN | R/W | 0h | Counter (ECAP_TSCNT) SyncIn select mode: |
20 | TSCNTSTP | R/W | 0h | Counter Stop (freeze) Control: |
19 | REARM_RESET | WCap | 0h | One-Shot "Re-arming" Control Write 0h = Has no effect. |
18-17 | STOPVALUE | R/W | 3h | Stop Value for One-Shot Mode: |
16 | CONT_ONESHT | R/W | 0h | Continuous or One-shot Mode Control (applicable only in Capture mode): |
15-14 | FREE_SOFT | R/W | 0h | Emulation Control |
13-9 | EVTFLTPS | R/W | 0h | Event Filter Prescale Select: |
8 | CAPLDEN | R/W | 0h | Enable Loading of the ECAP_CAP1 to ECAP_CAP4
registers on a capture event: |
7 | CTRRST4 | R/W | 0h | Counter Reset on Capture Event 4: |
6 | CAP4POL | R/W | 0h | Capture Event 4 Polarity Select: |
5 | CTRRST3 | R/W | 0h | Counter Reset on Capture Event 3: |
4 | CAP3POL | R/W | 0h | Capture Event 3 Polarity Select: |
3 | CTRRST2 | R/W | 0h | Counter Reset on Capture Event 2: |
2 | CAP2POL | R/W | 0h | Capture Event 2 Polarity Select: |
1 | CTRRST1 | R/W | 0h | Counter Reset on Capture Event 1: |
0 | CAP1POL | R/W | 0h | Capture Event 1 Polarity Select: |
ECAP_ECINT_EN_FLG is shown in Figure 12-2220 and described in Table 12-4301.
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ECAP Interrupt Enable and Flag register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 002Ch |
ECAP1_CTL_STS | 2311 002Ch |
ECAP2_CTL_STS | 2312 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPEQ_FLG | PRDEQ_FLG | CNTOVF_FLG | CEVT4_FLG | CEVT3_FLG | CEVT2_FLG | CEVT1_FLG | INT_FLG |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPEQ_EN | PRDEQ_EN | CNTOVF_EN | CEVT4_EN | CEVT3_EN | CEVT2_EN | CEVT1_EN | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23 | CMPEQ_FLG | R | 0h | Compare Equal Status Flag: |
22 | PRDEQ_FLG | R | 0h | Period Equal Status Flag: |
21 | CNTOVF_FLG | R | 0h | Counter Overflow Status Flag: |
20 | CEVT4_FLG | R | 0h | Capture Event 4 Status Flag: |
19 | CEVT3_FLG | R | 0h | Capture Event 3 Status Flag: |
18 | CEVT2_FLG | R | 0h | Capture Event 2 Status Flag: |
17 | CEVT1_FLG | R | 0h | Capture Event 1 Status Flag: |
16 | INT_FLG | R | 0h | Global Interrupt Status Flag: |
15-8 | RESERVED | R | 0h | Reserved |
7 | CMPEQ_EN | R/W | 0h | Compare Equal Interrupt Enable: |
6 | PRDEQ_EN | R/W | 0h | Period Equal Interrupt Enable: |
5 | CNTOVF_EN | R/W | 0h | Counter Overflow Interrupt Enable: |
4 | CEVT4_EN | R/W | 0h | Capture Event 4 Interrupt Enable: |
3 | CEVT3_EN | R/W | 0h | Capture Event 3 Interrupt Enable: |
2 | CEVT2_EN | R/W | 0h | Capture Event 2 Interrupt Enable: |
1 | CEVT1_EN | R/W | 0h | Capture Event 1 Interrupt Enable: |
0 | RESERVED | R | 0h | Reserved |
ECAP_ECINT_CLR_FRC is shown in Figure 12-2221 and described in Table 12-4303.
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ECAP Interrupt Clear and Forcing register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 0030h |
ECAP1_CTL_STS | 2311 0030h |
ECAP2_CTL_STS | 2312 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPEQ_FRC | PRDEQ_FRC | CNTOVF_FRC | CEVT4_FRC | CEVT3_FRC | CEVT2_FRC | CEVT1_FRC | RESERVED |
W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | W1S-0h | R-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPEQ_CLR | PRDEQ_CLR | CNTOVF_CLR | CEVT4_CLR | CEVT3_CLR | CEVT2_CLR | CEVT1_CLR | INT_CLR |
W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h | W1C-0h |
LEGEND: W = Write Only; W1C = Write 1 to Clear Bit; W1S = Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23 | CMPEQ_FRC | W1S | 0h | Force Compare Equal: |
22 | PRDEQ_FRC | W1S | 0h | Force Period Equal: |
21 | CNTOVF_FRC | W1S | 0h | Force Counter Overflow: |
20 | CEVT4_FRC | W1S | 0h | Force Capture Event 4: |
19 | CEVT3_FRC | W1S | 0h | Force Capture Event 3: |
18 | CEVT2_FRC | W1S | 0h | Force Capture Event 2: |
17 | CEVT1_FRC | W1S | 0h | Force Capture Event 1: |
16-8 | RESERVED | R | 0h | Reserved |
7 | CMPEQ_CLR | W1C | 0h | Compare Equal Status Flag: |
6 | PRDEQ_CLR | W1C | 0h | Period Equal Status Flag: |
5 | CNTOVF_CLR | W1C | 0h | Counter Overflow Status Flag: |
4 | CEVT4_CLR | W1C | 0h | Capture Event 4 Status Flag: |
3 | CEVT3_CLR | W1C | 0h | Capture Event 3 Status Flag: |
2 | CEVT2_CLR | W1C | 0h | Capture Event 2 Status Flag: |
1 | CEVT1_CLR | W1C | 0h | Capture Event 1 Status Flag: |
0 | INT_CLR | W1C | 0h | Global Interrupt Clear Flag: |
ECAP_PID is shown in Figure 12-2222 and described in Table 12-4305.
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Peripheral ID register
Instance | Physical Address |
---|---|
ECAP0_CTL_STS | 2310 005Ch |
ECAP1_CTL_STS | 2311 005Ch |
ECAP2_CTL_STS | 2312 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVISION | |||||||||||||||||||||||||||||||
44D24100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REVISION | R | 44D24100h | TI internal data. Identifies revision of peripheral. |