SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 5-424 lists the memory-mapped registers for the MAIN_SEC_MMR0_CFG0. All register offset addresses not listed in Table 5-424 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0000h |
Offset | Acronym | Register Name | MAIN_SEC_MMR0_CFG0 Physical Address |
---|---|---|---|
20h | CTRLMMR_SEC_CLSTR0_DEF | Cluster0 Definition Register | 45A0 0020h |
40h | CTRLMMR_SEC_CLSTR0_CFG | Cluster0 Configuration Register | 45A0 0040h |
80h | CTRLMMR_SEC_CLSTR0_PMCTRL | Cluster0 Power Management Control Register | 45A0 0080h |
90h | CTRLMMR_SEC_CLSTR0_PMSTAT | Cluster0 Power Management Status Register | 45A0 0090h |
100h | CTRLMMR_SEC_CLSTR0_CORE0_CFG | Cluster0 Core0 Configuration Register | 45A0 0100h |
110h | CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_LO | Cluster0 Core0 Boot Vector Lo Register | 45A0 0110h |
114h | CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_HI | Cluster0 Core0 Boot Vector Hi Register | 45A0 0114h |
120h | CTRLMMR_SEC_CLSTR0_CORE0_PMCTRL | Cluster0 Core0 Power Management Control | 45A0 0120h |
130h | CTRLMMR_SEC_CLSTR0_CORE0_PMSTAT | Cluster0 Core0 Power Management Status Register | 45A0 0130h |
180h | CTRLMMR_SEC_CLSTR0_CORE1_CFG | Cluster0 Core1 Configuration Register 0 | 45A0 0180h |
190h | CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_LO | Cluster0 Core1 Boot Vector Lo Register | 45A0 0190h |
194h | CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_HI | Cluster0 Core1 Boot Vector Hi Register | 45A0 0194h |
1A0h | CTRLMMR_SEC_CLSTR0_CORE1_PMCTRL | Cluster0 Core1 Power Management Control | 45A0 01A0h |
1B0h | CTRLMMR_SEC_CLSTR0_CORE1_PMSTAT | Cluster0 Core1 Power Management Status Register | 45A0 01B0h |
1020h | CTRLMMR_SEC_CLSTR1_DEF | Cluster1 Definition Register | 45A0 1020h |
1040h | CTRLMMR_SEC_CLSTR1_CFG | Cluster1 Configuration Register | 45A0 1040h |
1080h | CTRLMMR_SEC_CLSTR1_PMCTRL | Cluster1 Power Management Control Register | 45A0 1080h |
1090h | CTRLMMR_SEC_CLSTR1_PMSTAT | Cluster1 Power Management Status Register | 45A0 1090h |
1100h | CTRLMMR_SEC_CLSTR1_CORE0_CFG | Cluster1 Core0 Configuration Register | 45A0 1100h |
1110h | CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_LO | Cluster1 Core0 Boot Vector Lo Register | 45A0 1110h |
1114h | CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_HI | Cluster1 Core0 Boot Vector Hi Register | 45A0 1114h |
1120h | CTRLMMR_SEC_CLSTR1_CORE0_PMCTRL | Cluster1 Core0 Power Management Control | 45A0 1120h |
1130h | CTRLMMR_SEC_CLSTR1_CORE0_PMSTAT | Cluster1 Core0 Power Management Status Register | 45A0 1130h |
1180h | CTRLMMR_SEC_CLSTR1_CORE1_CFG | Cluster1 Core1 Configuration Register 0 | 45A0 1180h |
1190h | CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_LO | Cluster1 Core1 Boot Vector Lo Register | 45A0 1190h |
1194h | CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_HI | Cluster1 Core1 Boot Vector Hi Register | 45A0 1194h |
11A0h | CTRLMMR_SEC_CLSTR1_CORE1_PMCTRL | Cluster1 Core1 Power Management Control | 45A0 11A0h |
11B0h | CTRLMMR_SEC_CLSTR1_CORE1_PMSTAT | Cluster1 Core1 Power Management Status Register | 45A0 11B0h |
9020h | CTRLMMR_SEC_CLSTR9_DEF | Cluster9 Definition Register | 45A0 9020h |
9040h | CTRLMMR_SEC_CLSTR9_CONFIG0 | Cluster9 Configuration Register | 45A0 9040h |
9080h | CTRLMMR_SEC_CLSTR9_PM_CONFIG | Cluster9 Power Management Control Register | 45A0 9080h |
9090h | CTRLMMR_SEC_CLSTR9_PM_STATUS | Cluster9 Power Management Status Register | 45A0 9090h |
9100h | CTRLMMR_SEC_CLSTR9_CORE0_CFG | Cluster9 Core0 Configuration Register | 45A0 9100h |
9110h | CTRLMMR_SEC_CLSTR9_RST_VEC_LO_CORE0 | Cluster9 Core0 Boot Vector Lo Register | 45A0 9110h |
9114h | CTRLMMR_SEC_CLSTR9_RST_VEC_HI_CORE0 | Cluster9 Core0 Boot Vector Hi Register | 45A0 9114h |
9120h | CTRLMMR_SEC_CLSTR9_CORE0_PMCTRL | Cluster9 Core0 Power Management Control | 45A0 9120h |
9130h | CTRLMMR_SEC_CLSTR9_CORE0_PMSTAT | Cluster9 Core0 Power Management Status Register | 45A0 9130h |
9180h | CTRLMMR_SEC_CLSTR9_CORE1_CFG | Cluster9 Core1 Configuration Register 0 | 45A0 9180h |
9190h | CTRLMMR_SEC_CLSTR9_RST_VEC_LO_CORE1 | Cluster9 Core1 Boot Vector Lo Register | 45A0 9190h |
9194h | CTRLMMR_SEC_CLSTR9_RST_VEC_HI_CORE1 | Cluster9 Core1 Boot Vector Hi Register | 45A0 9194h |
91A0h | CTRLMMR_SEC_CLSTR9_CORE1_PMCTRL | Cluster9 Core1 Power Management Control | 45A0 91A0h |
91B0h | CTRLMMR_SEC_CLSTR9_CORE1_PMSTAT | Cluster9 Core1 Power Management Status Register | 45A0 91B0h |
10020h | CTRLMMR_SEC_CLSTR16_DEF | Cluster16 Definition Register | 45A1 0020h |
10040h | CTRLMMR_SEC_CLSTR16_CFG | Cluster16 Configuration Register | 45A1 0040h |
10080h | CTRLMMR_SEC_CLSTR16_PMCTRL | Cluster16 Power Management Control Register | 45A1 0080h |
10090h | CTRLMMR_SEC_CLSTR16_PMSTAT | Cluster16 Power Management Status Register | 45A1 0090h |
10100h | CTRLMMR_SEC_CLSTR16_CORE0_CFG | Cluster16 Core0 Configuration Register | 45A1 0100h |
10110h | CTRLMMR_SEC_CLSTR16_CORE0_BOOTVECT_LO | Cluster16 Core0 Boot Vector Lo Register | 45A1 0110h |
10114h | CTRLMMR_SEC_CLSTR16_CORE0_BOOTVECT_HI | Cluster16 Core0 Boot Vector Hi Register | 45A1 0114h |
10120h | CTRLMMR_SEC_CLSTR16_CORE0_PMCTRL | Cluster16 Core0 Power Management Control | 45A1 0120h |
10130h | CTRLMMR_SEC_CLSTR16_CORE0_PMSTAT | Cluster16 Core0 Power Management Status Register | 45A1 0130h |
10180h | CTRLMMR_SEC_CLSTR16_CORE1_CFG | Cluster16 Core1 Configuration Register 0 | 45A1 0180h |
10190h | CTRLMMR_SEC_CLSTR16_CORE1_BOOTVECT_LO | Cluster16 Core1 Boot Vector Lo Register | 45A1 0190h |
10194h | CTRLMMR_SEC_CLSTR16_CORE1_BOOTVECT_HI | Cluster16 Core1 Boot Vector Hi Register | 45A1 0194h |
101A0h | CTRLMMR_SEC_CLSTR16_CORE1_PMCTRL | Cluster16 Core1 Power Management Control | 45A1 01A0h |
101B0h | CTRLMMR_SEC_CLSTR16_CORE1_PMSTAT | Cluster16 Core1 Power Management Status Register | 45A1 01B0h |
18008h | CTRLMMR_SEC_GIC_CONFIG | GIC Configuration Register | 45A1 8008h |
CTRLMMR_SEC_CLSTR0_DEF is shown in Figure 5-203 and described in Table 5-426.
Return to Summary Table.
Defines the type of the processor cluster.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CORE_NUM | ||||||
R-0h | R-2h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSP_CORE_TYPE | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARM_CORE_TYPE | |||||||
R-10h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CORE_NUM | R | 2h | Number of cores in cluster |
15-8 | DSP_CORE_TYPE | R | FFh | DSP core type configuration 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP |
7-0 | ARM_CORE_TYPE | R | 10h | ARM core type configuration 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'h20 - M4F 8'hFF - Not ARM |
CTRLMMR_SEC_CLSTR0_CFG is shown in Figure 5-204 and described in Table 5-428.
Return to Summary Table.
Configures cluster level characteristics.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLSTR_CFG_RSVD | SINGLE_CORE_ONLY | SINGLE_CORE | MEM_INIT_DIS | LOCKSTEP_EN | DBG_NO_CLKSTOP | TEINIT | LOCKSTEP |
R/W-0h | R-X | R/W-X | R/W-0h | R-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | CLSTR_CFG_RSVD | R/W | 0h | Reserved for future use. Write '0' to ensure compatibility with future devices. |
6 | SINGLE_CORE_ONLY | R | X | Single / Dual CPU Mode Supported: |
5 | SINGLE_CORE | R/W | X | Single / Dual CPU Mode: |
4 | MEM_INIT_DIS | R/W | 0h | Disables SRAM initialization (TCM, Cache Tags, etc) at reset |
3 | LOCKSTEP_EN | R | 0h | Lockstep Not Supported |
2 | DBG_NO_CLKSTOP | R/W | 0h | CPU clockstop behavior |
1 | TEINIT | R/W | 0h | Exception handling state at reset: |
0 | LOCKSTEP | R | 0h | Lockstep Not Supported |
CTRLMMR_SEC_CLSTR0_PMCTRL is shown in Figure 5-205 and described in Table 5-430.
Return to Summary Table.
Configures Cluster overall power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for R5FSS |
CTRLMMR_SEC_CLSTR0_PMSTAT is shown in Figure 5-206 and described in Table 5-432.
Return to Summary Table.
Shows Cluster overall power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for R5FSS |
CTRLMMR_SEC_CLSTR0_CORE0_CFG is shown in Figure 5-207 and described in Table 5-434.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core0 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core0 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core0 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core0 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_LO is shown in Figure 5-208 and described in Table 5-436.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core0. Bits 4:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-4h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 4h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_HI is shown in Figure 5-209 and described in Table 5-438.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_SEC_CLSTR0_CORE0_PMCTRL is shown in Figure 5-210 and described in Table 5-440.
Return to Summary Table.
Configures Cluster Core0 power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core0 |
CTRLMMR_SEC_CLSTR0_CORE0_PMSTAT is shown in Figure 5-211 and described in Table 5-442.
Return to Summary Table.
Shows Cluster Core0 power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core0 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core0 WFE |
0 | WFI | R | X | Core0 WFI |
CTRLMMR_SEC_CLSTR0_CORE1_CFG is shown in Figure 5-212 and described in Table 5-444.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core1 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core1 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core1 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core1 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_LO is shown in Figure 5-213 and described in Table 5-446.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 4:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-4h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 4h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR0_CORE1_BOOTVECT_HI is shown in Figure 5-214 and described in Table 5-448.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 0194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_SEC_CLSTR0_CORE1_PMCTRL is shown in Figure 5-215 and described in Table 5-450.
Return to Summary Table.
Configures Cluster Core1 power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 01A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core1 |
CTRLMMR_SEC_CLSTR0_CORE1_PMSTAT is shown in Figure 5-216 and described in Table 5-452.
Return to Summary Table.
Shows Cluster Core1 power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 01B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core1 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core1 WFE |
0 | WFI | R | X | Core1 WFI |
CTRLMMR_SEC_CLSTR1_DEF is shown in Figure 5-217 and described in Table 5-454.
Return to Summary Table.
Defines the type of the processor cluster.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CORE_NUM | ||||||
R-0h | R-2h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSP_CORE_TYPE | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARM_CORE_TYPE | |||||||
R-10h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CORE_NUM | R | 2h | Number of cores in cluster |
15-8 | DSP_CORE_TYPE | R | FFh | DSP core type configuration 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP |
7-0 | ARM_CORE_TYPE | R | 10h | ARM core type configuration 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'h20 - M4F 8'hFF - Not ARM |
CTRLMMR_SEC_CLSTR1_CFG is shown in Figure 5-218 and described in Table 5-456.
Return to Summary Table.
Configures cluster level characteristics.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLSTR_CFG_RSVD | SINGLE_CORE_ONLY | SINGLE_CORE | MEM_INIT_DIS | LOCKSTEP_EN | DBG_NO_CLKSTOP | TEINIT | LOCKSTEP |
R/W-0h | R-X | R/W-X | R/W-0h | R-0h | R/W-0h | R/W-0h | R-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | CLSTR_CFG_RSVD | R/W | 0h | Reserved for future use. Write '0' to ensure compatibility with future devices. |
6 | SINGLE_CORE_ONLY | R | X | Single / Dual CPU Mode Supported: |
5 | SINGLE_CORE | R/W | X | Single / Dual CPU Mode: |
4 | MEM_INIT_DIS | R/W | 0h | Disables SRAM initialization (TCM, Cache Tags, etc) at reset |
3 | LOCKSTEP_EN | R | 0h | Lockstep Not Supported |
2 | DBG_NO_CLKSTOP | R/W | 0h | CPU clockstop behavior |
1 | TEINIT | R/W | 0h | Exception handling state at reset: |
0 | LOCKSTEP | R | 0h | Lockstep Not Supported |
CTRLMMR_SEC_CLSTR1_PMCTRL is shown in Figure 5-219 and described in Table 5-458.
Return to Summary Table.
Configures Cluster overall power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for R5FSS |
CTRLMMR_SEC_CLSTR1_PMSTAT is shown in Figure 5-220 and described in Table 5-460.
Return to Summary Table.
Shows Cluster overall power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for R5FSS |
CTRLMMR_SEC_CLSTR1_CORE0_CFG is shown in Figure 5-221 and described in Table 5-462.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core0 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core0 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core0 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core0 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_LO is shown in Figure 5-222 and described in Table 5-464.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core0. Bits 4:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-4h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 4h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE0_BOOTVECT_HI is shown in Figure 5-223 and described in Table 5-466.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_SEC_CLSTR1_CORE0_PMCTRL is shown in Figure 5-224 and described in Table 5-468.
Return to Summary Table.
Configures Cluster Core0 power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core0 |
CTRLMMR_SEC_CLSTR1_CORE0_PMSTAT is shown in Figure 5-225 and described in Table 5-470.
Return to Summary Table.
Shows Cluster Core0 power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core0 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core0 WFE |
0 | WFI | R | X | Core0 WFI |
CTRLMMR_SEC_CLSTR1_CORE1_CFG is shown in Figure 5-226 and described in Table 5-472.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core1 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core1 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core1 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core1 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_LO is shown in Figure 5-227 and described in Table 5-474.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 4:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-4h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 4h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_SEC_CLSTR1_CORE1_BOOTVECT_HI is shown in Figure 5-228 and described in Table 5-476.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 1194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_SEC_CLSTR1_CORE1_PMCTRL is shown in Figure 5-229 and described in Table 5-478.
Return to Summary Table.
Configures Cluster Core1 power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 11A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core1 |
CTRLMMR_SEC_CLSTR1_CORE1_PMSTAT is shown in Figure 5-230 and described in Table 5-480.
Return to Summary Table.
Shows Cluster Core1 power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 11B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core1 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core1 WFE |
0 | WFI | R | X | Core1 WFI |
CTRLMMR_SEC_CLSTR9_DEF is shown in Figure 5-231 and described in Table 5-482.
Return to Summary Table.
Defines the type of the processor cluster.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CORE_NUM | ||||||
R-0h | R-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSP_CORE_TYPE | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARM_CORE_TYPE | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17-16 | CORE_NUM | R | 1h | Number of cores in cluster |
15-8 | DSP_CORE_TYPE | R | FFh | 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP |
7-0 | ARM_CORE_TYPE | R | 0h | 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'h20 - M4F 8'hFF - Not ARM |
CTRLMMR_SEC_CLSTR9_CONFIG0 is shown in Figure 5-232 and described in Table 5-484.
Return to Summary Table.
Configures cluster level characteristics.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CP15_DISABLE1 | CP15_DISABLE0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONFIG_TE1 | CONFIG_TE0 | RESERVED | AARCH1 | AARCH0 | ||
R-0h | R/W-0h | R/W-0h | R-0h | R/W-1h | R/W-1h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | CP15_DISABLE1 | R/W | 0h | Disable write access to secure CP15 registers for Core1 |
8 | CP15_DISABLE0 | R/W | 0h | Disable write access to secure CP15 registers for Core0 |
7-6 | RESERVED | R | 0h | Reserved |
5 | CONFIG_TE1 | R/W | 0h | Enable T32 exceptions for Core1 |
4 | CONFIG_TE0 | R/W | 0h | Enable T32 exceptions for Core0 |
3-2 | RESERVED | R | 0h | Reserved |
1 | AARCH1 | R/W | 1h | Core1 ARM Architecture configuration |
0 | AARCH0 | R/W | 1h | Core0 ARM Architecture configuration |
CTRLMMR_SEC_CLSTR9_PM_CONFIG is shown in Figure 5-233 and described in Table 5-486.
Return to Summary Table.
Configures Cluster overall power state.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | L2RSTDISABLE | RESERVED | DBGPWRUP1 | DBGPWRUP0 | |||
R-0h | R/W-0h | R-0h | R/W-1h | R/W-1h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DBGL1RSTDISABLE | CLEAR_MON | L2_FLUSHREQ | RESERVED | ACP_MASTER | SNOOP_IF | ||
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12 | L2RSTDISABLE | R/W | 0h | Disable L2 cache automatic invalidate on reset functionality. |
11-10 | RESERVED | R | 0h | Reserved |
9 | DBGPWRUP1 | R/W | 1h | Core1 powered up |
8 | DBGPWRUP0 | R/W | 1h | Core0 powered up |
7 | DBGL1RSTDISABLE | R/W | 0h | Disable L1 data cache automatic invalidate on reset functionality. |
6 | CLEAR_MON | R/W | 0h | Request to clear the external global exclusive monitor. |
5 | L2_FLUSHREQ | R/W | 0h | ARM L2 hardware flush request |
4-2 | RESERVED | R | 0h | Reserved |
1 | ACP_MASTER | R/W | 0h | ACP master is inactive and is not participating in coherency. There must |
0 | SNOOP_IF | R/W | 0h | Snoop interface is inactive and not participating in coherency: |
CTRLMMR_SEC_CLSTR9_PM_STATUS is shown in Figure 5-234 and described in Table 5-488.
Return to Summary Table.
Shows Cluster overall power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLEAR_MONITOR_ACK | STANDBY_WFI_L2 | L2_HW_FLUSH | RESERVED | CORE1_SMPEN | CORE0_SMPEN | |
R-0h | R-X | R-X | R-X | R-0h | R-X | R-X | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE1_WFE | CORE0_WFE | RESERVED | CORE1_WFI | CORE0_WFI | ||
R-0h | R-X | R-X | R-0h | R-X | R-X | ||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Reserved |
14 | CLEAR_MONITOR_ACK | R | X | External global exclusive monitor clear acknowledge. |
13 | STANDBY_WFI_L2 | R | X | Indicates L2 low power state |
12 | L2_HW_FLUSH | R | X | L2 hardware flush complete |
11-10 | RESERVED | R | 0h | Reserved |
9 | CORE1_SMPEN | R | X | Core1 coherency indicator |
8 | CORE0_SMPEN | R | X | Core0 coherency indicator |
7-6 | RESERVED | R | 0h | Reserved |
5 | CORE1_WFE | R | X | Indicates Core1 in WFE state |
4 | CORE0_WFE | R | X | Indicates Core0 in WFE state |
3-2 | RESERVED | R | 0h | Reserved |
1 | CORE1_WFI | R | X | Indicates Core1 in WFI state |
0 | CORE0_WFI | R | X | Indicates Core0 in WFI state |
CTRLMMR_SEC_CLSTR9_CORE0_CFG is shown in Figure 5-235 and described in Table 5-490.
Return to Summary Table.
Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR9_RST_VEC_LO_CORE0 is shown in Figure 5-236 and described in Table 5-492.
Return to Summary Table.
Contains Bits [33:2] of the Boot Vector for A53SS Core 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESET_BASE_VECTOR_LO | R/W | 0h | Core0 - Reset base vector (v8 Mode) Address[33:2] |
CTRLMMR_SEC_CLSTR9_RST_VEC_HI_CORE0 is shown in Figure 5-237 and described in Table 5-494.
Return to Summary Table.
Contains Bits [35:34] of the Boot Vector for A53SS Core 0.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESET_BASE_VECTOR_HI | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | RESET_BASE_VECTOR_HI | R/W | 0h | Core0 - Reset base vector (v8 Mode) Address[35:34] |
CTRLMMR_SEC_CLSTR9_CORE0_PMCTRL is shown in Figure 5-238 and described in Table 5-496.
Return to Summary Table.
Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR9_CORE0_PMSTAT is shown in Figure 5-239 and described in Table 5-498.
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Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR9_CORE1_CFG is shown in Figure 5-240 and described in Table 5-500.
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Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR9_RST_VEC_LO_CORE1 is shown in Figure 5-241 and described in Table 5-502.
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Contains Bits [33:2] of the Boot Vector for A53SS Core 1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET_BASE_VECTOR_LO | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESET_BASE_VECTOR_LO | R/W | 0h | Core0 - Reset base vector (v8 Mode) Address[33:2] |
CTRLMMR_SEC_CLSTR9_RST_VEC_HI_CORE1 is shown in Figure 5-242 and described in Table 5-504.
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Contains Bits [35:34] of the Boot Vector for A53SS Core 1.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 9194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESET_BASE_VECTOR_HI | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | RESET_BASE_VECTOR_HI | R/W | 0h | Core0 - Reset base vector (v8 Mode) Address[35:34] |
CTRLMMR_SEC_CLSTR9_CORE1_PMCTRL is shown in Figure 5-243 and described in Table 5-506.
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Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 91A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR9_CORE1_PMSTAT is shown in Figure 5-244 and described in Table 5-508.
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Reserved - Not Used For A53SS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A0 91B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for A53SS |
CTRLMMR_SEC_CLSTR16_DEF is shown in Figure 5-245 and described in Table 5-510.
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Defines the type of the processor cluster.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CORE_NUM | ||||||
R-0h | R-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSP_CORE_TYPE | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARM_CORE_TYPE | |||||||
R-11h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CORE_NUM | R | 1h | Number of cores in cluster |
15-8 | DSP_CORE_TYPE | R | FFh | DSP core type configuration 8'h00 - C7x 8'h01 - C6x 8'hFF - Not DSP |
7-0 | ARM_CORE_TYPE | R | 11h | ARM core type configuration 8'h00 - A53 8'h01 - A57 8'h10 - R5 8'h20 - M4F 8'hFF - Not ARM |
CTRLMMR_SEC_CLSTR16_CFG is shown in Figure 5-246 and described in Table 5-512.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_PMCTRL is shown in Figure 5-247 and described in Table 5-514.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_PMSTAT is shown in Figure 5-248 and described in Table 5-516.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE0_CFG is shown in Figure 5-249 and described in Table 5-518.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE0_BOOTVECT_LO is shown in Figure 5-250 and described in Table 5-520.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE0_BOOTVECT_HI is shown in Figure 5-251 and described in Table 5-522.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE0_PMCTRL is shown in Figure 5-252 and described in Table 5-524.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE0_PMSTAT is shown in Figure 5-253 and described in Table 5-526.
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Shows M4FSS Core0 power status.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WFI | ||||||
R-0h | R-X | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Not used for M4FSS |
0 | WFI | R | X | M4FSS Sleeping Status |
CTRLMMR_SEC_CLSTR16_CORE1_CFG is shown in Figure 5-254 and described in Table 5-528.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE1_BOOTVECT_LO is shown in Figure 5-255 and described in Table 5-530.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE1_BOOTVECT_HI is shown in Figure 5-256 and described in Table 5-532.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 0194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE1_PMCTRL is shown in Figure 5-257 and described in Table 5-534.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 01A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_CLSTR16_CORE1_PMSTAT is shown in Figure 5-258 and described in Table 5-536.
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Reserved - Not Used For M4FSS.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 01B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Not used for M4FSS |
CTRLMMR_SEC_GIC_CONFIG is shown in Figure 5-259 and described in Table 5-538.
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Configures the A53 GIC.
Instance | Physical Address |
---|---|
MAIN_SEC_MMR0_CFG0 | 45A1 8008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | A53SS0_CORE1_ACTIVE | A53SS0_CORE0_ACTIVE | |||||
R-0h | R/W-1h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | A53SS0_CORE1_ACTIVE | R/W | 1h | Drives GIC cpu_active input for A53SS0 Core1. |
8 | A53SS0_CORE0_ACTIVE | R/W | 1h | Drives GIC cpu_active input for A53SS0 Core0. |
7-0 | RESERVED | R | 0h | Reserved |