SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There are two reasons why Blazar M4F needs to have address remapping function to access some of the end points on the SoC side.
First of all, M4F has different memory map view compared to ARM MPU and DMA even within 32b address space. For example, M4F has some reserved address space at 0xE000_0000 to 0xFFFF_FFFF. However, this same address space is mapped to DDR data region. Table 6-324 summarizes the difference between Blazar native 32b address view vs the other SoC initiators such as ARM MPU and DMA view.
Memory Region Name | CortexM4 Start Address (32 bit) | CortexM4 End Address (32 bit) | Total Size | Description | SoC Controller View (36 b address) |
---|---|---|---|---|---|
I-RAM | 0x0000_0000 | 0x0002_FFFF | 192KB | Unified RAM embedded inside M4F subsystem | 0x0500_0000 |
D-RaM | 0x0003_0000 | 0x0003_FFFF | 64KB | Unified RAM embedded inside M4F subsystem | 0x0504_0000 |
Reserved | 0x0004_0000 | 0x441F_FFFF | Reserved. Not implemented inside M4F subsystem | Not mapped on SoC side | |
RAT config | 0x4420_0000 | 0x4420_0FFF | 4KB | RAT config port (12-bits) | 0x05FF_0000 |
Blazar ECC Aggregator | 0x4420_1000 | 0x4420_13FF | 1KB | 0x05FF_1000 | |
Reserved | 0x4420_1400 | 0x5FFF_FFFF | Reserved. Not implemented inside M4F subsystem | Not mapped on SoC side | |
Memory Region external to M4F | 0x6000_0000 | 0xDFFF_FFFF | ~2GB | Can be mapped for CORTEX-M4 accesses outside of M4FE via RAT module | Can be mapped to any SoC memory region through RAT configuration |
ITM | 0xE000_0000 | 0xE000_0FFF | 4KB | Only Visible by M4F core itself | Not accessible from Soc side |
DWT | 0xE000_1000 | 0xE000_1FFF | 4KB | ||
FBP | 0xE000_2000 | 0xE000_2FFF | 4KB | ||
SCS | 0xE000_E000 | 0xE000_EFFF | 4KB | ||
CTI | 0xE004_2000 | 0xE004_2FFF | 4KB | ||
NVIC config region | 0xE000_E000 | 0xE000_E4EF | 1.2KB | ||
ROM Table | 0xE00F_F000 | ||||
Reserved | 0xE010_0000 | 0xFFFF_FFFF |
Second, M4F is a micro controller with 32b address, which is only able to access up to 4GB address space. However, Sitara SoC supports 36b address and there are end points such as some of the flash is located at upper 4GB address space. M4F’s native 32b address map is not able to access those flash regions without address remapping function. Figure 6-155 shows the SoC 36b memory map.
RAT block enables M4F core to have full access on the SoC memory map including the memory region at and above 0x1_0000_0000.