SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-1286 lists the memory-mapped registers for the PRU_MDIO_MDIO registers. All register offset addresses not listed in Table 6-1286 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2400h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2400h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_MDIO_V1P7_MDIO Physical Address | PRU_ICSSG1_PR1_MDIO_V1P7_MDIO Physical Address |
---|---|---|---|---|
0h | MDIO_VERSION_REG | MDIO Version Register | 3003 2400h | 300B 2400h |
4h | MDIO_CONTROL_REG | MDIO Control Register | 3003 2404h | 300B 2404h |
8h | MDIO_ALIVE_REG | MDIO Alive Register | 3003 2408h | 300B 2408h |
Ch | MDIO_LINK_REG | MDIO Link Register | 3003 240Ch | 300B 240Ch |
10h | MDIO_LINK_INT_RAW_REG | MDIO Link Interrupt Raw Register | 3003 2410h | 300B 2410h |
14h | MDIO_LINK_INT_MASKED_REG | MDIO Link Interrupt Masked Register | 3003 2414h | 300B 2414h |
18h | MDIO_LINK_INT_MASK_SET_REG | MDIO Link Interrupt Mask Set Register | 3003 2418h | 300B 2418h |
1Ch | MDIO_LINK_INT_MASK_CLEAR_REG | MDIO Link Interrupt Mask Clear Register | 3003 241Ch | 300B 241Ch |
20h | MDIO_USER_INT_RAW_REG | MDIO User Interrupt Raw Register | 3003 2420h | 300B 2420h |
24h | MDIO_USER_INT_MASKED_REG | MDIO User Interrupt Masked Register | 3003 2424h | 300B 2424h |
28h | MDIO_USER_INT_MASK_SET_REG | MDIO User Interrupt Mask Set Register | 3003 2428h | 300B 2428h |
2Ch | MDIO_USER_INT_MASK_CLEAR_REG | MDIO User Interrupt Mask Clear Register | 3003 242Ch | 300B 242Ch |
30h | MDIO_MANUAL_IF_REG | MDIO Manual Interface Register | 3003 2430h | 300B 2430h |
34h | MDIO_POLL_REG | MDIO Poll Inter Register | 3003 2434h | 300B 2434h |
38h | MDIO_POLL_EN_REG | MDIO Poll Enable Register | 3003 2438h | 300B 2438h |
3Ch | MDIO_CLAUS45_REG | Clause 45 Register | 3003 243Ch | 300B 243Ch |
40h | MDIO_USER_ADDR0_REG | MDIO User Address 0 Register | 3003 2440h | 300B 2440h |
44h | MDIO_USER_ADDR1_REG | MDIO User Address 1 Register | 3003 2444h | 300B 2444h |
80h | MDIO_USER_ACCESS_REG_j | MDIO User Access j Register | 3003 2480h | 300B 2480h |
84h | MDIO_USER_PHY_SEL_REG_j | MDIO User PHY Select j Register | 3003 2484h | 300B 2484h |
MDIO_VERSION_REG is shown in Figure 6-650 and described in Table 6-1288.
Return to Summary Table.
MDIO Version Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2400h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODID | REVMAJ | REVMINOR | |||||||||||||||||||||||||||||
R-7h | R-1h | R-7h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 7h | Module Identification value |
15-8 | REVMAJ | R | 1h | Major revision value |
7-0 | REVMINOR | R | 7h | Minor revision value |
MDIO_CONTROL_REG is shown in Figure 6-651 and described in Table 6-1290.
Return to Summary Table.
MDIO Control Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2404h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2404h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IDLE | ENABLE | RESERVED | HIGHEST_USER_CHANNEL | ||||
R-1h | R/W-0h | R/W-X | R-1h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PREAMBLE | FAULT | FAULT_DETECT_ENABLE | INT_TEST_ENABLE | RESERVED | ||
R/W-X | R/W-0h | R/W1C-0h | R/W-0h | R/W-0h | R/W-X | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLKDIV | |||||||
R/W-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKDIV | |||||||
R/W-FFh | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IDLE | R | 1h | MDIO state machine IDLE. |
30 | ENABLE | R/W | 0h | Enable control. |
29 | RESERVED | R/W | X | |
28-24 | HIGHEST_USER_CHANNEL | R | 1h | Highest user channel. |
23-21 | RESERVED | R/W | X | |
20 | PREAMBLE | R/W | 0h | Preamble disable. |
19 | FAULT | R/W1C | 0h | Fault indicator. |
18 | FAULT_DETECT_ENABLE | R/W | 0h | Fault detect enable. |
17 | INT_TEST_ENABLE | R/W | 0h | Interrupt test enable. |
16 | RESERVED | R/W | X | |
15-0 | CLKDIV | R/W | FFh | Clock Divider. |
MDIO_ALIVE_REG is shown in Figure 6-652 and described in Table 6-1292.
Return to Summary Table.
MDIO Alive Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2408h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2408h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALIVE | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ALIVE | R/W1C | 0h | MDIO Alive. |
MDIO_LINK_REG is shown in Figure 6-653 and described in Table 6-1294.
Return to Summary Table.
MDIO Link Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 240Ch |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 240Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINK | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LINK | R | 0h | MDIO Link state. |
MDIO_LINK_INT_RAW_REG is shown in Figure 6-654 and described in Table 6-1296.
Return to Summary Table.
MDIO Link Interrupt Raw Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2410h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2410h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINKINTRAW | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | LINKINTRAW | R/W1C | 0h | MDIO link change event raw value. |
MDIO_LINK_INT_MASKED_REG is shown in Figure 6-655 and described in Table 6-1298.
Return to Summary Table.
MDIO Link Interrupt Masked Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2414h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2414h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINKINTMASKED | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | LINKINTMASKED | R/W1C | 0h | MDIO link change interrupt masked value. |
MDIO_LINK_INT_MASK_SET_REG is shown in Figure 6-656 and described in Table 6-1300.
Return to Summary Table.
MDIO Link Interrupt Mask Set Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2418h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2418h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINKINTMASKSET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | LINKINTMASKSET | R/W1S | 0h | MDIO link interrupt mask set. |
MDIO_LINK_INT_MASK_CLEAR_REG is shown in Figure 6-657 and described in Table 6-1302.
Return to Summary Table.
MDIO Link Interrupt Mask Clear Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 241Ch |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 241Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINKINTMASKCLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | LINKINTMASKCLR | R/W1C | 0h | MDIO link interrupt mask clear. |
MDIO_USER_INT_RAW_REG is shown in Figure 6-658 and described in Table 6-1304.
Return to Summary Table.
MDIO User Interrupt Raw Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2420h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2420h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USERINTRAW | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | USERINTRAW | R/W1C | 0h | Raw value of MDIO user command complete event for
MDIO_USER_ACCESS_REG_1 through MDIO_USER_ACCESS_REG_0,
respectively. |
MDIO_USER_INT_MASKED_REG is shown in Figure 6-659 and described in Table 6-1306.
Return to Summary Table.
MDIO User Interrupt Masked Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2424h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2424h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USERINTMASKED | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | USERINTMASKED | R/W1C | 0h | Masked value of MDIO user command complete
interrupt for MDIO_USER_ACCESS_REG_1 through
MDIO_USER_ACCESS_REG_0, respectively. |
MDIO_USER_INT_MASK_SET_REG is shown in Figure 6-660 and described in Table 6-1308.
Return to Summary Table.
MDIO User Interrupt Mask Set Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2428h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2428h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USERINTMASKSET | ||||||
R/W-X | R/W1S-0h | ||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | USERINTMASKSET | R/W1S | 0h | MDIO user interrupt mask set for
USERINTMASKED[1:0], respectively. |
MDIO_USER_INT_MASK_CLEAR_REG is shown in Figure 6-661 and described in Table 6-1310.
Return to Summary Table.
MDIO User Interrupt Mask Clear Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 242Ch |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 242Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USERINTMASKCLR | ||||||
R/W-X | R/W1C-0h | ||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | USERINTMASKCLR | R/W1C | 0h | MDIO user command complete interrupt mask clear
for USERINTMASKED[1:0], respectively. |
MDIO_MANUAL_IF_REG is shown in Figure 6-662 and described in Table 6-1312.
Return to Summary Table.
MDIO Manual Interface Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2430h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2430h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MDIO_MDCLK_O | MDIO_OE | MDIO_PIN | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2 | MDIO_MDCLK_O | R/W | 0h | MDIO Clock Output. |
1 | MDIO_OE | R/W | 0h | MDIO Output Enable. |
0 | MDIO_PIN | R/W | 0h | MDIO_Pin Value. |
MDIO_POLL_REG is shown in Figure 6-663 and described in Table 6-1314.
Return to Summary Table.
MDIO Poll Inter Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2434h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2434h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MANUALMODE | STATECHANGEMODE | RESERVED | |||||
R/W-0h | R/W-0h | R/W-X | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPG | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | MANUALMODE | R/W | 0h | Manual Mode. |
30 | STATECHANGEMODE | R/W | 0h | State Change Mode. |
29-8 | RESERVED | R/W | X | |
7-0 | IPG | R/W | 0h | Polling Inter Packet Gap Value. |
MDIO_POLL_EN_REG is shown in Figure 6-664 and described in Table 6-1316.
Return to Summary Table.
MDIO Poll Enable Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2438h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2438h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POLL_EN | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | POLL_EN | R/W | FFFFFFFFh | Poll Enable. |
MDIO_CLAUS45_REG is shown in Figure 6-665 and described in Table 6-1318.
Return to Summary Table.
Claus 45 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 243Ch |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 243Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLAUSE45 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLAUSE45 | R/W | 0h | MDIO clause 45 mode. |
MDIO_USER_ADDR0_REG is shown in Figure 6-666 and described in Table 6-1320.
Return to Summary Table.
MDIO User Address 0 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2440h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2440h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USER_ADDR0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | USER_ADDR0 | R/W | 0h | User Address 0. |
MDIO_USER_ADDR1_REG is shown in Figure 6-667 and described in Table 6-1322.
Return to Summary Table.
MDIO User Address 1 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2444h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2444h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USER_ADDR1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | USER_ADDR1 | R/W | 0h | User Address 1. |
MDIO_USER_ACCESS_REG_j is shown in Figure 6-668 and described in Table 6-1324.
Return to Summary Table.
MDIO User Access j Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2480h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2480h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GO | WRITE | ACK | RESERVED | REGADR | |||
R/W1S-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
REGADR | PHYADR | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DATA | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GO | R/W1S | 0h | Go. |
30 | WRITE | R/W | 0h | Write enable. |
29 | ACK | R/W | 0h | Acknowledge. |
28-26 | RESERVED | R/W | X | |
25-21 | REGADR | R/W | 0h | Register address. |
20-16 | PHYADR | R/W | 0h | PHY address. |
15-0 | DATA | R/W | 0h | User data. |
MDIO_USER_PHY_SEL_REG_j is shown in Figure 6-669 and described in Table 6-1326.
Return to Summary Table.
MDIO User PHY Select j Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MDIO_V1P7_MDIO | 3003 2484h |
PRU_ICSSG1_PR1_MDIO_V1P7_MDIO | 300B 2484h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINKSEL | LINKINT_ENABLE | RESERVED | PHYADR_MON | ||||
R/W-0h | R/W-0h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7 | LINKSEL | R/W | 0h | Link status determination select. |
6 | LINKINT_ENABLE | R/W | 0h | Link change interrupt enable. |
5 | RESERVED | R/W | X | |
4-0 | PHYADR_MON | R/W | 0h | PHY address whose link status is to be monitored. |