SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-562 lists the memory-mapped registers for the PRU_ICSSG_DDRAM0 registers. All register offset addresses not listed in Table 6-562 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PRU_ICSSG0_DRAM0_SLV_RAM | 3000 0000h |
PRU_ICSSG1_DRAM0_SLV_RAM | 3008 0000h |
PRU_ICSSG0_DRAM1_SLV_RAM | 3000 2000h |
PRU_ICSSG1_DRAM1_SLV_RAM | 3008 2000h |
Offset | Acronym | Register Name | PRU_ICSSG0_DRAM0_SLV_RAM Physical Address | PRU_ICSSG1_DRAM0_SLV_RAM Physical Address |
---|---|---|---|---|
0h + formula | ICSSG_DRAM_REG_y | RAM memory word | 3000 0000h + formula | 3008 0000h + formula |
Offset | Acronym | Register Name | PRU_ICSSG0_DRAM1_SLV_RAM Physical Address | PRU_ICSSG1_DRAM1_SLV_RAM Physical Address |
---|---|---|---|---|
0h + formula | ICSSG_DRAM_REG_y | RAM memory word | 3000 2000h + formula | 3008 2000h + formula |
ICSSG_DRAM_REG_y is shown in Figure 6-295 and described in Table 6-565.
Return to Summary Table.
The RAM memory words provide memory mapped random access data storage.
Offset = 0h + (y * 4h); where y = 0h to 7FFh
Instance | Physical Address |
---|---|
PRU_ICSSG0_DRAM0_SLV_RAM | 3000 0000h + formula |
PRU_ICSSG0_DRAM1_SLV_RAM | 3000 2000h + formula |
PRU_ICSSG1_DRAM0_SLV_RAM | 3008 0000h + formula |
PRU_ICSSG1_DRAM1_SLV_RAM | 3008 2000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTE3 | BYTE2 | BYTE1 | BYTE0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | BYTE3 | R/W | 0h | This is the MSB (Most Significant Byte) |
23-16 | BYTE2 | R/W | 0h | This is the UMB (Upper Middle Byte) |
15-8 | BYTE1 | R/W | 0h | This is the LMB (Lower Middle Byte) |
7-0 | BYTE0 | R/W | 0h | This is the LSB (Least Significant Byte) |