SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 10-44 shows the Timer Manager integration.
Table 10-85 and Table 10-86 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
TIMER_MGR0 | PSC0 | GP | LPSC0 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
TIMER_MGR0 | TIMER_MGR0_ICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | Timer Manager0 interface clock |
EON_TICK_EVT | CPTS0_CPTS_GENF0_0 | CPTS0 | Timer Manager0 asynchronous tick event | |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
TIMER_MGR0 | TIMER_MGR0_RST | MODSS_RST | LPSC0 | Timer Manager0 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
TIMER_MGR0 | TIMERMGR0_EVT | DMSS EVENT | DMSS | Timer expiration events ×1024 | ETL |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
TIMER_MGR0 | - | - | - | No PDMA channels to external DMA engines | - |