SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 10-7 lists the memory-mapped registers for the CPTS. All register offset addresses not listed in Table 10-7 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPTS0 | 3900 0000h |
Offset | Acronym | Register Name | CPTS0 Physical Address |
---|---|---|---|
0h | CPTS_IDVER_REG | Identification and Version | 3900 0000h |
4h | CPTS_CONTROL_REG | Time Sync Control | 3900 0004h |
8h | CPTS_RFTCLK_SEL_REG | RFTCLK Select | 3900 0008h |
Ch | CPTS_TS_PUSH_REG | Time Stamp Event Push | 3900 000Ch |
10h | CPTS_TS_LOAD_VAL_REG | Time Stamp Load Low Value | 3900 0010h |
14h | CPTS_TS_LOAD_EN_REG | Time Stamp Load Enable | 3900 0014h |
18h | CPTS_TS_COMP_VAL_REG | Time Stamp Comparison Low Value | 3900 0018h |
1Ch | CPTS_TS_COMP_LEN_REG | Time Stamp Comparison Length | 3900 001Ch |
20h | CPTS_INTSTAT_RAW_REG | Interrupt Status Register Raw | 3900 0020h |
24h | CPTS_INTSTAT_MASKED_REG | Interrupt Status Register Masked | 3900 0024h |
28h | CPTS_INT_ENABLE_REG | Interrupt Enable Register | 3900 0028h |
2Ch | CPTS_TS_COMP_NUDGE_REG | Time Stamp Comparison Nudge | 3900 002Ch |
30h | CPTS_EVENT_POP_REG | Event Pop | 3900 0030h |
34h | CPTS_EVENT_0_REG | Event Register 0 | 3900 0034h |
38h | CPTS_EVENT_1_REG | Event Register 1 | 3900 0038h |
3Ch | CPTS_EVENT_2_REG | Event Register 2 | 3900 003Ch |
40h | CPTS_EVENT_3_REG | Event Register 3 | 3900 0040h |
44h | CPTS_TS_LOAD_HIGH_VAL_REG | Time Stamp Load High Value | 3900 0044h |
48h | CPTS_TS_COMP_HIGH_VAL_REG | Time Stamp Comparison High Value | 3900 0048h |
4Ch | CPTS_TS_ADD_VAL_REG | Time Stamp Add Value | 3900 004Ch |
50h | CPTS_TS_PPM_LOW_VAL_REG | Time Stamp PPM Low Value | 3900 0050h |
54h | CPTS_TS_PPM_HIGH_VAL_REG | Time Stamp PPM High Value | 3900 0054h |
58h | CPTS_TS_NUDGE_VAL_REG | Time Stamp Nudge Value | 3900 0058h |
D0h | CPTS_TS_CONFIG_REG | Time Stamp Configuration Read | 3900 00D0h |
E0h + formula | CPTS_TS_GENF_COMP_LOW_REG_j | Time Stamp Generate Function j Comparison Low Value | 3900 00E0h + formula |
E4h + formula | CPTS_TS_GENF_COMP_HIGH_REG_j | Time Stamp Generate Function j Comparison high Value | 3900 00E4h + formula |
E8h + formula | CPTS_TS_GENF_CONTROL_REG_j | Time Stamp Generate Function j Control | 3900 00E8h + formula |
ECh + formula | CPTS_TS_GENF_LENGTH_REG_j | Time Stamp Generate Function j Length Value | 3900 00ECh + formula |
F0h + formula | CPTS_TS_GENF_PPM_LOW_REG_j | Time Stamp Generate Function j PPM Low Value | 3900 00F0h + formula |
F4h + formula | CPTS_TS_GENF_PPM_HIGH_REG_j | Time Stamp Generate Function j PPM High Value | 3900 00F4h + formula |
F8h + formula | CPTS_TS_GENF_NUDGE_REG_j | Time Stamp Generate Function j Nudge Value | 3900 00F8h + formula |
200h | CPTS_TS_ESTF_COMP_LOW_REG | Time Stamp ESTF Generate Function Comparison Low Value | 3900 0200h |
204h | CPTS_TS_ESTF_COMP_HIGH_REG | Time Stamp ESTF Generate Function Comparison high Value | 3900 0204h |
208h | CPTS_TS_ESTF_CONTROL_REG | Time Stamp ESTF Generate Function Control | 3900 0208h |
20Ch | CPTS_TS_ESTF_LENGTH_REG | Time Stamp ESTF Generate Function Length Value | 3900 020Ch |
210h | CPTS_TS_ESTF_PPM_LOW_REG | Time Stamp ESTF Generate Function PPM Low Value | 3900 0210h |
214h | CPTS_TS_ESTF_PPM_HIGH_REG | Time Stamp ESTF Generate Function PPM High Value | 3900 0214h |
218h | CPTS_TS_ESTF_NUDGE_REG | Time Stamp ESTF Generate Function Nudge Value | 3900 0218h |
CPTS_IDVER_REG is shown in Figure 10-5 and described in Table 10-9.
Return to Summary Table.
Identification and Version Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_IDENT | |||||||||||||||
R-4E8Ah | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-1h | R-Ch | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TX_IDENT | R | 4E8Ah | Identification value |
15-11 | RTL_VER | R | RTL version value |
|
10-8 | MAJOR_VER | R | 1h | Major version value |
7-0 | MINOR_VER | R | R-Ch | Minor version value |
CPTS_CONTROL_REG is shown in Figure 10-6 and described in Table 10-11.
Return to Summary Table.
Time Sync Control Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TS_SYNC_SEL | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TX_GENF_CLR_EN | TS_RX_NO_EVENT | |||||
R/W-X | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HW8_TS_PUSH_EN | HW7_TS_PUSH_EN | HW6_TS_PUSH_EN | HW5_TS_PUSH_EN | HW4_TS_PUSH_EN | HW3_TS_PUSH_EN | HW2_TS_PUSH_EN | HW1_TS_PUSH_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_DIR | TS_COMP_TOG | MODE | SEQUENCE_EN | TSTAMP_EN | TS_COMP_POLARITY | INT_TEST | CPTS_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | TS_SYNC_SEL | R/W | 0h | TS_SYNC output timestamp counter bit select 0000 – TS_SYNC disabled 00010001..1111 - TS_SYNC is timestamp counter bits 31 (1111) down to 17 (0001) |
27-18 | RESERVED | R/W | X | |
17 | TX_GENF_CLR_EN | R/W | 0h | GENF (and ESTF) Clear Enable. 0 - A TS_GENFn output is not cleared when the associated CPTS_TS_GENF_LENGTH_REG_j[31:0] LENGTH field is cleared to zero. 1 - A TS_GENFn output is cleared when the associated CPTS_TS_GENF_LENGTH_REG_j[31:0] LENGTH field is cleared to zero. |
16 | TS_RX_NO_EVENT | R/W | 0h | Timestamp Ethernet Receive produces no events. 0 - Ethernet receive timesync events enabled 1 - Ethernet receive timesync events disabled |
15 | HW8_TS_PUSH_EN | R/W | 0h | Hardware push 8 enable |
14 | HW7_TS_PUSH_EN | R/W | 0h | Hardware push 7 enable |
13 | HW6_TS_PUSH_EN | R/W | 0h | Hardware push 6 enable |
12 | HW5_TS_PUSH_EN | R/W | 0h | Hardware push 5 enable |
11 | HW4_TS_PUSH_EN | R/W | 0h | Hardware push 4 enable |
10 | HW3_TS_PUSH_EN | R/W | 0h | Hardware push 3 enable |
9 | HW2_TS_PUSH_EN | R/W | 0h | Hardware push 2 enable |
8 | HW1_TS_PUSH_EN | R/W | 0h | Hardware push 1 enable |
7 | TS_PPM_DIR | R/W | 0h | Timestamp PPM Direction 0 – Increase the time_stamp[63:0] value by the PPM value1 – Decrease the time_stamp[63:0] value by the PPM value |
6 | TS_COMP_TOG | R/W | 0h | Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode 1=TS_COMP is in toggle mode |
5 | MODE | R/W | 0h | Timestamp mode 0 – The timestamp is 32-bits with the upper 32-bits forced to zero.1 – The timestamp is 64-bits. |
4 | SEQUENCE_EN | R/W | 0h | Sequence Enable 0 – The timestamp value increments with the selected RFTCLK1 - The timestamp for received packets is the sequence number of the received packet (first packet is 1, second packet is 2, etc). |
3 | TSTAMP_EN | R/W | 0h | Host Receive Timestamp Enable 0 – Timestamps are disabled on received packets to host1 – Timestamps enabled on received packets to host (cpts_en must be set) |
2 | TS_COMP_POLARITY | R/W | 1h | TS_COMP polarity 0 – TS_COMP is asserted low1 – TS_COMP is asserted high |
1 | INT_TEST | R/W | 0h | Interrupt test When set, this bit allows the raw interrupt to be written to facilitate interrupt test. |
0 | CPTS_EN | R/W | 0h | Time sync enable When disabled (cleared to zero), the RCLK domain is held in reset. |
CPTS_RFTCLK_SEL_REG is shown in Figure 10-7 and described in Table 10-13.
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RFTCLK Select Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RFTCLK_SEL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4-0 | RFTCLK_SEL | R/W | 0h | Reference clock select. |
CPTS_TS_PUSH_REG is shown in Figure 10-8 and described in Table 10-15.
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Time Stamp Event Push Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PUSH | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_PUSH | W | 0h | Time stamp event push When a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register, not the time of the event read. The time stamp value can then be read on interrupt via the event registers. Software should not push a second time stamp event onto the event FIFO until the first time stamp value has been read from the event FIFO (there should be only one time stamp event in the event FIFO at any given time). |
CPTS_TS_LOAD_VAL_REG is shown in Figure 10-9 and described in Table 10-17.
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Time Stamp Load Low Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time stamp load low value Writing the ts_load_en bit causes ts_load[63:0] to be written into the time stamp. The time stamp value is read by initiating a time stamp push event, not by reading this register. When reading this register, the value read is not the time stamp, but is the value that was last written to this register. |
CPTS_TS_LOAD_EN_REG is shown in Figure 10-10 and described in Table 10-19.
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Time Stamp Load Enable Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_LOAD_EN | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_LOAD_EN | W | 0h | Time stamp load enable Writing a one to this bit enables the time stamp value to be written with the value in ts_load[63:0]. This bit is write only and will be cleared by the hardware after one clock. The upper 32-bits of the timestamp are forced to zero in 32-bit mode. |
CPTS_TS_COMP_VAL_REG is shown in Figure 10-11 and described in Table 10-21.
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Time Stamp Comparison Low Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_VAL | R/W | 0h | Time stamp comparison low value Writing a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent to ts_comp_val. |
CPTS_TS_COMP_LEN_REG is shown in Figure 10-12 and described in Table 10-23.
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Time Stamp Comparison Length Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_LENGTH | R/W | 0h | Time stamp comparison length Writing a non-zero value to this field enables the time stamp comparison event and output. This value should be zero when the TS_Comp_Low and TS_Comp_High registers are written. |
CPTS_INTSTAT_RAW_REG is shown in Figure 10-13 and described in Table 10-25.
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Interrupt Status Register Raw
Instance | Physical Address |
---|---|
CPTS0 | 3900 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_RAW | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_RAW | R/W | 0h | TS_PEND_RAW int read (before enable) Writable when int_test = 1. A one in this bit indicates that there are one or more events in the event FIFO. |
CPTS_INTSTAT_MASKED_REG is shown in Figure 10-14 and described in Table 10-27.
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Interrupt Status Register Masked
Instance | Physical Address |
---|---|
CPTS0 | 3900 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | TS_PEND | R | 0h | TS_PEND masked interrupt read (after enable) |
CPTS_INT_ENABLE_REG is shown in Figure 10-15 and described in Table 10-29.
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Interrupt Enable Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_EN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_EN | R/W | 0h | TS_PEND masked interrupt enable |
CPTS_TS_COMP_NUDGE_REG is shown in Figure 10-16 and described in Table 10-31.
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Time Stamp Comparison Nudge Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount Only a single high or low time is adjusted and the ts_comp_nudge value is cleared to zero when the nudge has occurred. |
CPTS_EVENT_POP_REG is shown in Figure 10-17 and described in Table 10-33.
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Event Pop Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVENT_POP | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | EVENT_POP | W | 0h | Event pop When a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read from the Event_0-3 registers. Popping an event discards the event and causes the next event, if any, to be moved to the top of the FIFO ready to be read by software on interrupt. |
CPTS_EVENT_0_REG is shown in Figure 10-18 and described in Table 10-35.
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Event 0 Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp The timestamp is valid for transmit, receive, and time stamp push event types. The timestamp value is not valid for counter roll event types. |
CPTS_EVENT_1_REG is shown in Figure 10-19 and described in Table 10-37.
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Event 1 Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PREMPT_QUEUE | PORT_NUMBER | |||||
R-X | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EVENT_TYPE | MESSAGE_TYPE | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQUENCE_ID | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQUENCE_ID | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | X | |
29 | PREMPT_QUEUE | R | 0h | Prempt QUEUE 0 – The packet was received/transmitted on the express queue. 1 – The packet was received/transmitted on the prempt queue. |
28-24 | PORT_NUMBER | R | 0h | Port number indicates the port number (encoded) of an Ethernet event or the encoded hardware timestamp number. |
23-20 | EVENT_TYPE | R | 0h | Event type 0000 – Time Stamp Push Event 0001 – Time Stamp Rollover Event 0010 – Time Stamp Half Rollover Event 0011 – Hardware Time Stamp Push Event 0100 – Ethernet Receive Event 0101 – Ethernet Transmit Event 0110 – Time Stamp Compare Event 0111 – Host Transmit Event 1000 1111 reserved |
19-16 | MESSAGE_TYPE | R | 0h | Message type The message type value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events. |
15-0 | SEQUENCE_ID | R | 0h | Sequence ID The 16-bit sequence id is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events. |
CPTS_EVENT_2_REG is shown in Figure 10-20 and described in Table 10-39.
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Event 2 Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOMAIN | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | DOMAIN | R | 0h | Domain The 8-bit domain is the value that was contained in an Ethernet transmit or receive time sync packet. This field is valid only for Ethernet transmit or receive events. |
CPTS_EVENT_3_REG is shown in Figure 10-21 and described in Table 10-41.
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Event 3 Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp The timestamp upper 32-bits are valid for transmit, receive, and time stamp push event types. This value is zero in 32-bit mode. |
CPTS_TS_LOAD_HIGH_VAL_REG is shown in Figure 10-22 and described in Table 10-43.
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Time Stamp Load High Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time stamp load high value Writing the ts_load_en bit causes the value contained in this register (and the ts_load[63:0]) to be written into the time stamp. The time stamp value is read by initiating a time stamp push event, not by reading this register. When reading this register, the value read is not the time stamp, but is the value that was last written to this register. This value is unused in 32-bit mode |
CPTS_TS_COMP_HIGH_VAL_REG is shown in Figure 10-23 and described in Table 10-45.
Return to Summary Table.
Time Stamp Comparison High Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_HIGH_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_HIGH_VAL | R/W | 0h | Time stamp comparison high value Writing a non-zero value to the TS_Comp_Length[31:0] register causes a pulse of TS_Comp_Length RCLK periods on the TS_COMP output and a comparison event when the time_stamp counter value is equivalent to ts_comp_val[63:0]. This value is unused in 32-bit mode. The upper 32-bits in this register should be written before the lower 32-bits in the TS_Comp_Low register. |
CPTS_TS_ADD_VAL_REG is shown in Figure 10-24 and described in Table 10-47.
Return to Summary Table.
TS Add Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADD_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | ADD_VAL | R/W | 0h | Add Value Add Value is added to 1 to comprise the timestamp increment value. The timestamp increment value is added to the current timestamp (time_stamp[63:0]) on each RCLK. The timestamp increment value can be adjusted by nudge and ppm also. The ts_add_val[2:0] value may be non-zero in 64-bit mode only. |
CPTS_TS_PPM_LOW_VAL_REG is shown in Figure 10-25 and described in Table 10-49.
Return to Summary Table.
Time Stamp PPM Low Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_LOW_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_PPM_LOW_VAL | R/W | 0h | Time stamp PPM Low value The 64-bit PPM value takes effect when this low value is written. The high value should be written first.Note: There should be at least 10 clocks in between writes to the low register to ensure that the previous operation has been seen |
CPTS_TS_PPM_HIGH_VAL_REG is shown in Figure 10-26 and described in Table 10-51.
Return to Summary Table.
Time Stamp PPM High Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PPM_HIGH_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | TS_PPM_HIGH_VAL | R/W | 0h | Time stamp PPM High value This value should be written first (before the low value is written). The minimum value of the ts_ppm is 0x400 (all 42 bits). |
CPTS_TS_NUDGE_VAL_REG is shown in Figure 10-27 and described in Table 10-53.
Return to Summary Table.
Time Stamp Nudge Value Register
Instance | Physical Address |
---|---|
CPTS0 | 3900 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_NUDGE_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | TS_NUDGE_VAL | R/W | 0h | Time stamp Nudge value This two’s complement number is added to the time_stamp[63:0] value to increase or decrease the timestamp value by the ts_nudge amount. The ts_nudge value is cleared to zero when the nudge has occurred. |
CPTS_TS_CONFIG_REG is shown in Figure 10-28 and described in Table 10-55.
Return to Summary Table.
Time Stamp Configuration Read
Instance | Physical Address |
---|---|
CPTS0 | 3900 00D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVNT_FIFO_DEPTH | NUM_GENF | ||||||||||||||
R-20h | R-6h | ||||||||||||||
LEGEND: R = Read; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | EVNT_FIFO_DEPTH | R | 20h | The event FIFO depth. |
7-0 | NUM_GENF | R | 6h | The number of CPTS GENF outputs. |
CPTS_COMP_LOW_REG_j is shown in Figure 10-29 and described in Table 10-57.
Return to Summary Table.
Time Stamp Generate Function Comparison Low Value
Offset = E0h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00E0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp Generate Function Comparison Low Value This value should be written after the upper 32-bits. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero. |
CPTS_COMP_HIGH_REG_j is shown in Figure 10-30 and described in Table 10-59.
Return to Summary Table.
Time Stamp Generate Function Comparison high Value
Offset = E4h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00E4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp Generate Function Comparison High Value This value should be written before the lower 32-bits are written. The ts_GENFn_comp high and low should only be written when the ts_GENFn_length value is zero. |
CPTS_CONTROL_REG_j is shown in Figure 10-31 and described in Table 10-61.
Return to Summary Table.
Time Stamp Generate Function Control
Offset = E8h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00E8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_DIR | POLARITY_INV | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | PPM_DIR | R/W | 0h | Time Stamp Generate Function PPM Direction 0 – A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount.1 – A single RCLK is subtracted from the generate function counter at the PPM rate which has the effect of increasing the generate function frequency by the PPM amount. |
0 | POLARITY_INV | R/W | 0h | Time Stamp Generate Function Polarity Invert 0 – The output TS_GENFn signal asserts high1 – The output TS_GENFn signal asserts low |
CPTS_LENGTH_REG_j is shown in Figure 10-32 and described in Table 10-63.
Return to Summary Table.
Time Stamp Generate Function Length Value
Offset = ECh + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00ECh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp Generate Function Length Value The minimum value is decimal 5 |
CPTS_PPM_LOW_REG_j is shown in Figure 10-33 and described in Table 10-65.
Return to Summary Table.
Time Stamp Generate Function PPM Low Value
Offset = F0h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00F0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp Generate Function PPM Low Value The 64-bit PPM value takes effect when this low value is written. The high value should be written first |
CPTS_PPM_HIGH_REG_j is shown in Figure 10-34 and described in Table 10-67.
Return to Summary Table.
Time Stamp Generate Function PPM High Value
Offset = F4h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00F4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp Generate Function PPM High Value This value should be written first (before the low value is written). |
CPTS_NUDGE_REG_j is shown in Figure 10-35 and described in Table 10-69.
Return to Summary Table.
Time Stamp Generate Function Nudge Value
Offset = F8h + (j * 20h); where j = 0h to 5h
Instance | Physical Address |
---|---|
CPTS0 | 3900 00F8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp Generate Function Nudge Value This two’s complement number is added to the generate counter value to increase or decrease the length by the ts_genfN_nudge amount. Only a single high or low time is adjusted and the ts_genfN_nudge value is cleared to zero when the nudge has occurred. |
CPTS_COMP_LOW_REG is shown in Figure 10-36 and described in Table 10-71.
Return to Summary Table.
Time Stamp ESTF Generate Function Comparison Low Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp ESTF Generate Function Comparison Low Value This value should be written after the upper 32-bits. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero. |
CPTS_COMP_HIGH_REG is shown in Figure 10-37 and described in Table 10-73.
Return to Summary Table.
Time Stamp ESTF Generate Function Comparison high Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp ESTF Generate Function Comparison High Value This value should be written before the lower 32-bits are written. The ts_ESTFn_comp high and low should only be written when the ts_ESTFn_length value is zero |
CPTS_CONTROL_REG is shown in Figure 10-38 and described in Table 10-75.
Return to Summary Table.
Time Stamp ESTF Generate Function Control
Instance | Physical Address |
---|---|
CPTS0 | 3900 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_DIR | POLARITY_INV | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | PPM_DIR | R/W | 0h | Time Stamp ESTF Generate Function PPM Direction 0 – A single RCLK is added to the generate function counter at the PPM rate which has the effect of decreasing the generate function frequency by the PPM amount.1 – A single RCLK is subtracted from the generate function counter at the PPM rate which has the effect of increasing the generate function frequency by the PPM amount. |
0 | POLARITY_INV | R/W | 0h | Time Stamp ESTF Generate Function Polarity Invert 0 – The output TS_ESTFn signal asserts low1 – The output TS_ESTFn signal asserts high |
CPTS_LENGTH_REG is shown in Figure 10-39 and described in Table 10-77.
Return to Summary Table.
Time Stamp ESTF Generate Function Length Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp ESTF Generate Function Length Value |
CPTS_PPM_LOW_REG is shown in Figure 10-40 and described in Table 10-79.
Return to Summary Table.
Time Stamp ESTF Generate Function PPM Low Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 0210h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp ESTF Generate Function PPM Low Value The 64-bit PPM value takes effect when this low value is written. The high value should be written first. |
CPTS_PPM_HIGH_REG is shown in Figure 10-41 and described in Table 10-81.
Return to Summary Table.
Time Stamp ESTF Generate Function PPM High Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 0214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp ESTF Generate Function PPM High Value This value should be written first (before the low value is written). |
CPTS_NUDGE_REG is shown in Figure 10-42 and described in Table 10-83.
Return to Summary Table.
Time Stamp ESTF Generate Function Nudge Value
Instance | Physical Address |
---|---|
CPTS0 | 3900 0218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp ESTF Generate Function Nudge Value This two’s complement number is added to the generate counter value to increase or decrease the length by the ts_estfN_nudge amount. Only a single high or low time is adjusted and the ts_estfN_nudge value is cleared to zero when the nudge has occurred. |