SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
In 28-bit shift in mode, the device-level, general-purpose input pin PRU<n>_DATAIN is sampled and shifted into a 28-bit shift register on an internal clock pulse. The register fills in LSB order (from bit 0 to 27) and then overflows into a bit bucket. The 28-bit register is mapped to pru<n>_r31_status[0:27] and can be cleared in software through the ICSSG_GPCFG0_REG[13] PRU0_GPI_SB register (PRU0 or PRU1).
Note that by default, the PRU will continually capture and shift the DATAIN input when the GPI mode has been set. However, clearing the ICSSG_GPCFG0_REG[1] PRU0_GPI_SHIFT_EN bit will freeze the shift operation.
The shift rate is controlled by the effective divisor of two cascaded dividers applied to the ICSSG<n>_CORE_CLK clock. These cascaded dividers can each be configured through the PRU_ICSSG CFG register space to a value of {1, 1.5, …, 16}. Table 6-413 shows sample effective clock values and the divisor values that can be used to generate clocks from a 200MHz ICSSG<n>_CORE_CLK clock.
Generated clock | PRU0_GPI_DIV0 | PRU0_GPI_DIV1 |
---|---|---|
8-MHz | 12.5 (17h) | 2 (02h) |
10-MHz | 10 (12h) | 2 (02h) |
16-MHz | 12.5 (17h) | 1 (00h) |
20-MHz | 10 (12h) | 1 (00h) |
The 28-bit shift mode also supports the following features: