SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | FSIRX0 | FSIRX1 | FSIRX2 | Section |
---|---|---|---|---|---|---|---|
0 h | 1 | RX_MASTER_CTRL_ALTB_ | RX_MASTER_CTRL_ALTB_ | 2350 0000 h | 2351 0000 h | 2352 0000 h | Go To |
2 h | 1 | RESERVED | Reserved | 2350 0002 h | 2351 0002 h | 2352 0002 h | Go To |
4 h | 1 | RESERVED | Reserved | 2350 0004 h | 2351 0004 h | 2352 0004 h | Go To |
6 h | 1 | RESERVED | Reserved | 2350 0006 h | 2351 0006 h | 2352 0006 h | Go To |
8 h | 1 | RX_OPER_CTRL | RX_OPER_CTRL | 2350 0008 h | 2351 0008 h | 2352 0008 h | Go To |
A h | 1 | RESERVED | Reserved | 2350 000A h | 2351 000A h | 2352 000A h | Go To |
C h | 1 | RX_FRAME_INFO | RX_FRAME_INFO | 2350 000C h | 2351 000C h | 2352 000C h | Go To |
E h | 1 | RX_FRAME_TAG_UDATA | RX_FRAME_TAG_UDATA | 2350 000E h | 2351 000E h | 2352 000E h | Go To |
10 h | 1 | RX_DMA_CTRL | RX_DMA_CTRL | 2350 0010 h | 2351 0010 h | 2352 0010 h | Go To |
12 h | 1 | RESERVED | Reserved | 2350 0012 h | 2351 0012 h | 2352 0012 h | Go To |
14 h | 1 | RX_EVT_STS_ALT1_ | RX_EVT_STS_ALT1_ | 2350 0014 h | 2351 0014 h | 2352 0014 h | Go To |
16 h | 1 | RX_CRC_INFO | RX_CRC_INFO | 2350 0016 h | 2351 0016 h | 2352 0016 h | Go To |
18 h | 1 | RX_EVT_CLR_ALT1_ | RX_EVT_CLR_ALT1_ | 2350 0018 h | 2351 0018 h | 2352 0018 h | Go To |
1A h | 1 | RX_EVT_FRC_ALT1_ | RX_EVT_FRC_ALT1_ | 2350 001A h | 2351 001A h | 2352 001A h | Go To |
1C h | 1 | RX_BUF_PTR_LOAD | RX_BUF_PTR_LOAD | 2350 001C h | 2351 001C h | 2352 001C h | Go To |
1E h | 1 | RX_BUF_PTR_STS | RX_BUF_PTR_STS | 2350 001E h | 2351 001E h | 2352 001E h | Go To |
20 h | 1 | RX_FRAME_WD_CTRL | RX_FRAME_WD_CTRL | 2350 0020 h | 2351 0020 h | 2352 0020 h | Go To |
22 h | 1 | RESERVED | Reserved | 2350 0022 h | 2351 0022 h | 2352 0022 h | Go To |
24 h | 1 | RX_FRAME_WD_REF | RX_FRAME_WD_REF | 2350 0024 h | 2351 0024 h | 2352 0024 h | Go To |
28 h | 1 | RX_FRAME_WD_CNT | RX_FRAME_WD_CNT | 2350 0028 h | 2351 0028 h | 2352 0028 h | Go To |
2C h | 1 | RX_PING_WD_CTRL | RX_PING_WD_CTRL | 2350 002C h | 2351 002C h | 2352 002C h | Go To |
2E h | 1 | RX_PING_TAG | RX_PING_TAG | 2350 002E h | 2351 002E h | 2352 002E h | Go To |
30 h | 1 | RX_PING_WD_REF | RX_PING_WD_REF | 2350 0030 h | 2351 0030 h | 2352 0030 h | Go To |
34 h | 1 | RX_PING_WD_CNT | RX_PING_WD_CNT | 2350 0034 h | 2351 0034 h | 2352 0034 h | Go To |
38 h | 1 | RX_INT1_CTRL_ALT1_ | RX_INT1_CTRL_ALT1_ | 2350 0038 h | 2351 0038 h | 2352 0038 h | Go To |
3A h | 1 | RX_INT2_CTRL_ALT1_ | RX_INT2_CTRL_ALT1_ | 2350 003A h | 2351 003A h | 2352 003A h | Go To |
3C h | 1 | RX_LOCK_CTRL | RX_LOCK_CTRL | 2350 003C h | 2351 003C h | 2352 003C h | Go To |
3E h | 1 | RESERVED | Reserved | 2350 003E h | 2351 003E h | 2352 003E h | Go To |
40 h | 1 | RX_ECC_DATA | RX_ECC_DATA | 2350 0040 h | 2351 0040 h | 2352 0040 h | Go To |
44 h | 1 | RX_ECC_VAL | RX_ECC_VAL | 2350 0044 h | 2351 0044 h | 2352 0044 h | Go To |
46 h | 1 | RESERVED | Reserved | 2350 0046 h | 2351 0046 h | 2352 0046 h | Go To |
48 h | 1 | RX_ECC_SEC_DATA | RX_ECC_SEC_DATA | 2350 0048 h | 2351 0048 h | 2352 0048 h | Go To |
4C h | 1 | RX_ECC_LOG | RX_ECC_LOG | 2350 004C h | 2351 004C h | 2352 004C h | Go To |
4E h | 1 | RESERVED | Reserved | 2350 004E h | 2351 004E h | 2352 004E h | Go To |
50 h | 1 | RX_FRAME_TAG_CMP | RX_FRAME_TAG_CMP | 2350 0050 h | 2351 0050 h | 2352 0050 h | Go To |
52 h | 1 | RX_PING_TAG_CMP | RX_PING_TAG_CMP | 2350 0052 h | 2351 0052 h | 2352 0052 h | Go To |
54 h | 6 | RESERVED | Reserved | 2350 0054 h | 2351 0054 h | 2352 0054 h | Go To |
60 h | 1 | RX_DLYLINE_CTRL | RX_DLYLINE_CTRL | 2350 0060 h | 2351 0060 h | 2352 0060 h | Go To |
62 h | 7 | RESERVED | Reserved | 2350 0062 h | 2351 0062 h | 2352 0062 h | Go To |
70 h | 1 | RX_VIS_1 | RX_VIS_1 | 2350 0070 h | 2351 0070 h | 2352 0070 h | Go To |
74 h | 6 | RESERVED | Reserved | 2350 0074 h | 2351 0074 h | 2352 0074 h | Go To |
80 h | 16 | RX_BUF_BASE | RX_BUF_BASE | 2350 0080 h | 2351 0080 h | 2352 0080 h | Go To |
Offset | Length | Acronym | Register Name | FSIRX3 | FSIRX4 | FSIRX5 | Section |
---|---|---|---|---|---|---|---|
0 h | 1 | RX_MASTER_CTRL_ALTB_ | RX_MASTER_CTRL_ALTB_ | 2353 0000 h | 2354 0000 h | 2355 0000 h | Go To |
2 h | 1 | RESERVED | Reserved | 2353 0002 h | 2354 0002 h | 2355 0002 h | Go To |
4 h | 1 | RESERVED | Reserved | 2353 0004 h | 2354 0004 h | 2355 0004 h | Go To |
6 h | 1 | RESERVED | Reserved | 2353 0006 h | 2354 0006 h | 2355 0006 h | Go To |
8 h | 1 | RX_OPER_CTRL | RX_OPER_CTRL | 2353 0008 h | 2354 0008 h | 2355 0008 h | Go To |
A h | 1 | RESERVED | Reserved | 2353 000A h | 2354 000A h | 2355 000A h | Go To |
C h | 1 | RX_FRAME_INFO | RX_FRAME_INFO | 2353 000C h | 2354 000C h | 2355 000C h | Go To |
E h | 1 | RX_FRAME_TAG_UDATA | RX_FRAME_TAG_UDATA | 2353 000E h | 2354 000E h | 2355 000E h | Go To |
10 h | 1 | RX_DMA_CTRL | RX_DMA_CTRL | 2353 0010 h | 2354 0010 h | 2355 0010 h | Go To |
12 h | 1 | RESERVED | Reserved | 2353 0012 h | 2354 0012 h | 2355 0012 h | Go To |
14 h | 1 | RX_EVT_STS_ALT1_ | RX_EVT_STS_ALT1_ | 2353 0014 h | 2354 0014 h | 2355 0014 h | Go To |
16 h | 1 | RX_CRC_INFO | RX_CRC_INFO | 2353 0016 h | 2354 0016 h | 2355 0016 h | Go To |
18 h | 1 | RX_EVT_CLR_ALT1_ | RX_EVT_CLR_ALT1_ | 2353 0018 h | 2354 0018 h | 2355 0018 h | Go To |
1A h | 1 | RX_EVT_FRC_ALT1_ | RX_EVT_FRC_ALT1_ | 2353 001A h | 2354 001A h | 2355 001A h | Go To |
1C h | 1 | RX_BUF_PTR_LOAD | RX_BUF_PTR_LOAD | 2353 001C h | 2354 001C h | 2355 001C h | Go To |
1E h | 1 | RX_BUF_PTR_STS | RX_BUF_PTR_STS | 2353 001E h | 2354 001E h | 2355 001E h | Go To |
20 h | 1 | RX_FRAME_WD_CTRL | RX_FRAME_WD_CTRL | 2353 0020 h | 2354 0020 h | 2355 0020 h | Go To |
22 h | 1 | RESERVED | Reserved | 2353 0022 h | 2354 0022 h | 2355 0022 h | Go To |
24 h | 1 | RX_FRAME_WD_REF | RX_FRAME_WD_REF | 2353 0024 h | 2354 0024 h | 2355 0024 h | Go To |
28 h | 1 | RX_FRAME_WD_CNT | RX_FRAME_WD_CNT | 2353 0028 h | 2354 0028 h | 2355 0028 h | Go To |
2C h | 1 | RX_PING_WD_CTRL | RX_PING_WD_CTRL | 2353 002C h | 2354 002C h | 2355 002C h | Go To |
2E h | 1 | RX_PING_TAG | RX_PING_TAG | 2353 002E h | 2354 002E h | 2355 002E h | Go To |
30 h | 1 | RX_PING_WD_REF | RX_PING_WD_REF | 2353 0030 h | 2354 0030 h | 2355 0030 h | Go To |
34 h | 1 | RX_PING_WD_CNT | RX_PING_WD_CNT | 2353 0034 h | 2354 0034 h | 2355 0034 h | Go To |
38 h | 1 | RX_INT1_CTRL_ALT1_ | RX_INT1_CTRL_ALT1_ | 2353 0038 h | 2354 0038 h | 2355 0038 h | Go To |
3A h | 1 | RX_INT2_CTRL_ALT1_ | RX_INT2_CTRL_ALT1_ | 2353 003A h | 2354 003A h | 2355 003A h | Go To |
3C h | 1 | RX_LOCK_CTRL | RX_LOCK_CTRL | 2353 003C h | 2354 003C h | 2355 003C h | Go To |
3E h | 1 | RESERVED | Reserved | 2353 003E h | 2354 003E h | 2355 003E h | Go To |
40 h | 1 | RX_ECC_DATA | RX_ECC_DATA | 2353 0040 h | 2354 0040 h | 2355 0040 h | Go To |
44 h | 1 | RX_ECC_VAL | RX_ECC_VAL | 2353 0044 h | 2354 0044 h | 2355 0044 h | Go To |
46 h | 1 | RESERVED | Reserved | 2353 0046 h | 2354 0046 h | 2355 0046 h | Go To |
48 h | 1 | RX_ECC_SEC_DATA | RX_ECC_SEC_DATA | 2353 0048 h | 2354 0048 h | 2355 0048 h | Go To |
4C h | 1 | RX_ECC_LOG | RX_ECC_LOG | 2353 004C h | 2354 004C h | 2355 004C h | Go To |
4E h | 1 | RESERVED | Reserved | 2353 004E h | 2354 004E h | 2355 004E h | Go To |
50 h | 1 | RX_FRAME_TAG_CMP | RX_FRAME_TAG_CMP | 2353 0050 h | 2354 0050 h | 2355 0050 h | Go To |
52 h | 1 | RX_PING_TAG_CMP | RX_PING_TAG_CMP | 2353 0052 h | 2354 0052 h | 2355 0052 h | Go To |
54 h | 6 | RESERVED | Reserved | 2353 0054 h | 2354 0054 h | 2355 0054 h | Go To |
60 h | 1 | RX_DLYLINE_CTRL | RX_DLYLINE_CTRL | 2353 0060 h | 2354 0060 h | 2355 0060 h | Go To |
62 h | 7 | RESERVED | Reserved | 2353 0062 h | 2354 0062 h | 2355 0062 h | Go To |
70 h | 1 | RX_VIS_1 | RX_VIS_1 | 2353 0070 h | 2354 0070 h | 2355 0070 h | Go To |
74 h | 6 | RESERVED | Reserved | 2353 0074 h | 2354 0074 h | 2355 0074 h | Go To |
80 h | 16 | RX_BUF_BASE | RX_BUF_BASE | 2353 0080 h | 2354 0080 h | 2355 0080 h | Go To |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0000 h |
FSIRX1 | 2351 0000 h |
FSIRX2 | 2352 0000 h |
FSIRX3 | 2353 0000 h |
FSIRX4 | 2354 0000 h |
FSIRX5 | 2355 0000 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED_1 | INPUT_ISOLATE | SPI_PAIRING | INT_LOOPBACK | CORE_RST | ||||||||||
W | R | R/W | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | KEY | W | 0h | Write Key.[[br]]In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. |
7 - 4 | RESERVED_1 | R | 0h | Reserved |
3 | INPUT_ISOLATE | R/W | 0h | When set to 1, the FSI RX inputs [RXCLK, RXD0 and RXD1] will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of device pins and hence any potential glitch that could occur during the process of switching will not affect the RX module itself. |
2 | SPI_PAIRING | R/W | 0h | Clock Pairing for SPI-like Behavior Enable bit[[br]]This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module, acting as a SPI master, to clock data into the receiver and out of the transmitter like a standard SPI module. This configuration is valid when the Module is in SPI mode only [RX_OPER_CTRL.SPI_MODE = 1][[br]] [[br]]0h [R/W] = SPI clock pairing is not enabled.[[br]]1h [R/W] = SPI clock pairing is enabled. The RXCLK will be internally connected to the TXCLK of the corresponding FSI module.[[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
1 | INT_LOOPBACK | R/W | 0h | Internal Loopback Enable bit[[br]]This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit, a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the pins.[[br]] [[br]]0h [R/W] = Internal loopback is disabled. The FSI RX module will receive signals coming from the pins.[[br]]1h [R/W] = Internal loopback is enabled. The FSI RX module will receive signals from the directly from FSI TX module rather than the pins.[[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
0 | CORE_RST | R/W | 0h | Receiver Master Core Reset bit[[br]]This bit controls the receiver master core reset. In order to receive any frame, this bit must be cleared.[[br]]Note: For reset to take affect, the FSI RX module must be held in reset for at least 4 SYSCLK cycles.[[br]] [[br]]0h [R/W] = Receiver core is not in reset and can receive frames.[[br]]1h [R/W] = Receiver core is held in reset.[[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
(None,)
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Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0008 h |
FSIRX1 | 2351 0008 h |
FSIRX2 | 2352 0008 h |
FSIRX3 | 2353 0008 h |
FSIRX4 | 2354 0008 h |
FSIRX5 | 2355 0008 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_WD_RST_MODE | ECC_SEL | N_WORDS | SPI_MODE | DATA_WIDTH | ||||||||||
R | R/W | R/W | R/W | R/W | R/W | ||||||||||
0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 9 | RESERVED_1 | R | 0h | Reserved |
8 | PING_WD_RST_MODE | R/W | 0h | Ping Watchdog Timeout Mode Select bit[[br]]This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame.[[br]] [[br]]0h [R/W] = The ping watchdog counter will reset and restart only by ping frames.[[br]]1h [R/W] = The ping watchdog counter will reset and restart by any received frame. |
7 | ECC_SEL | R/W | 0h | ECC Data Width Select bit[[br]]This bit selects between whether the ECC computation is done on 16-bit or 32-bit words.[[br]] [[br]]0h [R/W] = 32-bit ECC is used.[[br]]1h [R/W] = 16-bit ECC is used. |
6 - 3 | N_WORDS | R/W | 0h | Number of Words to Receive[[br]]This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the number of words to be received. This value is only applicable when the frame type received is DATA_N_WORD.[[br]] [[br]]0h [R/W] = 1 data word frame [16-bit data].[[br]]1h [R/W] = 2 data word frame [32-bit data].[[br]]..[[br]]Fh [R/W] = 16 data word frame [256-bit data]. |
2 | SPI_MODE | R/W | 0h | SPI Mode Enable bit[[br]]This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive data that is sent using SPI signal format. Refer to the applicable section in the FSI TRM chapter for more information.[[br]] [[br]]0h [R/W] = FSI is in normal mode of operation.[[br]]1h [R/W] = FSI is operating in SPI compatibility mode. |
1 - 0 | DATA_WIDTH | R/W | 0h | Receive Data Width Select bit[[br]]These bits decide the number of data lines used for receiving data. [[br]] [[br]]0h [R/W] = Data will be received on one data line, RXD0.[[br]]1h [R/W] = Data will be received on two data lines, RXD0 and RXD1.[[br]]2h, 3h [R/W] = Reserved |
(None,)
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Instance Name | Base Address |
---|---|
FSIRX0 | 2350 000C h |
FSIRX1 | 2351 000C h |
FSIRX2 | 2352 000C h |
FSIRX3 | 2353 000C h |
FSIRX4 | 2354 000C h |
FSIRX5 | 2355 000C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | FRAME_TYPE | ||||||||||||||
R | R | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | FRAME_TYPE | R | 0h | Received Frame Type[[br]]This field indicates the type of frame that was successfully received last.[[br]] [[br]]0000b [R/W] = A ping frame was received[[br]]0100b [R/W] = A DATA_1_WORD frame was received [16-bit data].[[br]]0101b [R/W] = A DATA_2_WORD frame was received [32-bit data].[[br]]0110b [R/W] = A DATA_4_WORD frame was received [64-bit data]. [[br]]0111b [R/W] = A DATA_6_WORD frame was received [96-bit data].[[br]]0011b [R/W] = A DATA_N_WORD frame was received. The N_WORD field will determine the number of words [1 to 16] to be sent. The number of words received must equal the value programmed in RX_OPER_CTRL.N_WORDS. [[br]]1111b [R/W] = An error frame was received. This frame can be used during error conditions or any condition where the transmitter wants to signal the receiver for attention. However, the user software is at liberty to use this for any purpose.[[br]] [[br]]0001b, 0010b, and 1000b through 1110b are Reserved and should not be used. |
(None,)
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Instance Name | Base Address |
---|---|
FSIRX0 | 2350 000E h |
FSIRX1 | 2351 000E h |
FSIRX2 | 2352 000E h |
FSIRX3 | 2353 000E h |
FSIRX4 | 2354 000E h |
FSIRX5 | 2355 000E h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_DATA | RESERVED_1 | FRAME_TAG | ZERO | ||||||||||||
R | R | R | R | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | USER_DATA | R | 0h | Received User Data[[br]]This field contains the 8-bit user data field of the last successfully received frame. |
7 - 5 | RESERVED_1 | R | 0h | Reserved |
4 - 1 | FRAME_TAG | R | 0h | Received Frame Tag[[br]]This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag. |
0 | ZERO | R | 0h | Zero bit[[br]]This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register [bits 4:0], application software can directly index into an array of 32-bit data. |
(None,)
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Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0010 h |
FSIRX1 | 2351 0010 h |
FSIRX2 | 2352 0010 h |
FSIRX3 | 2353 0010 h |
FSIRX4 | 2354 0010 h |
FSIRX5 | 2355 0010 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | DMA_EVT_EN | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 1 | RESERVED_1 | R | 0h | Reserved |
0 | DMA_EVT_EN | R/W | 0h | DMA Event Enable bit[[br]]This bit will enable a DMA Event to be generated upon the completion of a frame reception.[[br]] [[br]]0h [R/W] = A DMA event will not be generated.[[br]]1h [R/W] = A DMA event will be generated upon the reception of a frame.[[br]] [[br]]Note: The DMA event will only be generated for data frames. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0014 h |
FSIRX1 | 2351 0014 h |
FSIRX2 | 2352 0014 h |
FSIRX3 | 2353 0014 h |
FSIRX4 | 2354 0014 h |
FSIRX5 | 2355 0014 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | ERROR_TAG_MATCH | DATA_TAG_MATCH | PING_TAG_MATCH | DATA_FRAME | FRAME_OVERRUN | PING_FRAME | ERR_FRAME | BUF_UNDERRUN | FRAME_DONE | BUF_OVERRUN | EOF_ERR | TYPE_ERR | CRC_ERR | FRAME_WD_TO | PING_WD_TO |
R | R | R | R | R | R | R | R | R | R | R | R | R | R | R | R |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 | ERROR_TAG_MATCH | R | 0h | Error Tag Match Flag[[br]]This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No tag-matched error frame received.[[br]]1h [R] = A tag-matched error frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
13 | DATA_TAG_MATCH | R | 0h | Data Tag Match Flag[[br]]This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No tag-matched data frame received.[[br]]1h [R] = A tag-matched data frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
12 | PING_TAG_MATCH | R | 0h | Ping Tag Match Flag[[br]]This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No tag-matched ping frame received.[[br]]1h [R] = A tag-matched ping frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
11 | DATA_FRAME | R | 0h | Data Frame Received Flag[[br]]This bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No data frame has been received.[[br]]1h [R] = A data frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
10 | FRAME_OVERRUN | R | 0h | Frame Overrun Flag[[br]]This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Frame overrun has not ocurred.[[br]]1h [R] = Frame overrun has ocurred.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
9 | PING_FRAME | R | 0h | Ping Frame Received Flag[[br]]This bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No ping frame has been received.[[br]]1h [R] = A ping frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
8 | ERR_FRAME | R | 0h | Error Frame Received Flag[[br]]This bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No error frame has been received.[[br]]1h [R] = An error frame has been received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
7 | BUF_UNDERRUN | R | 0h | Receive Buffer Underrun Flag[[br]]This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Receive Buffer Underrun has not ocurred.[[br]]1h [R] = Receive Buffer Underrun has ocurred.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
6 | FRAME_DONE | R | 0h | Frame Done Flag[[br]]This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = No frame has been successfully received.[[br]]1h [R] = A frame has been successfully received.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
5 | BUF_OVERRUN | R | 0h | Receive Buffer Overrun Flag[[br]]This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Receive buffer overrun has not ocurred.[[br]]1h [R] = Receive buffer overrun has ocurred.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
4 | EOF_ERR | R | 0h | End-of-Frame Error Flag[[br]]This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Invalid end-of-frame has not been received.[[br]]1h [R] = Invalid end-of-frame has been received[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
3 | TYPE_ERR | R | 0h | Frame Type Error Flag[[br]]This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Invalid frame type has not been received.[[br]]1h [R] = Invalid frame type has been received[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
2 | CRC_ERR | R | 0h | CRC Error Flag[[br]]This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = CRC error has not occured.[[br]]1h [R] = CRC error has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
1 | FRAME_WD_TO | R | 0h | Frame Watchdog Timeout Flag[[br]]This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Frame watchdog timeout has not occured.[[br]]1h [R] = Frame watchdog timeout has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
0 | PING_WD_TO | R | 0h | Ping Watchdog Timeout Flag[[br]]This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. [[br]] [[br]]0h [R] = Ping watchdog timeout has not occured.[[br]]1h [R] = Ping watchdog timeout has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the RX_EVT_CLR register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0016 h |
FSIRX1 | 2351 0016 h |
FSIRX2 | 2352 0016 h |
FSIRX3 | 2353 0016 h |
FSIRX4 | 2354 0016 h |
FSIRX5 | 2355 0016 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CALC_CRC | RX_CRC | ||||||||||||||
R | R | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | CALC_CRC | R | 0h | Harware Calculated CRC Value[[br]]This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. [[br]] [[br]]Note: The contents of this bitfield are invalid for ping and error frames. |
7 - 0 | RX_CRC | R | 0h | Received CRC Value[[br]]This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. [[br]] [[br]]Note: The contents of this bitfield are invalid for ping and error frames. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0018 h |
FSIRX1 | 2351 0018 h |
FSIRX2 | 2352 0018 h |
FSIRX3 | 2353 0018 h |
FSIRX4 | 2354 0018 h |
FSIRX5 | 2355 0018 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | ERROR_TAG_MATCH | DATA_TAG_MATCH | PING_TAG_MATCH | DATA_FRAME | FRAME_OVERRUN | PING_FRAME | ERR_FRAME | BUF_UNDERRUN | FRAME_DONE | BUF_OVERRUN | EOF_ERR | TYPE_ERR | CRC_ERR | FRAME_WD_TO | PING_WD_TO |
R | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 | ERROR_TAG_MATCH | W | 0h | Error Tag Match Glag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
13 | DATA_TAG_MATCH | W | 0h | Data Tag Match Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
12 | PING_TAG_MATCH | W | 0h | Ping Tag Match Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
11 | DATA_FRAME | W | 0h | Data Frame Received Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
10 | FRAME_OVERRUN | W | 0h | Frame Overrun Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
9 | PING_FRAME | W | 0h | Ping Frame Received Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
8 | ERR_FRAME | W | 0h | Error Frame Received Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
7 | BUF_UNDERRUN | W | 0h | Receive Buffer Underrun Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit will have no effect.[[br]]1h [R/W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
6 | FRAME_DONE | W | 0h | Frame Done Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
5 | BUF_OVERRUN | W | 0h | Receive Buffer Overrun Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
4 | EOF_ERR | W | 0h | End-of-Frame Error Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
3 | TYPE_ERR | W | 0h | Frame Type Error Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
2 | CRC_ERR | W | 0h | CRC Error Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
1 | FRAME_WD_TO | W | 0h | Frame Watchdog Timeout Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
0 | PING_WD_TO | W | 0h | Ping Watchdog Timeout Flag Clear bit[[br]]This bit clears the corresponding bit in the RX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 001A h |
FSIRX1 | 2351 001A h |
FSIRX2 | 2352 001A h |
FSIRX3 | 2353 001A h |
FSIRX4 | 2354 001A h |
FSIRX5 | 2355 001A h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | ERROR_TAG_MATCH | DATA_TAG_MATCH | PING_TAG_MATCH | DATA_FRAME | FRAME_OVERRUN | PING_FRAME | ERR_FRAME | BUF_UNDERRUN | FRAME_DONE | BUF_OVERRUN | EOF_ERR | TYPE_ERR | CRC_ERR | FRAME_WD_TO | PING_WD_TO |
R | W | W | W | W | W | W | W | W | W | W | W | W | W | W | W |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 | ERROR_TAG_MATCH | W | 0h | Error Tag Match Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
13 | DATA_TAG_MATCH | W | 0h | Data Tag Match Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
12 | PING_TAG_MATCH | W | 0h | Ping Tag Match Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
11 | DATA_FRAME | W | 0h | Data Frame Received Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
10 | FRAME_OVERRUN | W | 0h | Frame Overrun Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
9 | PING_FRAME | W | 0h | Ping Frame Received Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
8 | ERR_FRAME | W | 0h | Error Frame Received Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
7 | BUF_UNDERRUN | W | 0h | Receive Buffer Underrun Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
6 | FRAME_DONE | W | 0h | Frame Done Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
5 | BUF_OVERRUN | W | 0h | Receive Buffer Overrun Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
4 | EOF_ERR | W | 0h | End-of-Frame Error Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
3 | TYPE_ERR | W | 0h | Frame Type Error Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
2 | CRC_ERR | W | 0h | CRC Error Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
1 | FRAME_WD_TO | W | 0h | Frame Watchdog Timeout Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
0 | PING_WD_TO | W | 0h | Ping Watchdog Timeout Flag Force bit[[br]]This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding bit in the RX_EVT_STS Register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 001C h |
FSIRX1 | 2351 001C h |
FSIRX2 | 2352 001C h |
FSIRX3 | 2353 001C h |
FSIRX4 | 2354 001C h |
FSIRX5 | 2355 001C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | BUF_PTR_LOAD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | BUF_PTR_LOAD | R/W | 0h | Buffer Pointer Load.[[br]]This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. [[br]] [[br]]NOTE: The value of the CURR_BUF_PTR in the RX_BUF_PTR_STS will not get reflected immediately. This will take effect only when there is a valid receive operation with incoming clocks after [3 RXCLK + 3 SYCLK] cycles. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 001E h |
FSIRX1 | 2351 001E h |
FSIRX2 | 2352 001E h |
FSIRX3 | 2353 001E h |
FSIRX4 | 2354 001E h |
FSIRX5 | 2355 001E h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | CURR_WORD_CNT | RESERVED_1 | CURR_BUF_PTR | ||||||||||||
R | R | R | R | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 13 | RESERVED_2 | R | 0h | Reserved |
12 - 8 | CURR_WORD_CNT | R | 0h | Words Available in the Receive Buffer[[br]]This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer.[[br]] [[br]]Note: This value will not be valid if there has been a buffer overrun or underrun condition. |
7 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | CURR_BUF_PTR | R | 0h | Current Buffer Pointer Index[[br]]This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0020 h |
FSIRX1 | 2351 0020 h |
FSIRX2 | 2352 0020 h |
FSIRX3 | 2353 0020 h |
FSIRX4 | 2354 0020 h |
FSIRX5 | 2355 0020 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | FRAME_WD_EN | FRAME_WD_CNT_RST | |||||||||||||
R | R/W | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 2 | RESERVED_1 | R | 0h | Reserved |
1 | FRAME_WD_EN | R/W | 0h | Frame Watchdog Counter Enable bit[[br]]This bit will enable or disable the frame watchdog counter. The counter [RX_FRAME_WD_CNT] will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value [RX_FRAME_WD_REF] is reached, it will generate a frame watchdog timeout event [RX_EVT_STS.FRAME_WD_TO] and the counter value will reset to 0 and continue counting on the next valid start-of-frame.[[br]] [[br]]0h [R/W] = The frame watchdog counter is disabled and not running.[[br]]1h [R/W] = The frame watchdog counter logic is enabled and running. |
0 | FRAME_WD_CNT_RST | R/W | 0h | Frame Watchdog Counter Reset bit[[br]]This bit will reset the frame watchdog counter to 0. This bit will always be read as 0.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit has no effect.[[br]]1h [W] = The frame watchdog counter will be reset to 0. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0024 h |
FSIRX1 | 2351 0024 h |
FSIRX2 | 2352 0024 h |
FSIRX3 | 2353 0024 h |
FSIRX4 | 2354 0024 h |
FSIRX5 | 2355 0024 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FRAME_WD_REF | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME_WD_REF | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | FRAME_WD_REF | R/W | 0h | Frame Watchdog Counter Reference Value[[br]]This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0028 h |
FSIRX1 | 2351 0028 h |
FSIRX2 | 2352 0028 h |
FSIRX3 | 2353 0028 h |
FSIRX4 | 2354 0028 h |
FSIRX5 | 2355 0028 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FRAME_WD_CNT | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME_WD_CNT | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | FRAME_WD_CNT | R | 0h | Frame Watchdog Counter Value[[br]]This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST, a match with FRAME_WD_REF, or the reception of a successful data frame. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 002C h |
FSIRX1 | 2351 002C h |
FSIRX2 | 2352 002C h |
FSIRX3 | 2353 002C h |
FSIRX4 | 2354 002C h |
FSIRX5 | 2355 002C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_WD_EN | PING_WD_RST | |||||||||||||
R | R/W | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 2 | RESERVED_1 | R | 0h | Reserved |
1 | PING_WD_EN | R/W | 0h | Ping Watchdog Counter Enable bit[[br]]This bit will enable or disable the ping watchdog counter. The counter [RX_PING_WD_CNT] will begin counting from 0 when it is enabled. When the reference value [RX_PING_WD_REF] is reached, it will generate a ping watchdog timeout event [RX_EVT_STS.PING_WD_TO] and the counter value will reset to 0, and resume counting[[br]] [[br]]0h [R/W] = The ping watchdog counter is disabled and not running.[[br]]1h [R/W] = The ping watchdog counter logic is enabled and running. |
0 | PING_WD_RST | R/W | 0h | Ping Watchdog Counter Reset bit[[br]]This bit will reset the ping watchdog counter to 0. This bit will always be read as 0.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit has no effect.[[br]]1h [W] = The ping watchdog counter will be reset to 0. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 002E h |
FSIRX1 | 2351 002E h |
FSIRX2 | 2352 002E h |
FSIRX3 | 2353 002E h |
FSIRX4 | 2354 002E h |
FSIRX5 | 2355 002E h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_TAG | ZERO | |||||||||||||
R | R | R | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 5 | RESERVED_1 | R | 0h | Reserved |
4 - 1 | PING_TAG | R | 0h | Received Ping Frame Tag[[br]]This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag. |
0 | ZERO | R | 0h | Zero bit[[br]]This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register [bits 4:0], application software can directly index into an array of 32-bit data. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0030 h |
FSIRX1 | 2351 0030 h |
FSIRX2 | 2352 0030 h |
FSIRX3 | 2353 0030 h |
FSIRX4 | 2354 0030 h |
FSIRX5 | 2355 0030 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PING_WD_REF | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PING_WD_REF | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | PING_WD_REF | R/W | 0h | Ping Watchdog Counter Reference Value[[br]]This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0034 h |
FSIRX1 | 2351 0034 h |
FSIRX2 | 2352 0034 h |
FSIRX3 | 2353 0034 h |
FSIRX4 | 2354 0034 h |
FSIRX5 | 2355 0034 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PING_WD_CNT | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PING_WD_CNT | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | PING_WD_CNT | R | 0h | Ping Watchdog Counter Value[[br]]This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST, a match with PING_WD_REF, or the reception of a ping frame. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0038 h |
FSIRX1 | 2351 0038 h |
FSIRX2 | 2352 0038 h |
FSIRX3 | 2353 0038 h |
FSIRX4 | 2354 0038 h |
FSIRX5 | 2355 0038 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | INT1_EN_ERROR_TAG_MATCH | INT1_EN_DATA_TAG_MATCH | INT1_EN_PING_TAG_MATCH | INT1_EN_DATA_FRAME | INT1_EN_FRAME_OVERRUN | INT1_EN_PING_FRAME | INT1_EN_ERR_FRAME | INT1_EN_UNDERRUN | INT1_EN_FRAME_DONE | INT1_EN_OVERRUN | INT1_EN_EOF_ERR | INT1_EN_TYPE_ERR | INT1_EN_CRC_ERR | INT1_EN_FRAME_WD_TO | INT1_EN_PING_WD_TO |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 | INT1_EN_ERROR_TAG_MATCH | R/W | 0h | Enable Error Frame Received with Tag Match Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = An error frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
13 | INT1_EN_DATA_TAG_MATCH | R/W | 0h | Enable Data Frame Received with Tag Match Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A data frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
12 | INT1_EN_PING_TAG_MATCH | R/W | 0h | Enable Ping Frame Received with Tag Match Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A ping frame received with matching tag will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
11 | INT1_EN_DATA_FRAME | R/W | 0h | Enable Data Frame Received Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A data frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
10 | INT1_EN_FRAME_OVERRUN | R/W | 0h | Enable Frame Overrun Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A frame overrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
9 | INT1_EN_PING_FRAME | R/W | 0h | Enable Ping Frame Received Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A ping frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
8 | INT1_EN_ERR_FRAME | R/W | 0h | Enable ERROR Frame Received Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A error frame received event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
7 | INT1_EN_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A buffer underrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
6 | INT1_EN_FRAME_DONE | R/W | 0h | Enable Frame Done Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A frame done event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
5 | INT1_EN_OVERRUN | R/W | 0h | Enable Receive Buffer Overrun Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A receive buffer overrun event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
4 | INT1_EN_EOF_ERR | R/W | 0h | Enable End-of-Frame Error Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = An end-of-frame error event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
3 | INT1_EN_TYPE_ERR | R/W | 0h | Enable Frame Type Error Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A frame type error event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
2 | INT1_EN_CRC_ERR | R/W | 0h | Enable CRC Error Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A CRC error will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
1 | INT1_EN_FRAME_WD_TO | R/W | 0h | Enable Frame Watchdog Timeout Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A frame watchdog timeout event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
0 | INT1_EN_PING_WD_TO | R/W | 0h | Enable Ping Watchdog Timeout Interrupt to INT1 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT1] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT1.[[br]]1h [R/W] = A ping watchdog timeout event will trigger an interrupt on RX_INT1. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 003A h |
FSIRX1 | 2351 003A h |
FSIRX2 | 2352 003A h |
FSIRX3 | 2353 003A h |
FSIRX4 | 2354 003A h |
FSIRX5 | 2355 003A h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | INT2_EN_ERROR_TAG_MATCH | INT2_EN_DATA_TAG_MATCH | INT2_EN_PING_TAG_MATCH | INT2_EN_DATA_FRAME | INT2_EN_FRAME_OVERRUN | INT2_EN_PING_FRAME | INT2_EN_ERR_FRAME | INT2_EN_UNDERRUN | INT2_EN_FRAME_DONE | INT2_EN_OVERRUN | INT2_EN_EOF_ERR | INT2_EN_TYPE_ERR | INT2_EN_CRC_ERR | INT2_EN_FRAME_WD_TO | INT2_EN_PING_WD_TO |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 | INT2_EN_ERROR_TAG_MATCH | R/W | 0h | Enable Error Frame Received with Tag Match Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = An error frame received with matching tag will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
13 | INT2_EN_DATA_TAG_MATCH | R/W | 0h | Enable Data Frame Received with Tag Match Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A data frame received with matching tag will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
12 | INT2_EN_PING_TAG_MATCH | R/W | 0h | Enable Ping Frame Received with Tag Match Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A ping frame received with matching tag will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
11 | INT2_EN_DATA_FRAME | R/W | 0h | Enable Data Frame Received Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A data frame received event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
10 | INT2_EN_FRAME_OVERRUN | R/W | 0h | Enable Frame Overrun Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A frame overrun event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
9 | INT2_EN_PING_FRAME | R/W | 0h | Enable Ping Frame Received Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A ping frame received event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
8 | INT2_EN_ERR_FRAME | R/W | 0h | Enable Error Frame Received Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A error frame received event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
7 | INT2_EN_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A buffer underrun event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
6 | INT2_EN_FRAME_DONE | R/W | 0h | Enable Frame Done Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A frame done event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
5 | INT2_EN_OVERRUN | R/W | 0h | Enable Buffer Overrun Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A buffer overrun event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
4 | INT2_EN_EOF_ERR | R/W | 0h | Enable End-of-Frame Error Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = An end-of-frame error event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
3 | INT2_EN_TYPE_ERR | R/W | 0h | Enable Frame Type Error Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A frame type error event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
2 | INT2_EN_CRC_ERR | R/W | 0h | Enable CRC Error Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A CRC error will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
1 | INT2_EN_FRAME_WD_TO | R/W | 0h | Enable Frame Watchdog Timeout Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A frame watchdog timeout event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
0 | INT2_EN_PING_WD_TO | R/W | 0h | Enable Ping Watchdog Timeout Interrupt to INT2 bit[[br]]This is an enable register which decides whether an interrupt [RX_INT2] will be generated on the enabled event.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on RX_INT2.[[br]]1h [R/W] = A ping watchdog timeout event will trigger an interrupt on RX_INT2. The event itself will be latched in the corresponding bit in the RX_EVT_STS Register |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 003C h |
FSIRX1 | 2351 003C h |
FSIRX2 | 2352 003C h |
FSIRX3 | 2353 003C h |
FSIRX4 | 2354 003C h |
FSIRX5 | 2355 003C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED_1 | LOCK | |||||||||||||
W | R | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | KEY | W | 0h | Write Key.[[br]]In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. |
7 - 1 | RESERVED_1 | R | 0h | Reserved |
0 | LOCK | R/W | 0h | Control Register Lock Enable bit[[br]]This bit locks the contents of all the receive control registers that support a lock protection. Once locked, further writes will not take effect until SYSRS unlocks the register. Once set, further writes even to this bit will be ignored.[[br]] [[br]]0h [R/W] = Receive control registers can be modified and are not locked.[[br]]1h [R/W] = Receive control registers are locked and cannot be modified until this bit is cleared by SYSRS. Any further writes to this bit are ignored.[[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0040 h |
FSIRX1 | 2351 0040 h |
FSIRX2 | 2352 0040 h |
FSIRX3 | 2353 0040 h |
FSIRX4 | 2354 0040 h |
FSIRX5 | 2355 0040 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_HIGH | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_LOW | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 16 | DATA_HIGH | R/W | 0h | Upper 16 bits of ECC Data[[br]]Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a 32-bit write when needing to compute ECC for 32-bits for the full TX_ECC_DATA register. |
15 - 0 | DATA_LOW | R/W | 0h | Lower 16 bits of ECC Data[[br]]Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when needing to compute ECC for 16-bits. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0044 h |
FSIRX1 | 2351 0044 h |
FSIRX2 | 2352 0044 h |
FSIRX3 | 2353 0044 h |
FSIRX4 | 2354 0044 h |
FSIRX5 | 2355 0044 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | ECC_VAL | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 7 | RESERVED_1 | R | 0h | Reserved |
6 - 0 | ECC_VAL | R/W | 0h | ECC Value for SEC-DED check[[br]]This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0048 h |
FSIRX1 | 2351 0048 h |
FSIRX2 | 2352 0048 h |
FSIRX3 | 2353 0048 h |
FSIRX4 | 2354 0048 h |
FSIRX5 | 2355 0048 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SEC_DATA | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEC_DATA | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | SEC_DATA | R | 0h | ECC Single Error Corrected Data[[br]]The ECC corrected data will be available in this register. This value is valid only when there are no bit errors, or a single bit error was detected. Otherwise, the contents of this register are invalid and should not be used. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 004C h |
FSIRX1 | 2351 004C h |
FSIRX2 | 2352 004C h |
FSIRX3 | 2353 004C h |
FSIRX4 | 2354 004C h |
FSIRX5 | 2355 004C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | MBE | SBE | |||||||||||||
R | R | R | |||||||||||||
0 | 1 | 1 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 2 | RESERVED_1 | R | 0h | Reserved |
1 | MBE | R | 1h | Multiple Bit Errors Detected[[br]]This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set, the data present in RX_ECC_SEC_DATA is invalid and should not be used.[[br]] [[br]]0h [R] Multiple Bit Errors were not detected. Check the SBE bit for single bit errors.[[br]]1h [R] Multiple Bit Errors were detected. The data is not able to be corrected. The value present in RX_ECC_SEC_DATA is invalid and should not be used. |
0 | SBE | R | 1h | Single Bit Error Detected[[br]]This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0.[[br]] [[br]]0h [R] No bit errors were detected. The value in RX_ECC_SEC_DATA is correct. [[br]]1h [R] A single bit error was detected and corrected. The corrected data is present in RX_ECC_SEC_DATA. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0050 h |
FSIRX1 | 2351 0050 h |
FSIRX2 | 2352 0050 h |
FSIRX3 | 2353 0050 h |
FSIRX4 | 2354 0050 h |
FSIRX5 | 2355 0050 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | BROADCAST_EN | CMP_EN | TAG_MASK | TAG_REF | |||||||||||
R | R/W | R/W | R/W | R/W | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 10 | RESERVED_1 | R | 0h | Reserved |
9 | BROADCAST_EN | R/W | 0h | Broadcast Enable bit[[br]]This will enable the reception of a ping frame broadcast. When this bit is set, bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1, a ping tag match event will be triggered regardless of the. A match caused by the comparison of TAG_MASK and TAG_REF will still be considered a match and the frame tag match event will be triggered as normal[[br]] [[br]]This bit only takes effect only if CMP_EN is set to 1.[[br]] [[br]]0h [R/W] Broadcast frame match disabled.[[br]]1h [R/W] Broadcast frame match enabled. |
8 | CMP_EN | R/W | 0h | Frame Tag Compare Enable bit[[br]]Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK, TAG_REF, and the incoming frame tag will trigger the apprpriate frame tag match event.[[br]] [[br]]0h [R/W] Frame tag comparison is disabled.[[br]]1h [R/W] Frame tag comparison is enabled. |
7 - 4 | TAG_MASK | R/W | 0h | Frame Tag Mask[[br]]Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison.[[br]] [[br]]This mask value is used only for non-ping frames. |
3 - 0 | TAG_REF | R/W | 0h | Frame Tag Reference[[br]]The reference tag to check against when comparing the TAG_MASK and the incoming frame tag.[[br]] [[br]]This reference value is used only for non-ping frames. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0052 h |
FSIRX1 | 2351 0052 h |
FSIRX2 | 2352 0052 h |
FSIRX3 | 2353 0052 h |
FSIRX4 | 2354 0052 h |
FSIRX5 | 2355 0052 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | BROADCAST_EN | CMP_EN | TAG_MASK | TAG_REF | |||||||||||
R | R/W | R/W | R/W | R/W | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 10 | RESERVED_1 | R | 0h | Reserved |
9 | BROADCAST_EN | R/W | 0h | Broadcast Enable bit[[br]]This will enable the reception of a ping frame broadcast. When this bit is set, bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1, a ping tag match event will be triggered regardless of the. A match caused by the comparison of TAG_MASK and TAG_REF will still be considered a match and the ping tag match event will be triggered as normal[[br]] [[br]]This bit only takes effect only if CMP_EN is set to 1.[[br]] [[br]]0h [R/W] Broadcast frame match disabled.[[br]]1h [R/W] Broadcast frame match enabled. |
8 | CMP_EN | R/W | 0h | Ping Tag Compare Enable bit[[br]]Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK, TAG_REF, and the incoming ping tag will trigger a ping frame tag match event.[[br]] [[br]]0h [R/W] Ping tag comparison is disabled.[[br]]1h [R/W] Ping tag comparison is enabled. |
7 - 4 | TAG_MASK | R/W | 0h | Ping Tag Mask[[br]]Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison.[[br]] [[br]]This mask value is used only for ping frames. |
3 - 0 | TAG_REF | R/W | 0h | Ping Tag Reference[[br]]The reference tag to check against when comparing the TAG_MASK and the incoming ping tag.[[br]] [[br]]This reference value is used only for ping frames. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0060 h |
FSIRX1 | 2351 0060 h |
FSIRX2 | 2352 0060 h |
FSIRX3 | 2353 0060 h |
FSIRX4 | 2354 0060 h |
FSIRX5 | 2355 0060 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | RXD1_DLY | RXD0_DLY | RXCLK_DLY | ||||||||||||
R | R/W | R/W | R/W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | RESERVED_1 | R | 0h | Reserved |
14 - 10 | RXD1_DLY | R/W | 0h | Delay Line Tap Select for RXD1[[br]]This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core.[[br]] [[br]]0h [R/W] Zero delay elements are included in the RXD1 path. RXD1 is taken directly from the pin.[[br]]1h [R/W] One delay element is included in the RXD1 path.[[br]]2h [R/W] Two delay elements are included in the RXD1 path.[[br]]...[[br]]1Fh [R/W] 31 delay elements are included in the RXD1 path, the maximum. |
9 - 5 | RXD0_DLY | R/W | 0h | Delay Line Tap Select for RXD0[[br]]This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core.[[br]] [[br]]0h [R/W] Zero delay elements are included in the RXD0 path. RXD0 is taken directly from the pin.[[br]]1h [R/W] One delay element is included in the RXD0 path.[[br]]2h [R/W] Two delay elements are included in the RXD0 path.[[br]]...[[br]]1Fh [R/W] 31 delay elements are included in the RXD0 path, the maximum. |
4 - 0 | RXCLK_DLY | R/W | 0h | Delay Line Tap Select for RXCLK[[br]]This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core.[[br]] [[br]]0h [R/W] Zero delay elements are included in the RXCLK path. RXCLK is taken directly from the pin.[[br]]1h [R/W] One delay element is included in the RXCLK path.[[br]]2h [R/W] Two delay elements are included in the RXCLK path.[[br]]...[[br]]1Fh [R/W] 31 delay elements are included in the RXCLK path, the maximum. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0070 h |
FSIRX1 | 2351 0070 h |
FSIRX2 | 2352 0070 h |
FSIRX3 | 2353 0070 h |
FSIRX4 | 2354 0070 h |
FSIRX5 | 2355 0070 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_2 | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | RX_CORE_STS | RESERVED_1 | |||||||||||||
R | R | R | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 4 | RESERVED_2 | R | 0h | Reserved |
3 | RX_CORE_STS | R | 0h | Receiver Core Status bit[[br]]This bit indicates the status of the receiver core. If this bit is set, the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has detected and end of frame error or a frame type error. This bit can also be set if the receiver becomes corrupted due to noise on the signal lines. If the receiver has experienced a ping watchdog or frame watchdog timeout, this bit should be read to determine if the cause was due to a corrupt transaction, thus putting the receiver core into an unrecoverable state.[[br]] [[br]]Only a soft reset will reset the recevier core and thus reset this bit.[[br]] [[br]]0h [R] The receiver core is operating normally.[[br]]1h [R] The receiver core has entered into an error state and should be reset. |
2 - 0 | RESERVED_1 | R | 0h | Reserved |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSIRX0 | 2350 0080 h |
FSIRX1 | 2351 0080 h |
FSIRX2 | 2352 0080 h |
FSIRX3 | 2353 0080 h |
FSIRX4 | 2354 0080 h |
FSIRX5 | 2355 0080 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASE_ADDRESS | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | BASE_ADDRESS | R | 0h | Receive Data Buffer Base Address[[br]]This is the base address of the 16-word data buffer used by the receiver. |
Access Type | Code | Description |
---|---|---|
W | W | Write |
R | R | Read |
R/W | R/W | Read / Write |