SPRUIM2H May   2020  – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Glossary
    3.     Related Documentation From Texas Instruments
    4.     6
    5.     Support Resources
    6.     Trademarks
    7.     Export Control Notice
  3. 1 Introduction
    1. 1.1 Device Overview
    2.     12
    3. 1.2 Functional Block Diagram
      1. 1.2.1 Module Allocation and Instances within Device Domains
    4. 1.3 Device MAIN Domain
      1. 1.3.1  Arm Cortex-A53 Subsystem (A53SS)
      2.      Arm Cortex-R5F Processor (R5FSS)
      3. 1.3.2  Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      4. 1.3.3  DDR 16-bit Subsystem (DDR16)
      5. 1.3.4  Region-based Address Translation Module (RAT)
      6. 1.3.5  Data Movement Subsystem (DMSS)
      7. 1.3.6  Mailbox (MAILBOX)
      8. 1.3.7  Spinlock (SPINLOCK)
      9. 1.3.8  Analog-to-Digital Converter (ADC)
      10. 1.3.9  General Purpose Input/Output Interface (GPIO)
      11. 1.3.10 Inter-Integrated Circuit Interface (I2C)
      12. 1.3.11 Serial Peripheral Interface (SPI)
      13. 1.3.12 Universal Asynchronous Receiver/Transmitter (UART)
      14. 1.3.13 3-port Gigabit Ethernet Switch (CPSW3G)
      15. 1.3.14 Peripheral Component Interconnect Express Subsystem (PCIE)
      16. 1.3.15 Serializer/Deserializer (SERDES)
      17. 1.3.16 Universal Serial Bus 3.1 Subsystem (USBSS)
      18. 1.3.17 General Purpose Memory Controller (GPMC)
      19. 1.3.18 Error Location Module (ELM)
      20. 1.3.19 Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
      21. 1.3.20 Multi-Media Card/Secure Digital Interface (MMCSD)
      22. 1.3.21 Enhanced Capture Module (ECAP)
      23. 1.3.22 Enhanced Pulse-Width Modulation Module (EPWM)
      24. 1.3.23 Enhanced Quadrature Encoder Pulse Module (EQEP)
      25. 1.3.24 Controller Area Network (MCAN)
      26. 1.3.25 Fast Serial Interface Receiver (FSI_RX)
      27. 1.3.26 Fast Serial Interface Transmitter (FSI_TX)
      28. 1.3.27 Timers
      29. 1.3.28 Internal Diagnostics Modules
    5. 1.4 Device MCU Domain
      1. 1.4.1 MCU Arm Cortex M4F Subsystem (MCU_M4FSS)
      2. 1.4.2 MCU General Purpose Input/Output Interface (MCU_GPIO)
      3. 1.4.3 MCU Inter-Integrated Circuit Interface (MCU_I2C)
      4. 1.4.4 MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
      5. 1.4.5 MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
      6. 1.4.6 MCU Timers
      7. 1.4.7 MCU Internal Diagnostics Modules
    6. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 Processors View Memory Map
    4. 2.4 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1  Terminology
    2. 3.2  System Interconnect Overview
    3. 3.3  Initiator/Target Connectivity
    4. 3.4  Interrupt Condition for Interconnect
    5. 3.5  IO Coherency Support
    6. 3.6  Quality of Service (QoS) Block
      1.      66
    7. 3.7  Route ID
      1.      68
    8. 3.8  ISC and Firewall
      1. 3.8.1 Initiator-Side Security Controls (ISC)
        1.       71
        2. 3.8.1.1 ISC MMR
      2. 3.8.2 Transaction Attributes for BCDMA and PktDMA Transactions
      3. 3.8.3 Firewall Block
        1.       75
        2. 3.8.3.1 Region Based Firewall Programming
    9. 3.9  System Interconnect Integration
      1. 3.9.1 Interconnect Integration in MAIN/MCU Domain
    10. 3.10 System Interconnect Registers
      1. 3.10.1 CBASS Registers
        1. 3.10.1.1    ERR_PID Registers
        2. 3.10.1.2    ERR_DESTINATION_ID Registers
        3. 3.10.1.3    ERR_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.1.4    ERR_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.1.5    ERR_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.1.6    ERR_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.1.7    ERR_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.1.8    ERR_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.1.9    ERR_ERR_INTR_RAW_STAT Registers
        10. 3.10.1.10   ERR_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.1.11   ERR_ERR_INTR_ENABLE_SET Registers
        12. 3.10.1.12   ERR_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.1.13   ERR_EOI Registers
        14. 3.10.1.14   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_CONTROL Registers
        15. 3.10.1.15   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.1.16   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.1.17   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.1.18   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.1.19   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.1.20   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.1.21   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.1.22   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_CONTROL Registers
        23. 3.10.1.23   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.1.24   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.1.25   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.1.26   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.1.27   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.1.28   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.1.29   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.1.30   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_CONTROL Registers
        31. 3.10.1.31   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.1.32   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.1.33   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.1.34   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.1.35   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.1.36   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.1.37   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.1.38   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_CONTROL Registers
        39. 3.10.1.39   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.1.40   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.1.41   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.1.42   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.1.43   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.1.44   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.1.45   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.1.46   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_CONTROL Registers
        47. 3.10.1.47   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.1.48   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.1.49   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.1.50   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.1.51   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.1.52   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.1.53   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.1.54   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_CONTROL Registers
        55. 3.10.1.55   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.1.56   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.1.57   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.1.58   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.1.59   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.1.60   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.1.61   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.1.62   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_CONTROL Registers
        63. 3.10.1.63   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.1.64   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.1.65   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.1.66   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.1.67   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.1.68   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.1.69   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.1.70   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_CONTROL Registers
        71. 3.10.1.71   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.1.72   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.1.73   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.1.74   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.1.75   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.1.76   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.1.77   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.1.78   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_CONTROL Registers
        79. 3.10.1.79   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.1.80   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.1.81   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.1.82   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.1.83   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.1.84   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.1.85   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.1.86   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_CONTROL Registers
        87. 3.10.1.87   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.1.88   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.1.89   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.1.90   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.1.91   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.1.92   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.1.93   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.1.94   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_CONTROL Registers
        95. 3.10.1.95   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.1.96   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.1.97   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.1.98   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.1.99   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.1.100  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.1.101  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.1.102  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_CONTROL Registers
        103. 3.10.1.103  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.1.104  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.1.105  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.1.106  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.1.107  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.1.108  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.1.109  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.1.110  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_CONTROL Registers
        111. 3.10.1.111  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.1.112  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.1.113  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.1.114  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.1.115  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.1.116  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.1.117  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.1.118  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_CONTROL Registers
        119. 3.10.1.119  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.1.120  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.1.121  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.1.122  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.1.123  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.1.124  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.1.125  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.1.126  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_CONTROL Registers
        127. 3.10.1.127  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.1.128  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.1.129  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.1.130  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.1.131  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.1.132  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.1.133  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.1.134  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_CONTROL Registers
        135. 3.10.1.135  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.1.136  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.1.137  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.1.138  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.1.139  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.1.140  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.1.141  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.1.142  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_CONTROL Registers
        143. 3.10.1.143  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_0 Registers
        144. 3.10.1.144  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_1 Registers
        145. 3.10.1.145  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_2 Registers
        146. 3.10.1.146  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_L Registers
        147. 3.10.1.147  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_H Registers
        148. 3.10.1.148  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_L Registers
        149. 3.10.1.149  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_H Registers
        150. 3.10.1.150  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_CONTROL Registers
        151. 3.10.1.151  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_0 Registers
        152. 3.10.1.152  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_1 Registers
        153. 3.10.1.153  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_2 Registers
        154. 3.10.1.154  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_L Registers
        155. 3.10.1.155  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_H Registers
        156. 3.10.1.156  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_L Registers
        157. 3.10.1.157  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_H Registers
        158. 3.10.1.158  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_CONTROL Registers
        159. 3.10.1.159  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_0 Registers
        160. 3.10.1.160  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_1 Registers
        161. 3.10.1.161  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_2 Registers
        162. 3.10.1.162  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_L Registers
        163. 3.10.1.163  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_H Registers
        164. 3.10.1.164  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_L Registers
        165. 3.10.1.165  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_H Registers
        166. 3.10.1.166  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_CONTROL Registers
        167. 3.10.1.167  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_0 Registers
        168. 3.10.1.168  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_1 Registers
        169. 3.10.1.169  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_2 Registers
        170. 3.10.1.170  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_L Registers
        171. 3.10.1.171  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_H Registers
        172. 3.10.1.172  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_L Registers
        173. 3.10.1.173  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_H Registers
        174. 3.10.1.174  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_CONTROL Registers
        175. 3.10.1.175  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_0 Registers
        176. 3.10.1.176  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_1 Registers
        177. 3.10.1.177  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_2 Registers
        178. 3.10.1.178  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_L Registers
        179. 3.10.1.179  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_H Registers
        180. 3.10.1.180  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_L Registers
        181. 3.10.1.181  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_H Registers
        182. 3.10.1.182  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_CONTROL Registers
        183. 3.10.1.183  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_0 Registers
        184. 3.10.1.184  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_1 Registers
        185. 3.10.1.185  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_2 Registers
        186. 3.10.1.186  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_L Registers
        187. 3.10.1.187  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_H Registers
        188. 3.10.1.188  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_L Registers
        189. 3.10.1.189  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_H Registers
        190. 3.10.1.190  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_CONTROL Registers
        191. 3.10.1.191  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_0 Registers
        192. 3.10.1.192  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_1 Registers
        193. 3.10.1.193  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_2 Registers
        194. 3.10.1.194  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_L Registers
        195. 3.10.1.195  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_H Registers
        196. 3.10.1.196  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_L Registers
        197. 3.10.1.197  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_H Registers
        198. 3.10.1.198  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_CONTROL Registers
        199. 3.10.1.199  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_0 Registers
        200. 3.10.1.200  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_1 Registers
        201. 3.10.1.201  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_2 Registers
        202. 3.10.1.202  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_L Registers
        203. 3.10.1.203  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_H Registers
        204. 3.10.1.204  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_L Registers
        205. 3.10.1.205  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_H Registers
        206. 3.10.1.206  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_CONTROL Registers
        207. 3.10.1.207  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_0 Registers
        208. 3.10.1.208  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_1 Registers
        209. 3.10.1.209  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_2 Registers
        210. 3.10.1.210  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_L Registers
        211. 3.10.1.211  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_H Registers
        212. 3.10.1.212  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_L Registers
        213. 3.10.1.213  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_H Registers
        214. 3.10.1.214  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_CONTROL Registers
        215. 3.10.1.215  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_0 Registers
        216. 3.10.1.216  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_1 Registers
        217. 3.10.1.217  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_2 Registers
        218. 3.10.1.218  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_L Registers
        219. 3.10.1.219  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_H Registers
        220. 3.10.1.220  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_L Registers
        221. 3.10.1.221  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_H Registers
        222. 3.10.1.222  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_CONTROL Registers
        223. 3.10.1.223  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_0 Registers
        224. 3.10.1.224  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_1 Registers
        225. 3.10.1.225  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_2 Registers
        226. 3.10.1.226  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_L Registers
        227. 3.10.1.227  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_H Registers
        228. 3.10.1.228  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_L Registers
        229. 3.10.1.229  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_H Registers
        230. 3.10.1.230  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_CONTROL Registers
        231. 3.10.1.231  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_0 Registers
        232. 3.10.1.232  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_1 Registers
        233. 3.10.1.233  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_2 Registers
        234. 3.10.1.234  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_L Registers
        235. 3.10.1.235  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_H Registers
        236. 3.10.1.236  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_L Registers
        237. 3.10.1.237  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_H Registers
        238. 3.10.1.238  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_CONTROL Registers
        239. 3.10.1.239  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_0 Registers
        240. 3.10.1.240  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_1 Registers
        241. 3.10.1.241  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_2 Registers
        242. 3.10.1.242  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_L Registers
        243. 3.10.1.243  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_H Registers
        244. 3.10.1.244  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_L Registers
        245. 3.10.1.245  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_H Registers
        246. 3.10.1.246  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_CONTROL Registers
        247. 3.10.1.247  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_0 Registers
        248. 3.10.1.248  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_1 Registers
        249. 3.10.1.249  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_2 Registers
        250. 3.10.1.250  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_L Registers
        251. 3.10.1.251  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_H Registers
        252. 3.10.1.252  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_L Registers
        253. 3.10.1.253  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_H Registers
        254. 3.10.1.254  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_CONTROL Registers
        255. 3.10.1.255  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_0 Registers
        256. 3.10.1.256  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_1 Registers
        257. 3.10.1.257  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_2 Registers
        258. 3.10.1.258  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_L Registers
        259. 3.10.1.259  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_H Registers
        260. 3.10.1.260  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_L Registers
        261. 3.10.1.261  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_H Registers
        262. 3.10.1.262  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_CONTROL Registers
        263. 3.10.1.263  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_0 Registers
        264. 3.10.1.264  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_1 Registers
        265. 3.10.1.265  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_2 Registers
        266. 3.10.1.266  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_L Registers
        267. 3.10.1.267  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_H Registers
        268. 3.10.1.268  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_L Registers
        269. 3.10.1.269  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_H Registers
        270. 3.10.1.270  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_CONTROL Registers
        271. 3.10.1.271  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_0 Registers
        272. 3.10.1.272  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_1 Registers
        273. 3.10.1.273  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_2 Registers
        274. 3.10.1.274  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_L Registers
        275. 3.10.1.275  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_H Registers
        276. 3.10.1.276  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_L Registers
        277. 3.10.1.277  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_H Registers
        278. 3.10.1.278  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_CONTROL Registers
        279. 3.10.1.279  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_0 Registers
        280. 3.10.1.280  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_1 Registers
        281. 3.10.1.281  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_2 Registers
        282. 3.10.1.282  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_L Registers
        283. 3.10.1.283  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_H Registers
        284. 3.10.1.284  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_L Registers
        285. 3.10.1.285  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_H Registers
        286. 3.10.1.286  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_CONTROL Registers
        287. 3.10.1.287  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_0 Registers
        288. 3.10.1.288  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_1 Registers
        289. 3.10.1.289  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_2 Registers
        290. 3.10.1.290  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_L Registers
        291. 3.10.1.291  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_H Registers
        292. 3.10.1.292  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_L Registers
        293. 3.10.1.293  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_H Registers
        294. 3.10.1.294  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_CONTROL Registers
        295. 3.10.1.295  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_0 Registers
        296. 3.10.1.296  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_1 Registers
        297. 3.10.1.297  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_2 Registers
        298. 3.10.1.298  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_L Registers
        299. 3.10.1.299  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_H Registers
        300. 3.10.1.300  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_L Registers
        301. 3.10.1.301  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_H Registers
        302. 3.10.1.302  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_CONTROL Registers
        303. 3.10.1.303  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_0 Registers
        304. 3.10.1.304  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_1 Registers
        305. 3.10.1.305  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_2 Registers
        306. 3.10.1.306  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_L Registers
        307. 3.10.1.307  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_H Registers
        308. 3.10.1.308  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_L Registers
        309. 3.10.1.309  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_H Registers
        310. 3.10.1.310  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_CONTROL Registers
        311. 3.10.1.311  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_0 Registers
        312. 3.10.1.312  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_1 Registers
        313. 3.10.1.313  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_2 Registers
        314. 3.10.1.314  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_L Registers
        315. 3.10.1.315  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_H Registers
        316. 3.10.1.316  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_L Registers
        317. 3.10.1.317  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_H Registers
        318. 3.10.1.318  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_CONTROL Registers
        319. 3.10.1.319  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_0 Registers
        320. 3.10.1.320  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_1 Registers
        321. 3.10.1.321  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_2 Registers
        322. 3.10.1.322  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_L Registers
        323. 3.10.1.323  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_H Registers
        324. 3.10.1.324  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_L Registers
        325. 3.10.1.325  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_H Registers
        326. 3.10.1.326  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_CONTROL Registers
        327. 3.10.1.327  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_0 Registers
        328. 3.10.1.328  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_1 Registers
        329. 3.10.1.329  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_2 Registers
        330. 3.10.1.330  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_L Registers
        331. 3.10.1.331  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_H Registers
        332. 3.10.1.332  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_L Registers
        333. 3.10.1.333  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_H Registers
        334. 3.10.1.334  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_CONTROL Registers
        335. 3.10.1.335  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_0 Registers
        336. 3.10.1.336  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_1 Registers
        337. 3.10.1.337  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_2 Registers
        338. 3.10.1.338  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_L Registers
        339. 3.10.1.339  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_H Registers
        340. 3.10.1.340  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_L Registers
        341. 3.10.1.341  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_H Registers
        342. 3.10.1.342  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_CONTROL Registers
        343. 3.10.1.343  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_0 Registers
        344. 3.10.1.344  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_1 Registers
        345. 3.10.1.345  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_2 Registers
        346. 3.10.1.346  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_L Registers
        347. 3.10.1.347  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_H Registers
        348. 3.10.1.348  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_L Registers
        349. 3.10.1.349  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_H Registers
        350. 3.10.1.350  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_CONTROL Registers
        351. 3.10.1.351  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_0 Registers
        352. 3.10.1.352  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_1 Registers
        353. 3.10.1.353  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_2 Registers
        354. 3.10.1.354  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_L Registers
        355. 3.10.1.355  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_H Registers
        356. 3.10.1.356  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_L Registers
        357. 3.10.1.357  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_H Registers
        358. 3.10.1.358  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_CONTROL Registers
        359. 3.10.1.359  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_0 Registers
        360. 3.10.1.360  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_1 Registers
        361. 3.10.1.361  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_2 Registers
        362. 3.10.1.362  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_L Registers
        363. 3.10.1.363  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_H Registers
        364. 3.10.1.364  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_L Registers
        365. 3.10.1.365  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_H Registers
        366. 3.10.1.366  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_CONTROL Registers
        367. 3.10.1.367  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_0 Registers
        368. 3.10.1.368  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_1 Registers
        369. 3.10.1.369  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_2 Registers
        370. 3.10.1.370  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_L Registers
        371. 3.10.1.371  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_H Registers
        372. 3.10.1.372  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_L Registers
        373. 3.10.1.373  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_H Registers
        374. 3.10.1.374  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_CONTROL Registers
        375. 3.10.1.375  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_0 Registers
        376. 3.10.1.376  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_1 Registers
        377. 3.10.1.377  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_2 Registers
        378. 3.10.1.378  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_L Registers
        379. 3.10.1.379  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_H Registers
        380. 3.10.1.380  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_L Registers
        381. 3.10.1.381  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_H Registers
        382. 3.10.1.382  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_CONTROL Registers
        383. 3.10.1.383  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_0 Registers
        384. 3.10.1.384  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_1 Registers
        385. 3.10.1.385  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_2 Registers
        386. 3.10.1.386  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_L Registers
        387. 3.10.1.387  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_H Registers
        388. 3.10.1.388  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_L Registers
        389. 3.10.1.389  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_H Registers
        390. 3.10.1.390  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_CONTROL Registers
        391. 3.10.1.391  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_0 Registers
        392. 3.10.1.392  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_1 Registers
        393. 3.10.1.393  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_2 Registers
        394. 3.10.1.394  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_L Registers
        395. 3.10.1.395  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_H Registers
        396. 3.10.1.396  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_L Registers
        397. 3.10.1.397  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_H Registers
        398. 3.10.1.398  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_CONTROL Registers
        399. 3.10.1.399  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_0 Registers
        400. 3.10.1.400  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_1 Registers
        401. 3.10.1.401  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_2 Registers
        402. 3.10.1.402  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_L Registers
        403. 3.10.1.403  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_H Registers
        404. 3.10.1.404  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_L Registers
        405. 3.10.1.405  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_H Registers
        406. 3.10.1.406  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_CONTROL Registers
        407. 3.10.1.407  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_0 Registers
        408. 3.10.1.408  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_1 Registers
        409. 3.10.1.409  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_2 Registers
        410. 3.10.1.410  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_L Registers
        411. 3.10.1.411  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_H Registers
        412. 3.10.1.412  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_L Registers
        413. 3.10.1.413  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_H Registers
        414. 3.10.1.414  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_CONTROL Registers
        415. 3.10.1.415  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_0 Registers
        416. 3.10.1.416  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_1 Registers
        417. 3.10.1.417  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_2 Registers
        418. 3.10.1.418  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_L Registers
        419. 3.10.1.419  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_H Registers
        420. 3.10.1.420  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_L Registers
        421. 3.10.1.421  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_H Registers
        422. 3.10.1.422  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_CONTROL Registers
        423. 3.10.1.423  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_0 Registers
        424. 3.10.1.424  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_1 Registers
        425. 3.10.1.425  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_2 Registers
        426. 3.10.1.426  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_L Registers
        427. 3.10.1.427  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_H Registers
        428. 3.10.1.428  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_L Registers
        429. 3.10.1.429  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_H Registers
        430. 3.10.1.430  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_CONTROL Registers
        431. 3.10.1.431  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_0 Registers
        432. 3.10.1.432  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_1 Registers
        433. 3.10.1.433  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_2 Registers
        434. 3.10.1.434  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_L Registers
        435. 3.10.1.435  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_H Registers
        436. 3.10.1.436  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_L Registers
        437. 3.10.1.437  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_H Registers
        438. 3.10.1.438  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_CONTROL Registers
        439. 3.10.1.439  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_0 Registers
        440. 3.10.1.440  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_1 Registers
        441. 3.10.1.441  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_2 Registers
        442. 3.10.1.442  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_L Registers
        443. 3.10.1.443  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_H Registers
        444. 3.10.1.444  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_L Registers
        445. 3.10.1.445  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_H Registers
        446. 3.10.1.446  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_CONTROL Registers
        447. 3.10.1.447  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_0 Registers
        448. 3.10.1.448  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_1 Registers
        449. 3.10.1.449  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_2 Registers
        450. 3.10.1.450  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_L Registers
        451. 3.10.1.451  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_H Registers
        452. 3.10.1.452  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_L Registers
        453. 3.10.1.453  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_H Registers
        454. 3.10.1.454  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_CONTROL Registers
        455. 3.10.1.455  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_0 Registers
        456. 3.10.1.456  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_1 Registers
        457. 3.10.1.457  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_2 Registers
        458. 3.10.1.458  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_L Registers
        459. 3.10.1.459  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_H Registers
        460. 3.10.1.460  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_L Registers
        461. 3.10.1.461  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_H Registers
        462. 3.10.1.462  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_CONTROL Registers
        463. 3.10.1.463  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_0 Registers
        464. 3.10.1.464  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_1 Registers
        465. 3.10.1.465  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_2 Registers
        466. 3.10.1.466  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_L Registers
        467. 3.10.1.467  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_H Registers
        468. 3.10.1.468  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_L Registers
        469. 3.10.1.469  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_H Registers
        470. 3.10.1.470  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_CONTROL Registers
        471. 3.10.1.471  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_0 Registers
        472. 3.10.1.472  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_1 Registers
        473. 3.10.1.473  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_2 Registers
        474. 3.10.1.474  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_L Registers
        475. 3.10.1.475  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_H Registers
        476. 3.10.1.476  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_L Registers
        477. 3.10.1.477  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_H Registers
        478. 3.10.1.478  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_CONTROL Registers
        479. 3.10.1.479  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_0 Registers
        480. 3.10.1.480  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_1 Registers
        481. 3.10.1.481  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_2 Registers
        482. 3.10.1.482  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_L Registers
        483. 3.10.1.483  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_H Registers
        484. 3.10.1.484  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_L Registers
        485. 3.10.1.485  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_H Registers
        486. 3.10.1.486  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_CONTROL Registers
        487. 3.10.1.487  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_0 Registers
        488. 3.10.1.488  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_1 Registers
        489. 3.10.1.489  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_2 Registers
        490. 3.10.1.490  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_L Registers
        491. 3.10.1.491  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_H Registers
        492. 3.10.1.492  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_L Registers
        493. 3.10.1.493  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_H Registers
        494. 3.10.1.494  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_CONTROL Registers
        495. 3.10.1.495  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_0 Registers
        496. 3.10.1.496  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_1 Registers
        497. 3.10.1.497  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_2 Registers
        498. 3.10.1.498  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_L Registers
        499. 3.10.1.499  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_H Registers
        500. 3.10.1.500  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_L Registers
        501. 3.10.1.501  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_H Registers
        502. 3.10.1.502  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_CONTROL Registers
        503. 3.10.1.503  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_0 Registers
        504. 3.10.1.504  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_1 Registers
        505. 3.10.1.505  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_2 Registers
        506. 3.10.1.506  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_L Registers
        507. 3.10.1.507  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_H Registers
        508. 3.10.1.508  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_L Registers
        509. 3.10.1.509  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_H Registers
        510. 3.10.1.510  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_CONTROL Registers
        511. 3.10.1.511  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_0 Registers
        512. 3.10.1.512  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_1 Registers
        513. 3.10.1.513  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_2 Registers
        514. 3.10.1.514  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_L Registers
        515. 3.10.1.515  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_H Registers
        516. 3.10.1.516  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_L Registers
        517. 3.10.1.517  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_H Registers
        518. 3.10.1.518  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_CONTROL Registers
        519. 3.10.1.519  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_0 Registers
        520. 3.10.1.520  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_1 Registers
        521. 3.10.1.521  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_2 Registers
        522. 3.10.1.522  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_L Registers
        523. 3.10.1.523  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_H Registers
        524. 3.10.1.524  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_L Registers
        525. 3.10.1.525  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_H Registers
        526. 3.10.1.526  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_CONTROL Registers
        527. 3.10.1.527  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_0 Registers
        528. 3.10.1.528  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_1 Registers
        529. 3.10.1.529  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_2 Registers
        530. 3.10.1.530  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_L Registers
        531. 3.10.1.531  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_H Registers
        532. 3.10.1.532  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_L Registers
        533. 3.10.1.533  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_H Registers
        534. 3.10.1.534  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_CONTROL Registers
        535. 3.10.1.535  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_0 Registers
        536. 3.10.1.536  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_1 Registers
        537. 3.10.1.537  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_2 Registers
        538. 3.10.1.538  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_L Registers
        539. 3.10.1.539  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_H Registers
        540. 3.10.1.540  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_L Registers
        541. 3.10.1.541  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_H Registers
        542. 3.10.1.542  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_CONTROL Registers
        543. 3.10.1.543  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_0 Registers
        544. 3.10.1.544  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_1 Registers
        545. 3.10.1.545  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_2 Registers
        546. 3.10.1.546  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_L Registers
        547. 3.10.1.547  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_H Registers
        548. 3.10.1.548  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_L Registers
        549. 3.10.1.549  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_H Registers
        550. 3.10.1.550  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_CONTROL Registers
        551. 3.10.1.551  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_0 Registers
        552. 3.10.1.552  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_1 Registers
        553. 3.10.1.553  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_2 Registers
        554. 3.10.1.554  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_L Registers
        555. 3.10.1.555  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_H Registers
        556. 3.10.1.556  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_L Registers
        557. 3.10.1.557  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_H Registers
        558. 3.10.1.558  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_CONTROL Registers
        559. 3.10.1.559  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_0 Registers
        560. 3.10.1.560  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_1 Registers
        561. 3.10.1.561  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_2 Registers
        562. 3.10.1.562  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_L Registers
        563. 3.10.1.563  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_H Registers
        564. 3.10.1.564  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_L Registers
        565. 3.10.1.565  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_H Registers
        566. 3.10.1.566  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_CONTROL Registers
        567. 3.10.1.567  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_0 Registers
        568. 3.10.1.568  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_1 Registers
        569. 3.10.1.569  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_2 Registers
        570. 3.10.1.570  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_L Registers
        571. 3.10.1.571  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_H Registers
        572. 3.10.1.572  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_L Registers
        573. 3.10.1.573  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_H Registers
        574. 3.10.1.574  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_CONTROL Registers
        575. 3.10.1.575  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_0 Registers
        576. 3.10.1.576  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_1 Registers
        577. 3.10.1.577  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_2 Registers
        578. 3.10.1.578  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_L Registers
        579. 3.10.1.579  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_H Registers
        580. 3.10.1.580  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_L Registers
        581. 3.10.1.581  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_H Registers
        582. 3.10.1.582  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_CONTROL Registers
        583. 3.10.1.583  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_0 Registers
        584. 3.10.1.584  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_1 Registers
        585. 3.10.1.585  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_2 Registers
        586. 3.10.1.586  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_L Registers
        587. 3.10.1.587  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_H Registers
        588. 3.10.1.588  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_L Registers
        589. 3.10.1.589  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_H Registers
        590. 3.10.1.590  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_CONTROL Registers
        591. 3.10.1.591  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_0 Registers
        592. 3.10.1.592  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_1 Registers
        593. 3.10.1.593  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_2 Registers
        594. 3.10.1.594  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_L Registers
        595. 3.10.1.595  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_H Registers
        596. 3.10.1.596  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_L Registers
        597. 3.10.1.597  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_H Registers
        598. 3.10.1.598  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_CONTROL Registers
        599. 3.10.1.599  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_0 Registers
        600. 3.10.1.600  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_1 Registers
        601. 3.10.1.601  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_2 Registers
        602. 3.10.1.602  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_L Registers
        603. 3.10.1.603  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_H Registers
        604. 3.10.1.604  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_L Registers
        605. 3.10.1.605  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_H Registers
        606. 3.10.1.606  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_CONTROL Registers
        607. 3.10.1.607  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_0 Registers
        608. 3.10.1.608  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_1 Registers
        609. 3.10.1.609  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_2 Registers
        610. 3.10.1.610  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_L Registers
        611. 3.10.1.611  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_H Registers
        612. 3.10.1.612  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_L Registers
        613. 3.10.1.613  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_H Registers
        614. 3.10.1.614  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_CONTROL Registers
        615. 3.10.1.615  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_0 Registers
        616. 3.10.1.616  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_1 Registers
        617. 3.10.1.617  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_2 Registers
        618. 3.10.1.618  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_L Registers
        619. 3.10.1.619  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_H Registers
        620. 3.10.1.620  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_L Registers
        621. 3.10.1.621  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_H Registers
        622. 3.10.1.622  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_CONTROL Registers
        623. 3.10.1.623  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_0 Registers
        624. 3.10.1.624  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_1 Registers
        625. 3.10.1.625  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_2 Registers
        626. 3.10.1.626  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_L Registers
        627. 3.10.1.627  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_H Registers
        628. 3.10.1.628  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_L Registers
        629. 3.10.1.629  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_H Registers
        630. 3.10.1.630  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_CONTROL Registers
        631. 3.10.1.631  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_0 Registers
        632. 3.10.1.632  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_1 Registers
        633. 3.10.1.633  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_2 Registers
        634. 3.10.1.634  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_L Registers
        635. 3.10.1.635  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_H Registers
        636. 3.10.1.636  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_L Registers
        637. 3.10.1.637  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_H Registers
        638. 3.10.1.638  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_CONTROL Registers
        639. 3.10.1.639  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_0 Registers
        640. 3.10.1.640  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_1 Registers
        641. 3.10.1.641  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_2 Registers
        642. 3.10.1.642  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_L Registers
        643. 3.10.1.643  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_H Registers
        644. 3.10.1.644  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_L Registers
        645. 3.10.1.645  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_H Registers
        646. 3.10.1.646  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_CONTROL Registers
        647. 3.10.1.647  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_0 Registers
        648. 3.10.1.648  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_1 Registers
        649. 3.10.1.649  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_2 Registers
        650. 3.10.1.650  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_L Registers
        651. 3.10.1.651  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_H Registers
        652. 3.10.1.652  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_L Registers
        653. 3.10.1.653  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_H Registers
        654. 3.10.1.654  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_CONTROL Registers
        655. 3.10.1.655  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_0 Registers
        656. 3.10.1.656  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_1 Registers
        657. 3.10.1.657  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_2 Registers
        658. 3.10.1.658  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_L Registers
        659. 3.10.1.659  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_H Registers
        660. 3.10.1.660  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_L Registers
        661. 3.10.1.661  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_H Registers
        662. 3.10.1.662  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_CONTROL Registers
        663. 3.10.1.663  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_0 Registers
        664. 3.10.1.664  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_1 Registers
        665. 3.10.1.665  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_2 Registers
        666. 3.10.1.666  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_L Registers
        667. 3.10.1.667  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_H Registers
        668. 3.10.1.668  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_L Registers
        669. 3.10.1.669  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_H Registers
        670. 3.10.1.670  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_CONTROL Registers
        671. 3.10.1.671  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_0 Registers
        672. 3.10.1.672  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_1 Registers
        673. 3.10.1.673  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_2 Registers
        674. 3.10.1.674  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_L Registers
        675. 3.10.1.675  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_H Registers
        676. 3.10.1.676  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_L Registers
        677. 3.10.1.677  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_H Registers
        678. 3.10.1.678  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_CONTROL Registers
        679. 3.10.1.679  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_0 Registers
        680. 3.10.1.680  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_1 Registers
        681. 3.10.1.681  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_2 Registers
        682. 3.10.1.682  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_L Registers
        683. 3.10.1.683  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_H Registers
        684. 3.10.1.684  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_L Registers
        685. 3.10.1.685  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_H Registers
        686. 3.10.1.686  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_CONTROL Registers
        687. 3.10.1.687  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_0 Registers
        688. 3.10.1.688  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_1 Registers
        689. 3.10.1.689  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_2 Registers
        690. 3.10.1.690  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_L Registers
        691. 3.10.1.691  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_H Registers
        692. 3.10.1.692  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_L Registers
        693. 3.10.1.693  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_H Registers
        694. 3.10.1.694  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_CONTROL Registers
        695. 3.10.1.695  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_0 Registers
        696. 3.10.1.696  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_1 Registers
        697. 3.10.1.697  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_2 Registers
        698. 3.10.1.698  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_L Registers
        699. 3.10.1.699  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_H Registers
        700. 3.10.1.700  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_L Registers
        701. 3.10.1.701  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_H Registers
        702. 3.10.1.702  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_CONTROL Registers
        703. 3.10.1.703  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_0 Registers
        704. 3.10.1.704  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_1 Registers
        705. 3.10.1.705  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_2 Registers
        706. 3.10.1.706  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_L Registers
        707. 3.10.1.707  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_H Registers
        708. 3.10.1.708  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_L Registers
        709. 3.10.1.709  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_H Registers
        710. 3.10.1.710  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_CONTROL Registers
        711. 3.10.1.711  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_0 Registers
        712. 3.10.1.712  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_1 Registers
        713. 3.10.1.713  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_2 Registers
        714. 3.10.1.714  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_L Registers
        715. 3.10.1.715  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_H Registers
        716. 3.10.1.716  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_L Registers
        717. 3.10.1.717  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_H Registers
        718. 3.10.1.718  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_CONTROL Registers
        719. 3.10.1.719  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_L Registers
        720. 3.10.1.720  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_H Registers
        721. 3.10.1.721  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_L Registers
        722. 3.10.1.722  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_H Registers
        723. 3.10.1.723  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_DEF_CONTROL Registers
        724. 3.10.1.724  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_CONTROL Registers
        725. 3.10.1.725  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_L Registers
        726. 3.10.1.726  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_H Registers
        727. 3.10.1.727  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_L Registers
        728. 3.10.1.728  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_H Registers
        729. 3.10.1.729  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_DEF_CONTROL Registers
        730. 3.10.1.730  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_CONTROL Registers
        731. 3.10.1.731  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        732. 3.10.1.732  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        733. 3.10.1.733  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        734. 3.10.1.734  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        735. 3.10.1.735  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_DEF_CONTROL Registers
        736. 3.10.1.736  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_CONTROL Registers
        737. 3.10.1.737  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        738. 3.10.1.738  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        739. 3.10.1.739  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        740. 3.10.1.740  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        741. 3.10.1.741  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_DEF_CONTROL Registers
        742. 3.10.1.742  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_CONTROL Registers
        743. 3.10.1.743  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        744. 3.10.1.744  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        745. 3.10.1.745  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        746. 3.10.1.746  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        747. 3.10.1.747  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_DEF_CONTROL Registers
        748. 3.10.1.748  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_CONTROL Registers
        749. 3.10.1.749  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        750. 3.10.1.750  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        751. 3.10.1.751  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        752. 3.10.1.752  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        753. 3.10.1.753  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_DEF_CONTROL Registers
        754. 3.10.1.754  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        755. 3.10.1.755  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        756. 3.10.1.756  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        757. 3.10.1.757  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        758. 3.10.1.758  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        759. 3.10.1.759  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        760. 3.10.1.760  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        761. 3.10.1.761  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        762. 3.10.1.762  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        763. 3.10.1.763  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        764. 3.10.1.764  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        765. 3.10.1.765  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        766. 3.10.1.766  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        767. 3.10.1.767  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        768. 3.10.1.768  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        769. 3.10.1.769  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        770. 3.10.1.770  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        771. 3.10.1.771  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        772. 3.10.1.772  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        773. 3.10.1.773  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        774. 3.10.1.774  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        775. 3.10.1.775  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        776. 3.10.1.776  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        777. 3.10.1.777  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        778. 3.10.1.778  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        779. 3.10.1.779  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        780. 3.10.1.780  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        781. 3.10.1.781  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        782. 3.10.1.782  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        783. 3.10.1.783  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        784. 3.10.1.784  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        785. 3.10.1.785  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        786. 3.10.1.786  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        787. 3.10.1.787  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        788. 3.10.1.788  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        789. 3.10.1.789  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        790. 3.10.1.790  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        791. 3.10.1.791  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        792. 3.10.1.792  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        793. 3.10.1.793  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        794. 3.10.1.794  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        795. 3.10.1.795  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        796. 3.10.1.796  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        797. 3.10.1.797  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        798. 3.10.1.798  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        799. 3.10.1.799  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        800. 3.10.1.800  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        801. 3.10.1.801  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        802. 3.10.1.802  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        803. 3.10.1.803  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        804. 3.10.1.804  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        805. 3.10.1.805  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        806. 3.10.1.806  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        807. 3.10.1.807  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        808. 3.10.1.808  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        809. 3.10.1.809  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        810. 3.10.1.810  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        811. 3.10.1.811  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        812. 3.10.1.812  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        813. 3.10.1.813  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        814. 3.10.1.814  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        815. 3.10.1.815  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        816. 3.10.1.816  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        817. 3.10.1.817  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        818. 3.10.1.818  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        819. 3.10.1.819  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        820. 3.10.1.820  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        821. 3.10.1.821  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        822. 3.10.1.822  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        823. 3.10.1.823  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        824. 3.10.1.824  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        825. 3.10.1.825  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        826. 3.10.1.826  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        827. 3.10.1.827  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        828. 3.10.1.828  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        829. 3.10.1.829  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        830. 3.10.1.830  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        831. 3.10.1.831  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        832. 3.10.1.832  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        833. 3.10.1.833  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        834. 3.10.1.834  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        835. 3.10.1.835  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        836. 3.10.1.836  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        837. 3.10.1.837  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        838. 3.10.1.838  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        839. 3.10.1.839  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        840. 3.10.1.840  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        841. 3.10.1.841  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        842. 3.10.1.842  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        843. 3.10.1.843  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        844. 3.10.1.844  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        845. 3.10.1.845  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        846. 3.10.1.846  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        847. 3.10.1.847  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        848. 3.10.1.848  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        849. 3.10.1.849  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        850. 3.10.1.850  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        851. 3.10.1.851  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        852. 3.10.1.852  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        853. 3.10.1.853  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        854. 3.10.1.854  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        855. 3.10.1.855  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        856. 3.10.1.856  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        857. 3.10.1.857  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        858. 3.10.1.858  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        859. 3.10.1.859  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        860. 3.10.1.860  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        861. 3.10.1.861  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        862. 3.10.1.862  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        863. 3.10.1.863  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        864. 3.10.1.864  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        865. 3.10.1.865  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        866. 3.10.1.866  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        867. 3.10.1.867  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        868. 3.10.1.868  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        869. 3.10.1.869  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        870. 3.10.1.870  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        871. 3.10.1.871  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        872. 3.10.1.872  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        873. 3.10.1.873  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        874. 3.10.1.874  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        875. 3.10.1.875  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        876. 3.10.1.876  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        877. 3.10.1.877  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        878. 3.10.1.878  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        879. 3.10.1.879  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        880. 3.10.1.880  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        881. 3.10.1.881  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        882. 3.10.1.882  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        883. 3.10.1.883  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        884. 3.10.1.884  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        885. 3.10.1.885  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        886. 3.10.1.886  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        887. 3.10.1.887  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        888. 3.10.1.888  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        889. 3.10.1.889  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        890. 3.10.1.890  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        891. 3.10.1.891  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        892. 3.10.1.892  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        893. 3.10.1.893  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        894. 3.10.1.894  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        895. 3.10.1.895  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        896. 3.10.1.896  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        897. 3.10.1.897  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        898. 3.10.1.898  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        899. 3.10.1.899  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        900. 3.10.1.900  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        901. 3.10.1.901  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        902. 3.10.1.902  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        903. 3.10.1.903  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        904. 3.10.1.904  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        905. 3.10.1.905  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        906. 3.10.1.906  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        907. 3.10.1.907  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        908. 3.10.1.908  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        909. 3.10.1.909  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        910. 3.10.1.910  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        911. 3.10.1.911  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        912. 3.10.1.912  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        913. 3.10.1.913  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        914. 3.10.1.914  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        915. 3.10.1.915  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        916. 3.10.1.916  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        917. 3.10.1.917  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        918. 3.10.1.918  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        919. 3.10.1.919  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        920. 3.10.1.920  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        921. 3.10.1.921  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        922. 3.10.1.922  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        923. 3.10.1.923  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        924. 3.10.1.924  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        925. 3.10.1.925  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        926. 3.10.1.926  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        927. 3.10.1.927  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        928. 3.10.1.928  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        929. 3.10.1.929  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        930. 3.10.1.930  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        931. 3.10.1.931  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        932. 3.10.1.932  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        933. 3.10.1.933  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        934. 3.10.1.934  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        935. 3.10.1.935  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        936. 3.10.1.936  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        937. 3.10.1.937  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        938. 3.10.1.938  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        939. 3.10.1.939  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        940. 3.10.1.940  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        941. 3.10.1.941  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        942. 3.10.1.942  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        943. 3.10.1.943  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        944. 3.10.1.944  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        945. 3.10.1.945  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        946. 3.10.1.946  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        947. 3.10.1.947  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        948. 3.10.1.948  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        949. 3.10.1.949  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        950. 3.10.1.950  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        951. 3.10.1.951  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        952. 3.10.1.952  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        953. 3.10.1.953  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        954. 3.10.1.954  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        955. 3.10.1.955  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        956. 3.10.1.956  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        957. 3.10.1.957  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        958. 3.10.1.958  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        959. 3.10.1.959  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        960. 3.10.1.960  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        961. 3.10.1.961  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        962. 3.10.1.962  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        963. 3.10.1.963  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        964. 3.10.1.964  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_CONTROL Registers
        965. 3.10.1.965  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_L Registers
        966. 3.10.1.966  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_H Registers
        967. 3.10.1.967  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_L Registers
        968. 3.10.1.968  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_H Registers
        969. 3.10.1.969  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_CONTROL Registers
        970. 3.10.1.970  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_L Registers
        971. 3.10.1.971  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_H Registers
        972. 3.10.1.972  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_L Registers
        973. 3.10.1.973  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_H Registers
        974. 3.10.1.974  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_CONTROL Registers
        975. 3.10.1.975  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_L Registers
        976. 3.10.1.976  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_H Registers
        977. 3.10.1.977  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_L Registers
        978. 3.10.1.978  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_H Registers
        979. 3.10.1.979  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_CONTROL Registers
        980. 3.10.1.980  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_L Registers
        981. 3.10.1.981  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_H Registers
        982. 3.10.1.982  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_L Registers
        983. 3.10.1.983  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_H Registers
        984. 3.10.1.984  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_CONTROL Registers
        985. 3.10.1.985  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_L Registers
        986. 3.10.1.986  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_H Registers
        987. 3.10.1.987  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_L Registers
        988. 3.10.1.988  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_H Registers
        989. 3.10.1.989  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_CONTROL Registers
        990. 3.10.1.990  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_L Registers
        991. 3.10.1.991  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_H Registers
        992. 3.10.1.992  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_L Registers
        993. 3.10.1.993  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_H Registers
        994. 3.10.1.994  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_CONTROL Registers
        995. 3.10.1.995  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_L Registers
        996. 3.10.1.996  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_H Registers
        997. 3.10.1.997  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_L Registers
        998. 3.10.1.998  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_H Registers
        999. 3.10.1.999  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_CONTROL Registers
        1000. 3.10.1.1000 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_L Registers
        1001. 3.10.1.1001 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_H Registers
        1002. 3.10.1.1002 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_L Registers
        1003. 3.10.1.1003 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_H Registers
        1004. 3.10.1.1004 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_DEF_CONTROL Registers
        1005. 3.10.1.1005 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_CONTROL Registers
        1006. 3.10.1.1006 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1007. 3.10.1.1007 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1008. 3.10.1.1008 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1009. 3.10.1.1009 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1010. 3.10.1.1010 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_CONTROL Registers
        1011. 3.10.1.1011 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_L Registers
        1012. 3.10.1.1012 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_H Registers
        1013. 3.10.1.1013 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_L Registers
        1014. 3.10.1.1014 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_H Registers
        1015. 3.10.1.1015 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_CONTROL Registers
        1016. 3.10.1.1016 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_L Registers
        1017. 3.10.1.1017 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_H Registers
        1018. 3.10.1.1018 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_L Registers
        1019. 3.10.1.1019 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_H Registers
        1020. 3.10.1.1020 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_CONTROL Registers
        1021. 3.10.1.1021 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_L Registers
        1022. 3.10.1.1022 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_H Registers
        1023. 3.10.1.1023 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_L Registers
        1024. 3.10.1.1024 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_H Registers
        1025. 3.10.1.1025 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_CONTROL Registers
        1026. 3.10.1.1026 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_L Registers
        1027. 3.10.1.1027 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_H Registers
        1028. 3.10.1.1028 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_L Registers
        1029. 3.10.1.1029 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_H Registers
        1030. 3.10.1.1030 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_CONTROL Registers
        1031. 3.10.1.1031 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_L Registers
        1032. 3.10.1.1032 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_H Registers
        1033. 3.10.1.1033 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_L Registers
        1034. 3.10.1.1034 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_H Registers
        1035. 3.10.1.1035 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_CONTROL Registers
        1036. 3.10.1.1036 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_L Registers
        1037. 3.10.1.1037 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_H Registers
        1038. 3.10.1.1038 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_L Registers
        1039. 3.10.1.1039 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_H Registers
        1040. 3.10.1.1040 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_CONTROL Registers
        1041. 3.10.1.1041 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_L Registers
        1042. 3.10.1.1042 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_H Registers
        1043. 3.10.1.1043 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_L Registers
        1044. 3.10.1.1044 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_H Registers
        1045. 3.10.1.1045 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_DEF_CONTROL Registers
        1046. 3.10.1.1046 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_CONTROL Registers
        1047. 3.10.1.1047 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1048. 3.10.1.1048 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1049. 3.10.1.1049 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1050. 3.10.1.1050 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1051. 3.10.1.1051 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_DEF_CONTROL Registers
        1052. 3.10.1.1052 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_CONTROL Registers
        1053. 3.10.1.1053 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        1054. 3.10.1.1054 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        1055. 3.10.1.1055 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        1056. 3.10.1.1056 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        1057. 3.10.1.1057 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_DEF_CONTROL Registers
        1058. 3.10.1.1058 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_CONTROL Registers
        1059. 3.10.1.1059 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_L Registers
        1060. 3.10.1.1060 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_H Registers
        1061. 3.10.1.1061 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_L Registers
        1062. 3.10.1.1062 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_H Registers
        1063. 3.10.1.1063 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_DEF_CONTROL Registers
        1064. 3.10.1.1064 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_CONTROL Registers
        1065. 3.10.1.1065 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_L Registers
        1066. 3.10.1.1066 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_H Registers
        1067. 3.10.1.1067 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_L Registers
        1068. 3.10.1.1068 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_H Registers
        1069. 3.10.1.1069 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_CONTROL Registers
        1070. 3.10.1.1070 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_L Registers
        1071. 3.10.1.1071 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_H Registers
        1072. 3.10.1.1072 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_L Registers
        1073. 3.10.1.1073 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_H Registers
        1074. 3.10.1.1074 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_CONTROL Registers
        1075. 3.10.1.1075 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_L Registers
        1076. 3.10.1.1076 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_H Registers
        1077. 3.10.1.1077 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_L Registers
        1078. 3.10.1.1078 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_H Registers
        1079. 3.10.1.1079 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_CONTROL Registers
        1080. 3.10.1.1080 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_L Registers
        1081. 3.10.1.1081 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_H Registers
        1082. 3.10.1.1082 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_L Registers
        1083. 3.10.1.1083 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_H Registers
        1084. 3.10.1.1084 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_CONTROL Registers
        1085. 3.10.1.1085 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_L Registers
        1086. 3.10.1.1086 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_H Registers
        1087. 3.10.1.1087 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_L Registers
        1088. 3.10.1.1088 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_H Registers
        1089. 3.10.1.1089 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_CONTROL Registers
        1090. 3.10.1.1090 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_L Registers
        1091. 3.10.1.1091 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_H Registers
        1092. 3.10.1.1092 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_L Registers
        1093. 3.10.1.1093 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_H Registers
        1094. 3.10.1.1094 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_CONTROL Registers
        1095. 3.10.1.1095 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_L Registers
        1096. 3.10.1.1096 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_H Registers
        1097. 3.10.1.1097 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_L Registers
        1098. 3.10.1.1098 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_H Registers
        1099. 3.10.1.1099 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_CONTROL Registers
        1100. 3.10.1.1100 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_L Registers
        1101. 3.10.1.1101 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_H Registers
        1102. 3.10.1.1102 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_L Registers
        1103. 3.10.1.1103 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_H Registers
        1104. 3.10.1.1104 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_DEF_CONTROL Registers
        1105. 3.10.1.1105 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_CONTROL Registers
        1106. 3.10.1.1106 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_L Registers
        1107. 3.10.1.1107 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_H Registers
        1108. 3.10.1.1108 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_L Registers
        1109. 3.10.1.1109 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_H Registers
        1110. 3.10.1.1110 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_CONTROL Registers
        1111. 3.10.1.1111 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_L Registers
        1112. 3.10.1.1112 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_H Registers
        1113. 3.10.1.1113 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_L Registers
        1114. 3.10.1.1114 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_H Registers
        1115. 3.10.1.1115 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_CONTROL Registers
        1116. 3.10.1.1116 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_L Registers
        1117. 3.10.1.1117 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_H Registers
        1118. 3.10.1.1118 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_L Registers
        1119. 3.10.1.1119 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_H Registers
        1120. 3.10.1.1120 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_CONTROL Registers
        1121. 3.10.1.1121 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_L Registers
        1122. 3.10.1.1122 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_H Registers
        1123. 3.10.1.1123 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_L Registers
        1124. 3.10.1.1124 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_H Registers
        1125. 3.10.1.1125 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_CONTROL Registers
        1126. 3.10.1.1126 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_L Registers
        1127. 3.10.1.1127 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_H Registers
        1128. 3.10.1.1128 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_L Registers
        1129. 3.10.1.1129 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_H Registers
        1130. 3.10.1.1130 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_CONTROL Registers
        1131. 3.10.1.1131 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_L Registers
        1132. 3.10.1.1132 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_H Registers
        1133. 3.10.1.1133 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_L Registers
        1134. 3.10.1.1134 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_H Registers
        1135. 3.10.1.1135 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_CONTROL Registers
        1136. 3.10.1.1136 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_L Registers
        1137. 3.10.1.1137 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_H Registers
        1138. 3.10.1.1138 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_L Registers
        1139. 3.10.1.1139 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_H Registers
        1140. 3.10.1.1140 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_CONTROL Registers
        1141. 3.10.1.1141 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_L Registers
        1142. 3.10.1.1142 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_H Registers
        1143. 3.10.1.1143 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_L Registers
        1144. 3.10.1.1144 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_H Registers
        1145. 3.10.1.1145 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_DEF_CONTROL Registers
        1146. 3.10.1.1146 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_CONTROL Registers
        1147. 3.10.1.1147 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_L Registers
        1148. 3.10.1.1148 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_H Registers
        1149. 3.10.1.1149 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_L Registers
        1150. 3.10.1.1150 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_H Registers
        1151. 3.10.1.1151 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_DEF_CONTROL Registers
        1152. 3.10.1.1152 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_CONTROL Registers
        1153. 3.10.1.1153 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_L Registers
        1154. 3.10.1.1154 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_H Registers
        1155. 3.10.1.1155 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_L Registers
        1156. 3.10.1.1156 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_H Registers
        1157. 3.10.1.1157 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_DEF_CONTROL Registers
        1158. 3.10.1.1158 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_CONTROL Registers
        1159. 3.10.1.1159 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_L Registers
        1160. 3.10.1.1160 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_H Registers
        1161. 3.10.1.1161 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_L Registers
        1162. 3.10.1.1162 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_H Registers
        1163. 3.10.1.1163 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_DEF_CONTROL Registers
        1164. 3.10.1.1164 GLB_PID Registers
        1165. 3.10.1.1165 GLB_DESTINATION_ID Registers
        1166. 3.10.1.1166 GLB_EXCEPTION_LOGGING_CONTROL Registers
        1167. 3.10.1.1167 GLB_EXCEPTION_LOGGING_HEADER0 Registers
        1168. 3.10.1.1168 GLB_EXCEPTION_LOGGING_HEADER1 Registers
        1169. 3.10.1.1169 GLB_EXCEPTION_LOGGING_DATA0 Registers
        1170. 3.10.1.1170 GLB_EXCEPTION_LOGGING_DATA1 Registers
        1171. 3.10.1.1171 GLB_EXCEPTION_LOGGING_DATA2 Registers
        1172. 3.10.1.1172 GLB_EXCEPTION_LOGGING_DATA3 Registers
        1173. 3.10.1.1173 GLB_EXCEPTION_PEND_SET Registers
        1174. 3.10.1.1174 GLB_EXCEPTION_PEND_CLEAR Registers
        1175. 3.10.1.1175 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_MAP0 Registers
        1176. 3.10.1.1176 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_MAP0 Registers
        1177. 3.10.1.1177 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MAP0 Registers
        1178. 3.10.1.1178 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MAP0 Registers
        1179. 3.10.1.1179 QOS_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_MAP0 Registers
        1180. 3.10.1.1180 QOS_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_MAP0 Registers
        1181. 3.10.1.1181 QOS_IPULSAR_LITE_MAIN_0_CPU0_RMST_MAP0 Registers
        1182. 3.10.1.1182 QOS_IPULSAR_LITE_MAIN_0_CPU0_WMST_MAP0 Registers
        1183. 3.10.1.1183 QOS_IPULSAR_LITE_MAIN_0_CPU1_RMST_MAP0 Registers
        1184. 3.10.1.1184 QOS_IPULSAR_LITE_MAIN_0_CPU1_WMST_MAP0 Registers
        1185. 3.10.1.1185 QOS_IPULSAR_LITE_MAIN_1_CPU0_RMST_MAP0 Registers
        1186. 3.10.1.1186 QOS_IPULSAR_LITE_MAIN_1_CPU0_WMST_MAP0 Registers
        1187. 3.10.1.1187 QOS_IPULSAR_LITE_MAIN_1_CPU1_RMST_MAP0 Registers
        1188. 3.10.1.1188 QOS_IPULSAR_LITE_MAIN_1_CPU1_WMST_MAP0 Registers
        1189. 3.10.1.1189 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP0 Registers
        1190. 3.10.1.1190 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP1 Registers
        1191. 3.10.1.1191 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP2 Registers
        1192. 3.10.1.1192 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP3 Registers
        1193. 3.10.1.1193 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP4 Registers
        1194. 3.10.1.1194 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP5 Registers
        1195. 3.10.1.1195 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP6 Registers
        1196. 3.10.1.1196 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP7 Registers
        1197. 3.10.1.1197 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP8 Registers
        1198. 3.10.1.1198 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP9 Registers
        1199. 3.10.1.1199 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP10 Registers
        1200. 3.10.1.1200 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP11 Registers
        1201. 3.10.1.1201 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP12 Registers
        1202. 3.10.1.1202 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP13 Registers
        1203. 3.10.1.1203 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP14 Registers
        1204. 3.10.1.1204 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP15 Registers
        1205. 3.10.1.1205 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP0 Registers
        1206. 3.10.1.1206 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP1 Registers
        1207. 3.10.1.1207 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP2 Registers
        1208. 3.10.1.1208 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP3 Registers
        1209. 3.10.1.1209 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP4 Registers
        1210. 3.10.1.1210 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP5 Registers
        1211. 3.10.1.1211 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP6 Registers
        1212. 3.10.1.1212 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP7 Registers
        1213. 3.10.1.1213 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP8 Registers
        1214. 3.10.1.1214 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP9 Registers
        1215. 3.10.1.1215 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP10 Registers
        1216. 3.10.1.1216 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP11 Registers
        1217. 3.10.1.1217 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP12 Registers
        1218. 3.10.1.1218 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP13 Registers
        1219. 3.10.1.1219 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP14 Registers
        1220. 3.10.1.1220 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP15 Registers
        1221. 3.10.1.1221 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP0 Registers
        1222. 3.10.1.1222 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP1 Registers
        1223. 3.10.1.1223 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP2 Registers
        1224. 3.10.1.1224 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP3 Registers
        1225. 3.10.1.1225 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP4 Registers
        1226. 3.10.1.1226 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP5 Registers
        1227. 3.10.1.1227 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP6 Registers
        1228. 3.10.1.1228 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP7 Registers
        1229. 3.10.1.1229 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP0 Registers
        1230. 3.10.1.1230 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP1 Registers
        1231. 3.10.1.1231 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP2 Registers
        1232. 3.10.1.1232 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP3 Registers
        1233. 3.10.1.1233 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP4 Registers
        1234. 3.10.1.1234 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP5 Registers
        1235. 3.10.1.1235 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP6 Registers
        1236. 3.10.1.1236 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP7 Registers
        1237. 3.10.1.1237 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MAP0 Registers
        1238. 3.10.1.1238 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MAP0 Registers
        1239. 3.10.1.1239 QOS_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_MAP0 Registers
        1240. 3.10.1.1240 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP0 Registers
        1241. 3.10.1.1241 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP1 Registers
        1242. 3.10.1.1242 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP2 Registers
        1243. 3.10.1.1243 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP3 Registers
        1244. 3.10.1.1244 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP4 Registers
        1245. 3.10.1.1245 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP5 Registers
        1246. 3.10.1.1246 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP6 Registers
        1247. 3.10.1.1247 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP7 Registers
        1248. 3.10.1.1248 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP0 Registers
        1249. 3.10.1.1249 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP1 Registers
        1250. 3.10.1.1250 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP2 Registers
        1251. 3.10.1.1251 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP3 Registers
        1252. 3.10.1.1252 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP4 Registers
        1253. 3.10.1.1253 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP5 Registers
        1254. 3.10.1.1254 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP6 Registers
        1255. 3.10.1.1255 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP7 Registers
        1256. 3.10.1.1256 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_MAP0 Registers
        1257. 3.10.1.1257 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_MAP0 Registers
        1258. 3.10.1.1258 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_CONTROL Registers
        1259. 3.10.1.1259 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_L Registers
        1260. 3.10.1.1260 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_H Registers
        1261. 3.10.1.1261 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_L Registers
        1262. 3.10.1.1262 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_H Registers
        1263. 3.10.1.1263 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_DEF_CONTROL Registers
        1264. 3.10.1.1264 QOS_IBLAZAR_MCU_0_VBUSP_M_MAP0 Registers
        1265. 3.10.1.1265 Access Table
      2. 3.10.2 CBASS_FW Registers
        1. 3.10.2.1  ERR_REGS_CBASS_FW_PID Registers
        2. 3.10.2.2  ERR_REGS_CBASS_FW_DESTINATION_ID Registers
        3. 3.10.2.3  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.2.4  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.2.5  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.2.6  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.2.7  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.2.8  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.2.9  ERR_REGS_CBASS_FW_ERR_INTR_RAW_STAT Registers
        10. 3.10.2.10 ERR_REGS_CBASS_FW_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.2.11 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_SET Registers
        12. 3.10.2.12 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.2.13 ERR_REGS_CBASS_FW_EOI Registers
        14. 3.10.2.14 Access Table
      3. 3.10.3 CBASS_INFRA Registers
        1. 3.10.3.1   ERR_REGS_CBASS_INFRA_PID Registers
        2. 3.10.3.2   ERR_REGS_CBASS_INFRA_DESTINATION_ID Registers
        3. 3.10.3.3   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.3.4   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.3.5   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.3.6   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.3.7   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.3.8   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.3.9   ERR_REGS_CBASS_INFRA_ERR_INTR_RAW_STAT Registers
        10. 3.10.3.10  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.3.11  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_SET Registers
        12. 3.10.3.12  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.3.13  ERR_REGS_CBASS_INFRA_EOI Registers
        14. 3.10.3.14  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_CONTROL Registers
        15. 3.10.3.15  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.3.16  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.3.17  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.3.18  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.3.19  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.3.20  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.3.21  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.3.22  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_CONTROL Registers
        23. 3.10.3.23  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.3.24  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.3.25  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.3.26  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.3.27  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.3.28  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.3.29  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.3.30  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_CONTROL Registers
        31. 3.10.3.31  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.3.32  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.3.33  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.3.34  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.3.35  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.3.36  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.3.37  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.3.38  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_CONTROL Registers
        39. 3.10.3.39  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.3.40  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.3.41  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.3.42  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.3.43  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.3.44  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.3.45  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.3.46  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_CONTROL Registers
        47. 3.10.3.47  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.3.48  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.3.49  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.3.50  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.3.51  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.3.52  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.3.53  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.3.54  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_CONTROL Registers
        55. 3.10.3.55  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.3.56  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.3.57  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.3.58  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.3.59  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.3.60  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.3.61  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.3.62  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_CONTROL Registers
        63. 3.10.3.63  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.3.64  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.3.65  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.3.66  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.3.67  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.3.68  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.3.69  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.3.70  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_CONTROL Registers
        71. 3.10.3.71  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.3.72  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.3.73  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.3.74  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.3.75  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.3.76  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.3.77  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.3.78  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_CONTROL Registers
        79. 3.10.3.79  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.3.80  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.3.81  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.3.82  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.3.83  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.3.84  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.3.85  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.3.86  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_CONTROL Registers
        87. 3.10.3.87  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.3.88  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.3.89  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.3.90  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.3.91  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.3.92  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.3.93  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.3.94  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_CONTROL Registers
        95. 3.10.3.95  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.3.96  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.3.97  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.3.98  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.3.99  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.3.100 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.3.101 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.3.102 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_CONTROL Registers
        103. 3.10.3.103 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.3.104 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.3.105 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.3.106 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.3.107 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.3.108 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.3.109 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.3.110 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_CONTROL Registers
        111. 3.10.3.111 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.3.112 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.3.113 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.3.114 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.3.115 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.3.116 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.3.117 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.3.118 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_CONTROL Registers
        119. 3.10.3.119 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.3.120 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.3.121 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.3.122 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.3.123 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.3.124 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.3.125 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.3.126 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_CONTROL Registers
        127. 3.10.3.127 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.3.128 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.3.129 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.3.130 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.3.131 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.3.132 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.3.133 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.3.134 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_CONTROL Registers
        135. 3.10.3.135 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.3.136 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.3.137 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.3.138 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.3.139 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.3.140 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.3.141 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.3.142 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        143. 3.10.3.143 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        144. 3.10.3.144 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        145. 3.10.3.145 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        146. 3.10.3.146 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        147. 3.10.3.147 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        148. 3.10.3.148 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        149. 3.10.3.149 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        150. 3.10.3.150 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        151. 3.10.3.151 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        152. 3.10.3.152 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        153. 3.10.3.153 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        154. 3.10.3.154 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        155. 3.10.3.155 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        156. 3.10.3.156 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        157. 3.10.3.157 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        158. 3.10.3.158 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        159. 3.10.3.159 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        160. 3.10.3.160 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        161. 3.10.3.161 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        162. 3.10.3.162 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        163. 3.10.3.163 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        164. 3.10.3.164 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        165. 3.10.3.165 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        166. 3.10.3.166 GLB_REGS_CBASS_INFRA_PID Registers
        167. 3.10.3.167 GLB_REGS_CBASS_INFRA_DESTINATION_ID Registers
        168. 3.10.3.168 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_CONTROL Registers
        169. 3.10.3.169 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        170. 3.10.3.170 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        171. 3.10.3.171 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        172. 3.10.3.172 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        173. 3.10.3.173 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        174. 3.10.3.174 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        175. 3.10.3.175 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_SET Registers
        176. 3.10.3.176 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_CLEAR Registers
        177. 3.10.3.177 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_MAP0 Registers
        178. 3.10.3.178 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_MAP0 Registers
        179. 3.10.3.179 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_MAP0 Registers
        180. 3.10.3.180 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_MAP0 Registers
        181. 3.10.3.181 Access Table
      4. 3.10.4 CBASS_DBG Registers
        1. 3.10.4.1  ERR_REGS_CBASS_DBG_PID Registers
        2. 3.10.4.2  ERR_REGS_CBASS_DBG_DESTINATION_ID Registers
        3. 3.10.4.3  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.4.4  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.4.5  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.4.6  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.4.7  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.4.8  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.4.9  ERR_REGS_CBASS_DBG_ERR_INTR_RAW_STAT Registers
        10. 3.10.4.10 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.4.11 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_SET Registers
        12. 3.10.4.12 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.4.13 ERR_REGS_CBASS_DBG_EOI Registers
        14. 3.10.4.14 Access Table
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Boot Terminology
    2. 4.2 Boot Process
      1. 4.2.1 Public ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
    3. 4.3 Boot Mode Pins
      1. 4.3.1 BOOTMODE Pin Mapping
        1. 4.3.1.1 Primary Boot Mode Selection and Configuration
        2. 4.3.1.2 Backup Boot Mode Selection and Configuration
    4. 4.4 Boot Modes
      1. 4.4.1  OSPI, xSPI, QSPI, SPI Boot
        1. 4.4.1.1 OSPI Boot
          1. 4.4.1.1.1 OSPI Bootloader Operation
            1. 4.4.1.1.1.1 OSPI Initialization Process
            2. 4.4.1.1.1.2 OSPI Loading Process
        2. 4.4.1.2 xSPI Boot
          1. 4.4.1.2.1 xSPI Bootloader Operation
        3. 4.4.1.3 QSPI Boot
          1. 4.4.1.3.1 QSPI Bootloader Operation
            1. 4.4.1.3.1.1 QSPI Initialization Process
            2. 4.4.1.3.1.2 QSPI Loading Process
        4. 4.4.1.4 SPI Boot
          1. 4.4.1.4.1 SPI Bootloader Operation
            1. 4.4.1.4.1.1 SPI Initialization Process
            2. 4.4.1.4.1.2 SPI Loading Process
      2. 4.4.2  I2C Boot
        1. 4.4.2.1 I2C Bootloader Operation
          1. 4.4.2.1.1 I2C Initialization Process
            1. 4.4.2.1.1.1 Block Size
            2. 4.4.2.1.1.2 Addressing
          2. 4.4.2.1.2 I2C Loading Process
            1. 4.4.2.1.2.1 Loading a Boot Image From EEPROM
      3. 4.4.3  SD Card Boot
        1. 4.4.3.1 SD Card Bootloader Operation
      4. 4.4.4  eMMC Boot
        1. 4.4.4.1 eMMC Bootloader Operation
      5. 4.4.5  Ethernet Boot
        1. 4.4.5.1 Ethernet Bootloader Operation
          1. 4.4.5.1.1 Ethernet Initialization Process
          2. 4.4.5.1.2 Ethernet Loading Process
            1. 4.4.5.1.2.1 Ethernet Boot Data Formats
              1. 4.4.5.1.2.1.1 Limitations
              2. 4.4.5.1.2.1.2 BOOTP Request
                1. 4.4.5.1.2.1.2.1 MAC Header (DIX)
                2. 4.4.5.1.2.1.2.2 IPv4 Header
                3. 4.4.5.1.2.1.2.3 UDP Header
                4. 4.4.5.1.2.1.2.4 BOOTP Payload
                5. 4.4.5.1.2.1.2.5 TFTP
          3. 4.4.5.1.3 Ethernet Hand Over Process
      6. 4.4.6  USB Boot
        1. 4.4.6.1 USB Bootloader Operation
          1. 4.4.6.1.1 USB-Specific Attributes
            1. 4.4.6.1.1.1 DFU Device Mode
        2. 4.4.6.2 Limitations for USB DFU and PCIe boot modes
      7. 4.4.7  PCIe Boot
        1. 4.4.7.1 PCIe Bootloader Operation
          1. 4.4.7.1.1 PCIe Initialization Process
          2. 4.4.7.1.2 PCIe Loading Process
        2. 4.4.7.2 Limitations for USB DFU and PCIe boot modes
      8. 4.4.8  UART Boot
        1. 4.4.8.1 UART Bootloader Operation
          1. 4.4.8.1.1 Initialization Process
          2. 4.4.8.1.2 UART Loading Process
            1. 4.4.8.1.2.1 UART XMODEM
          3. 4.4.8.1.3 UART Hand-Over Process
      9. 4.4.9  GPMC NOR Boot
        1. 4.4.9.1 GPMC NOR Bootloader Operation
          1. 4.4.9.1.1 GPMC NOR Initialization Process
          2. 4.4.9.1.2 GPMC NOR Loading Process
      10. 4.4.10 GPMC NAND Boot
        1. 4.4.10.1 GPMC NAND Bootloader Operation
      11. 4.4.11 No boot/Development boot
    5. 4.5 PLL Configuration
    6. 4.6 Boot Parameter Tables
      1. 4.6.1  Common Header
      2. 4.6.2  PLL Setup
      3. 4.6.3  OSPI/QSPI/SPI Boot Parameter Table
      4. 4.6.4  UART Boot Parameter Table
      5. 4.6.5  PCIe Boot Parameter Table
      6. 4.6.6  I2C Boot Parameter Table
      7. 4.6.7  MMCSD/eMMC Boot Parameter Table
      8. 4.6.8  Ethernet Boot Parameter Table
      9. 4.6.9  xSPI Boot Parameter Table
      10. 4.6.10 USB DFU Boot Parameter Table
      11. 4.6.11 USB MSC Boot Parameter Table
      12. 4.6.12 GPMC NOR Boot Parameter Table
      13. 4.6.13 GPMC NAND Boot Parameter Table
    7. 4.7 Boot Image Format
      1. 4.7.1 Overall Structure
      2. 4.7.2 X.509 Certificate
      3. 4.7.3 Organizational Identifier (OID)
      4. 4.7.4 X.509 Extensions Specific to Boot
        1. 4.7.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.7.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.7.5 Extended Boot Info Extension
        1. 4.7.5.1 Impact on HS Device
        2. 4.7.5.2 Extended Boot Info Details
        3. 4.7.5.3 Certificate / Component Types
        4. 4.7.5.4 Extended Boot Encryption Info
        5. 4.7.5.5 Component Ordering
        6. 4.7.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.7.5.7 Device Type and Extended Boot Extension
      6. 4.7.6 Generating X.509 Certificates
        1. 4.7.6.1 Key Generation
          1. 4.7.6.1.1 Degenerate RSA Keys
        2. 4.7.6.2 Configuration Script
        3. 4.7.6.3 Image Data
    8. 4.8 Boot Memory Maps
      1. 4.8.1 Memory Layout/MPU
      2. 4.8.2 Global Memory Addresses Used by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0
        1. 5.1.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Overview
        2. 5.1.1.2 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Integration
        3. 5.1.1.3 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.1.3.1 Description for CTRL_MMR0 and PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.1.3.1.1 Pad Configuration Registers
            2. 5.1.1.3.1.2 Kick Protection Registers
            3. 5.1.1.3.1.3 Proxy Addressing Registers
            4. 5.1.1.3.1.4 CTRL_MMR0 Module Interrupts
            5. 5.1.1.3.1.5 EHRPWM/EQEP Control and Status Registers
            6. 5.1.1.3.1.6 Clock Muxing and Division Registers
            7. 5.1.1.3.1.7 Ethernet Port Operation Control Registers
            8. 5.1.1.3.1.8 DDRSS Dynamic Frequency Change Registers
            9. 5.1.1.3.1.9 Device Feature Registers
        4. 5.1.1.4 Pad Configuration Registers
          1. 5.1.1.4.1 Pad Configuration Register Functional Description
          2. 5.1.1.4.2 Pad Configuration Ball Names
          3. 5.1.1.4.3 PADCFG_CTRL0_CFG0 Registers
        5. 5.1.1.5 CTRL_MMR0 Registers
        6. 5.1.1.6 MAIN_SEC_MMR0_CFG2 Registers
        7. 5.1.1.7 MAIN_SEC_MMR0_CFG0 Registers
      2. 5.1.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0
        1. 5.1.2.1 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.2.3.1.1 Pad Configuration Registers
            2. 5.1.2.3.1.2 Kick Protection Registers
            3. 5.1.2.3.1.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Module Interrupts
            4. 5.1.2.3.1.4 Clock Muxing and Division Registers
            5. 5.1.2.3.1.5 I/O Debounce Control Registers
            6. 5.1.2.3.1.6 PRG Related Registers
            7. 5.1.2.3.1.7 POK Module Registers
        4. 5.1.2.4 MCU_PADCFG_CTRL0_CFG0 Registers
        5. 5.1.2.5 MCU_CTRL_MMR0 Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power System Modules
          1. 5.2.2.1.1 Power OK (POK) Modules
            1. 5.2.2.1.1.1 Configuration Registers
          2. 5.2.2.1.2 Power on Reset (POR) Module
            1. 5.2.2.1.2.1 POR Overview
            2. 5.2.2.1.2.2 POR Integration
          3. 5.2.2.1.3 PoR/Reset Generator (PRG) Modules
            1. 5.2.2.1.3.1 PRG Overview
          4. 5.2.2.1.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.1.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.1.5.1 VTM Overview
              1. 5.2.2.1.5.1.1 VTM Features
              2. 5.2.2.1.5.1.2 VTM Not Supported Features
            2. 5.2.2.1.5.2 VTM Functional Description
              1. 5.2.2.1.5.2.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.1.5.2.1.1 10-bit Temperature Values Versus Temperature
          6. 5.2.2.1.6 Integrated Low-dropout Regulator (LDO)
            1. 5.2.2.1.6.1 SDIO LDO Overview
        2. 5.2.2.2 Power Control Modules
          1. 5.2.2.2.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.2.1.1 PSC Terminology
            2. 5.2.2.2.1.2 PSC Features
            3. 5.2.2.2.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.2.1.3.1 Device Power-Management Layout
            4. 5.2.2.2.1.4 PSC: Executing State Transitions
              1. 5.2.2.2.1.4.1 Power Domain State Transitions
              2. 5.2.2.2.1.4.2 Module State Transitions
              3. 5.2.2.2.1.4.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.2.1.4.4 Recommendations for Power Domain/Module Sequencing
            5. 5.2.2.2.1.5 LPSC Dependencies Overview
          2. 5.2.2.2.2 DMSC-L Power Management Overview
            1. 5.2.2.2.2.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Device Power States and Transitions
      4. 5.2.4 Thermal Management
      5. 5.2.5 Power Registers
        1. 5.2.5.1 VTM Registers
        2. 5.2.5.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Overview
        1. 5.3.1.1 MAIN Domain Supported Resets
        2. 5.3.1.2 MCU Domain Supported Resets
        3. 5.3.1.3 Reset Terminology
        4. 5.3.1.4 Reset Architecture
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
        1. 5.3.3.1 Reset Source Status Registers
        2. 5.3.3.2 MCU_RESETSTATz Status Pin
        3. 5.3.3.3 MCU_SAFETY_ERRORn Status Pin
        4. 5.3.3.4 MAIN_RESETSTATz Status Pin
        5. 5.3.3.5 MAIN_PORz_OUT Status Pin
      4. 5.3.4 Reset Controls
        1. 5.3.4.1 Reset Control Registers
        2. 5.3.4.2 Reset Isolation
      5. 5.3.5 Reset Details
        1. 5.3.5.1 POR Resets
          1. 5.3.5.1.1 SW_MAIN_PORz Reset
          2. 5.3.5.1.2 MCU_PORz Reset
        2. 5.3.5.2 Warm Resets
          1. 5.3.5.2.1 MAIN Domain Warm Reset Sequence Flow
          2. 5.3.5.2.2 MAIN_RESETz_REQ Reset
          3. 5.3.5.2.3 SW_MAIN_WARMRSTz Reset
          4. 5.3.5.2.4 MCU_RESETz Reset
          5. 5.3.5.2.5 SW_MCU_WARMRSTz Reset
        3. 5.3.5.3 DMSC-L Resets
          1. 5.3.5.3.1 DMSC_COLD_OUT_RST_n MAIN Reset
          2. 5.3.5.3.2 DMSC_WARM_OUT_RST_n MAIN Reset
          3. 5.3.5.3.3 DMSC_COLD_OUT_RST_n MCU Reset
        4. 5.3.5.4 VTM Thermal Alert Reset
        5. 5.3.5.5 MAIN ESM_ERRORz Reset
        6. 5.3.5.6 MCU ESM_ERRORz Reset
        7. 5.3.5.7 Reset - High Heating Value (HHV)
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 1800
          3. 5.4.3.1.3 OBSCLK0 Pin
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillator with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 MCU Domain PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRACF Type Output Clocks
              2. 5.4.5.4.1.2.2 PLL Lock
              3. 5.4.5.4.1.2.3 HSDIVIDER
              4. 5.4.5.4.1.2.4 ICG Module
              5. 5.4.5.4.1.2.5 PLL Power Down
              6. 5.4.5.4.1.2.6 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Clocking Registers
        1. 5.4.6.1 PLLCTRL0 Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 MCU_PLL0_CFG Registers
  8. 6 Processors and Accelerators
    1. 6.1 Arm Cortex-A53 Subsystem (A53SS)
      1. 6.1.1 A53SS Overview
        1. 6.1.1.1 A53SS Introduction
        2. 6.1.1.2 A53SS Features
      2. 6.1.2 A53SS Integration
      3. 6.1.3 A53SS Functional Description
        1. 6.1.3.1  A53SS Block Diagram
        2. 6.1.3.2  Arm Cortex-A53 Cluster
        3. 6.1.3.3  A53SS Interfaces and Async Bridges
        4. 6.1.3.4  A53SS Interrupts
          1. 6.1.3.4.1 A53SS Interrupt Inputs
          2. 6.1.3.4.2 A53SS Interrupt Outputs
        5. 6.1.3.5  A53SS Power Management and Clocking
          1. 6.1.3.5.1 A53SS Power Management
          2. 6.1.3.5.2 A53SS Clocking
        6. 6.1.3.6  A53SS Debug
        7. 6.1.3.7  A53SS Global and Debug Timestamps
        8. 6.1.3.8  A53SS Watchdog
        9. 6.1.3.9  A53SS Functional Safety - ECC Error Injection Support
          1. 6.1.3.9.1 A53 ECC Aggregators During Low Power States
          2. 6.1.3.9.2 Auto-initialization of Memories
          3. 6.1.3.9.3 A53 SRAM Safety
          4. 6.1.3.9.4 A53 SRAM ECC Aggregator Configurations
        10. 6.1.3.10 A53SS Boot
        11. 6.1.3.11 A53SS Interprocessor Communication
      4. 6.1.4 A53SS Registers
        1. 6.1.4.1 A53SS Registers
    2. 6.2 Arm Cortex R5F Subsystem (R5FSS)
      1. 6.2.1 R5FSS Overview
        1. 6.2.1.1 R5FSS Features
        2. 6.2.1.2 R5FSS Not Supported Features
      2. 6.2.2 R5FSS Integration
        1. 6.2.2.1 R5FSS Integration in MAIN Domain
      3. 6.2.3 R5FSS Functional Description
        1. 6.2.3.1  R5FSS Block Diagram
        2. 6.2.3.2  R5FSS Cortex-R5F Core
          1. 6.2.3.2.1 L1 Caches
          2. 6.2.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.2.3.2.3 R5FSS Special Signals
        3. 6.2.3.3  R5FSS Interfaces
          1. 6.2.3.3.1 Initiator Interfaces
          2. 6.2.3.3.2 Target Interfaces
        4. 6.2.3.4  R5FSS Power, Clocking and Reset
          1. 6.2.3.4.1 R5FSS Power
          2. 6.2.3.4.2 R5FSS Clocking
          3. 6.2.3.4.3 R5FSS Reset
        5. 6.2.3.5  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.2.3.5.1 VIM Overview
          2. 6.2.3.5.2 VIM Interrupt Inputs
          3. 6.2.3.5.3 VIM Interrupt Outputs
          4. 6.2.3.5.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.2.3.5.5 VIM Interrupt Prioritization
          6. 6.2.3.5.6 VIM ECC Support
          7. 6.2.3.5.7 VIM IDLE State
          8. 6.2.3.5.8 VIM Interrupt Handling
            1. 6.2.3.5.8.1 Servicing IRQ Through Vector Interface
            2. 6.2.3.5.8.2 Servicing IRQ Through MMR Interface
            3. 6.2.3.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.2.3.5.8.4 Servicing FIQ
            5. 6.2.3.5.8.5 Servicing FIQ (Alternative)
        6. 6.2.3.6  R5FSS Region Address Translation (RAT)
          1. 6.2.3.6.1 R5FSS Usage
          2. 6.2.3.6.2 RAT Function
          3. 6.2.3.6.3 How to use RAT Block in R5
          4. 6.2.3.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
        7. 6.2.3.7  R5FSS ECC Support
        8. 6.2.3.8  R5FSS Memory View
        9. 6.2.3.9  R5FSS Interrupts
        10. 6.2.3.10 R5FSS Debug and Trace
        11. 6.2.3.11 R5FSS Boot Options
        12. 6.2.3.12 R5FSS Core Memory ECC Events
      4. 6.2.4 R5FSS Registers
        1. 6.2.4.1 R5FSS_MPIDR Register
        2. 6.2.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.2.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.2.4.4 R5FSS_VIM Registers
        5. 6.2.4.5 R5FSS_RAT Registers
        6. 6.2.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
    3. 6.3 Cortex-M4F Subsystem (MCU_M4FSS)
      1. 6.3.1 MCU_M4FSS Overview
        1. 6.3.1.1 MCU_M4FSS Features
        2. 6.3.1.2 MCU_M4FSS Not Supported Features
      2. 6.3.2 MCU_M4FSS Integration
      3. 6.3.3 MCU_M4FSS Functional Description
        1. 6.3.3.1  MCU_M4FSS Block Diagram
        2. 6.3.3.2  MCU_M4FSS Processor
        3. 6.3.3.3  MCU_M4FSS Internal RAMs
        4. 6.3.3.4  MCU_M4FSS Interfaces
        5. 6.3.3.5  MCU_M4FSS Power, Clocking and Reset
          1. 6.3.3.5.1 MCU_M4FSS Power
          2. 6.3.3.5.2 MCU_M4FSS Clocking
          3. 6.3.3.5.3 MCU_M4FSS Reset
        6. 6.3.3.6  MCU_M4FSS Memory View
        7. 6.3.3.7  MCU_M4FSS RAT
          1. 6.3.3.7.1 Why RAT is needed for M4F
          2. 6.3.3.7.2 RAT Function
          3. 6.3.3.7.3 How to use RAT Block in Blazar M4F
        8. 6.3.3.8  MCU_M4FSS ECC Support
        9. 6.3.3.9  MCU_M4FSS Interrupts
        10. 6.3.3.10 MCU_M4FSS Debug and Trace
        11. 6.3.3.11 MCU_M4FSS Time Sync
        12. 6.3.3.12 MCU_M4FSS SysTick
        13. 6.3.3.13 MCU_M4FSS Initialization
      4. 6.3.4 MCU_M4FSS Registers
        1. 6.3.4.1 M4FSS_RAT_0 Registers
          1. 6.3.4.1.1  RAT__CFG__MMRS_M4FSS_RAT_0_PID Registers
          2. 6.3.4.1.2  RAT__CFG__MMRS_M4FSS_RAT_0_CONFIG Registers
          3. 6.3.4.1.3  RAT__CFG__MMRS_M4FSS_RAT_0_DESTINATION_ID Registers
          4. 6.3.4.1.4  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_CONTROL Registers
          5. 6.3.4.1.5  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER0 Registers
          6. 6.3.4.1.6  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER1 Registers
          7. 6.3.4.1.7  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA0 Registers
          8. 6.3.4.1.8  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA1 Registers
          9. 6.3.4.1.9  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA2 Registers
          10. 6.3.4.1.10 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA3 Registers
          11. 6.3.4.1.11 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_SET Registers
          12. 6.3.4.1.12 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_CLEAR Registers
          13. 6.3.4.1.13 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_SET Registers
          14. 6.3.4.1.14 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_CLEAR Registers
          15. 6.3.4.1.15 RAT__CFG__MMRS_M4FSS_RAT_0_EOI_REG Registers
          16. 6.3.4.1.16 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_CTRL_J Registers
          17. 6.3.4.1.17 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_BASE_J Registers
          18. 6.3.4.1.18 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_L_J Registers
          19. 6.3.4.1.19 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_U_J Registers
          20. 6.3.4.1.20 Access Table
    4. 6.4 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      1. 6.4.1  PRU_ICSSG Overview
        1. 6.4.1.1 PRU_ICSSG Key Features
        2. 6.4.1.2 Not Supported Features
      2. 6.4.2  PRU_ICSSG Environment
        1. 6.4.2.1 PRU_ICSSG Internal Pinmux
          1.        PRU_ICSSG I/O Signals
        2. 6.4.2.2 PRU_ICSSG Fast GPIO pins
      3. 6.4.3  PRU_ICSSG Integration
        1.       PRU_ICSSG Clocks
      4. 6.4.4  PRU_ICSSG Top Level Resources Functional Description
        1. 6.4.4.1 PRU_ICSSG Reset Management
        2. 6.4.4.2 PRU_ICSSG Power and Clock Management
          1. 6.4.4.2.1 PRU_ICSSG CORE Clock Generation
          2. 6.4.4.2.2 PRU_ICSSG Idle State
          3. 6.4.4.2.3 PRU_ICSSG Protect
          4. 6.4.4.2.4 Module Clock Configurations at PRU_ICSSG Top Level
        3. 6.4.4.3 Other PRU_ICSSG Module Functional Registers at Subsystem Level
        4. 6.4.4.4 PRU_ICSSG Memory Maps
          1. 6.4.4.4.1 PRU_ICSSG Local Memory Map
            1. 6.4.4.4.1.1 PRU_ICSSG Local Instruction Memory Map
            2. 6.4.4.4.1.2 PRU_ICSSG Local Data Memory Map
          2. 6.4.4.4.2 PRU_ICSSG Global Memory Map
      5. 6.4.5  PRU_ICSSG PRU Cores
        1. 6.4.5.1 PRU Cores Overview
        2. 6.4.5.2 PRU Cores Functional Description
          1. 6.4.5.2.1 PRUs Constant Table
          2. 6.4.5.2.2 PRU Module Interface
            1. 6.4.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 6.4.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 6.4.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 6.4.5.2.2.3.1 PRU EGPIs Direct Input
              2. 6.4.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 6.4.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 6.4.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 6.4.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 6.4.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 6.4.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 4.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 6.4.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 6.4.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 6.4.5.2.2.3.5.3 Sigma Delta Description
                4. 6.4.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 6.4.5.2.2.3.6 Three Channel Peripheral Interface
                1. 6.4.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 6.4.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 6.4.5.2.2.3.6.3 Clock Generation
                  1. 4.5.2.2.3.6.3.1 Configuration
                  2. 4.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 4.5.2.2.3.6.3.3 Stop Conditions
                4. 6.4.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 4.5.2.2.3.6.4.1 Clock Generation
                  2. 4.5.2.2.3.6.4.2 TX - Single Shot
                  3. 4.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 4.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 6.4.5.3 PRU_ICSSG RAM Index Allocation
      6. 6.4.6  PRU_ICSSG Broadside Accelerators
        1. 6.4.6.1 PRU_ICSSG Broadside Accelerators Overview
        2. 6.4.6.2 PRU_ICSSG Data Processing Accelerators Functional
          1. 6.4.6.2.1  PRU Multiplier with Accumulation (MPY/MAC)
            1. 6.4.6.2.1.1 PRU MAC Operations
              1. 6.4.6.2.1.1.1 PRU versus MAC Interface
              2. 6.4.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 6.4.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 6.4.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 6.4.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 6.4.6.2.2  PRU CRC16/32 Module
            1. 6.4.6.2.2.1 PRU and CRC16/32 Interface
            2. 6.4.6.2.2.2 CRC Programming Model
            3. 6.4.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 6.4.6.2.3  PRU_ICSSG Scratch Pad Memory
            1. 6.4.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 6.4.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 6.4.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 6.4.6.2.3.2.2 Scratch Pad Operations Examples
          4. 6.4.6.2.4  PRU_ICSSG IPC Scratch Pad Memory
          5. 6.4.6.2.5  PRU_ICSSG Broadside (BS) RAM
            1. 6.4.6.2.5.1 Programming the BS RAM
          6. 6.4.6.2.6  PRU_ICSSG SUM32 Hardware Accelerator
          7. 6.4.6.2.7  PRU_ICSSG Byte Swap (BSWAP)
            1. 6.4.6.2.7.1 Byte Order Swap Function
            2. 6.4.6.2.7.2 4_8 Function
            3. 6.4.6.2.7.3 4_16 Function
          8. 6.4.6.2.8  PRU_ICSSG Task Manager
            1. 6.4.6.2.8.1 Task Manager General Purpose Mode
              1. 6.4.6.2.8.1.1 Tasks and Sub-tasks
              2. 6.4.6.2.8.1.2 Task Manager Hardware Context Switching
              3. 6.4.6.2.8.1.3 Task Manager Programming Guide
            2. 6.4.6.2.8.2 Task Manager RX_TX Mode
              1. 6.4.6.2.8.2.1 RX_TX Task Manager Features
              2. 6.4.6.2.8.2.2 Tasks and Sub-tasks
          9. 6.4.6.2.9  PRU_ICSSG Spinlock
            1. 6.4.6.2.9.1 PRU0/1 and RTU_PRU0/1 Spinlock Interface
          10. 6.4.6.2.10 PRU_ICSSG Filter Data Base (FDB)
            1. 6.4.6.2.10.1 FDB Modes of operation
              1. 6.4.6.2.10.1.1 FDB LUT: Hardware operation (HSR Disabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 0h)
              2. 6.4.6.2.10.1.2 FDB LUT: Hardware operation (HSR Enabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 1h)
              3. 6.4.6.2.10.1.3 8KB/16KB Generic broadside RAM mode of operation
                1. 6.4.6.2.10.1.3.1 Broadside (BS) Mapping
              4. 6.4.6.2.10.1.4 FDB General purpose compare mode operation
        3. 6.4.6.3 PRU_ICSSG Data Movement Accelerators Functional
          1. 6.4.6.3.1 PRU_ICSSG XFR2VBUS Hardware Accelerator
            1. 6.4.6.3.1.1 Blocking Conditions
            2. 6.4.6.3.1.2 Read Operation with Auto Disabled
            3. 6.4.6.3.1.3 Read Operation with Auto Enabled
            4. 6.4.6.3.1.4 Write Operation with Auto Disabled
            5. 6.4.6.3.1.5 RTU_PRU/ PRU to XFR2VBUS Interface
            6. 6.4.6.3.1.6 XFR2VBUS Programming Model
          2. 6.4.6.3.2 PRU_ICSSG XFRDMA Functional Operation
            1. 6.4.6.3.2.1 XFRDMA: XFR Bus
              1. 6.4.6.3.2.1.1 XFRDMA: XFR Status
              2. 6.4.6.3.2.1.2 XFRDMA: XFR Bus XOUT
              3. 6.4.6.3.2.1.3 XFRDMA: XFR Bus XOUXFRDMA Functional Operation T Alignment
              4. 6.4.6.3.2.1.4 XFRDMA: XFR Bus XIN
                1. 6.4.6.3.2.1.4.1 XFRDMA: XFR Bus XIN Alignment
            2. 6.4.6.3.2.2 XFRDMA: PSI-L Bus
              1. 6.4.6.3.2.2.1 PRU XFRPSI Mapping
            3. 6.4.6.3.2.3 XFRDMA: Temporary FIFOs
              1. 6.4.6.3.2.3.1 XFRDMA: FIFO Stalls
          3. 6.4.6.3.3 PRU_ICSSG XFR2TR Ring Accelerator
            1. 6.4.6.3.3.1 XFR2TR Programming Model
      7. 6.4.7  PRU_ICSSG Local INTC
        1. 6.4.7.1 PRU_ICSSG Interrupt Controller Functional Description
          1. 6.4.7.1.1 PRU_ICSSG Interrupt Controller Events
          2. 6.4.7.1.2 PRU_ICSSG Interrupt Controller System Events Flow
            1. 6.4.7.1.2.1 PRU_ICSSG Interrupt Processing
              1. 6.4.7.1.2.1.1 PRU_ICSSG Interrupt Enabling
            2. 6.4.7.1.2.2 PRU_ICSSG Interrupt Status Checking
            3. 6.4.7.1.2.3 PRU_ICSSG Interrupt Channel Mapping
              1. 6.4.7.1.2.3.1 PRU_ICSSG Host Interrupt Mapping
              2. 6.4.7.1.2.3.2 PRU_ICSSG Interrupt Prioritization
            4. 6.4.7.1.2.4 PRU_ICSSG Interrupt Nesting
            5. 6.4.7.1.2.5 PRU_ICSSG Interrupt Status Clearing
          3. 6.4.7.1.3 PRU_ICSSG Interrupt Disabling
        2. 6.4.7.2 PRU_ICSSG Interrupt Controller Basic Programming Model
        3. 6.4.7.3 PRU_ICSSG Interrupt Requests Mapping
      8. 6.4.8  PRU_ICSSG UART Module
        1. 6.4.8.1 PRU_ICSSG UART Overview
        2. 6.4.8.2 PRU_ICSSG UART Environment
          1. 6.4.8.2.1 PRU_ICSSG UART Pin Multiplexing
          2. 6.4.8.2.2 PRU_ICSSG UART Signal Descriptions
          3. 6.4.8.2.3 PRU_ICSSG UART Protocol Description and Data Format
            1. 6.4.8.2.3.1 PRU_ICSSG UART Transmission Protocol
            2. 6.4.8.2.3.2 PRU_ICSSG UART Reception Protocol
            3. 6.4.8.2.3.3 PRU_ICSSG UART Data Format
              1. 6.4.8.2.3.3.1 Frame Formatting
          4. 6.4.8.2.4 PRU_ICSSG UART Clock Generation and Control
        3. 6.4.8.3 PRU_ICSSG UART Functional Description
          1. 6.4.8.3.1 PRU_ICSSG UART Functional Block Diagram
          2. 6.4.8.3.2 PRU_ICSSG UART Reset Considerations
            1. 6.4.8.3.2.1 PRU_ICSSG UART Software Reset Considerations
            2. 6.4.8.3.2.2 PRU_ICSSG UART Hardware Reset Considerations
          3. 6.4.8.3.3 PRU_ICSSG UART Power Management
          4. 6.4.8.3.4 PRU_ICSSG UART Interrupt Support
            1. 6.4.8.3.4.1 PRU_ICSSG UART Interrupt Events and Requests
            2. 6.4.8.3.4.2 PRU_ICSSG UART Interrupt Multiplexing
          5. 6.4.8.3.5 2134
          6. 6.4.8.3.6 PRU_ICSSG UART DMA Event Support
          7. 6.4.8.3.7 PRU_ICSSG UART Operations
            1. 6.4.8.3.7.1 PRU_ICSSG UART FIFO Modes
              1. 6.4.8.3.7.1.1 PRU_ICSSG UART FIFO Interrupt Mode
              2. 6.4.8.3.7.1.2 PRU_ICSSG UART FIFO Poll Mode
            2. 6.4.8.3.7.2 PRU_ICSSG UART Autoflow Control
              1. 6.4.8.3.7.2.1 PRU_ICSSG UART Signal UART0_RTS Behavior
              2. 6.4.8.3.7.2.2 PRU_ICSSG UART Signal UART0_CTS Behavior
            3. 6.4.8.3.7.3 PRU_ICSSG UART Loopback Control
          8. 6.4.8.3.8 PRU_ICSSG UART Emulation Considerations
          9. 6.4.8.3.9 PRU_ICSSG UART Exception Processing
            1. 6.4.8.3.9.1 PRU_ICSSG UART Divisor Latch Not Programmed
            2. 6.4.8.3.9.2 Changing Operating Mode During Busy Serial Communication of PRU_ICSSG UART
      9. 6.4.9  PRU_ICSSG ECAP Module
        1. 6.4.9.1 PRU_ICSSG ECAP Functional Description
      10. 6.4.10 PRU_ICSSG PWM Module
        1. 6.4.10.1 PRU_ICSSG PWM Supported Features
        2. 6.4.10.2 PRU_ICSSG PWM States Overview
        3. 6.4.10.3 PRU_ICSSG PWM Trip State Logic
        4. 6.4.10.4 PRU_ICSSG PWM Glitch Filter
      11. 6.4.11 PRU_ICSSG MII_G_RT Module
        1. 6.4.11.1 PRU_ICSSG MII_G_RT Introduction
          1. 6.4.11.1.1 PRU_ICSSG MII_G_RT Features
          2. 6.4.11.1.2 Unsupported Features
          3. 6.4.11.1.3 PRU_ICSSG MII_G_RT Block Diagram
        2. 6.4.11.2 MII_G_RT Functional Description
          1. 6.4.11.2.1 MII_G_RT Data Path Configuration
            1. 6.4.11.2.1.1 Auto-forward with Optional PRU Snoop
            2. 6.4.11.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 6.4.11.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 6.4.11.2.2 MII_G_RT Definition and Terms
            1. 6.4.11.2.2.1 MII_G_RT Data Frame Structure
            2. 6.4.11.2.2.2 PRU R30 and R31
            3. 6.4.11.2.2.3 RX and TX L1 FIFO Data Movement
            4. 6.4.11.2.2.4 Receive CRC Computation
            5. 6.4.11.2.2.5 Transmit CRC Computation
            6. 6.4.11.2.2.6 Transmit CRC Computation for fragmented frames
          3. 6.4.11.2.3 RX MII Interface
            1. 6.4.11.2.3.1 RX MII Receive Data Latch
            2. 6.4.11.2.3.2 RX MII Start of Frame Detection
            3. 6.4.11.2.3.3 CRC Error Detection
            4. 6.4.11.2.3.4 RX Error Detection and Action
            5. 6.4.11.2.3.5 RX Data Path Options to PRU
            6. 6.4.11.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 6.4.11.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 6.4.11.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_G_CFG[2] RX_L2_G_EN= 0h)
              2. 6.4.11.2.3.7.2 2181
              3. 6.4.11.2.3.7.3 RX L2 Status for IET Type 1/Type 2 (when MII_G_RT_ICSS_G_CFG[2] RX_L2_G_EN = 1h)
              4. 6.4.11.2.3.7.4 2183
              5. 6.4.11.2.3.7.5 Broadside Stitch FIFO
              6. 6.4.11.2.3.7.6 MII_G_RT RX Classifier
                1. 6.4.11.2.3.7.6.1 RX Rate Counter Block
                2. 6.4.11.2.3.7.6.2 RX Rate Hit Mapping
                3. 6.4.11.2.3.7.6.3 Traffic Class Selector Block
                4. 6.4.11.2.3.7.6.4 PRU_ICSSG RX L2 Filter Block
                  1. 4.11.2.3.7.6.4.1 PRU_ICSSG RX L2 Filter Operation
                  2. 4.11.2.3.7.6.4.2 PRU_ICSSG RX L2 Filter - Type 1 (MAC Filter) Operation
                  3. 4.11.2.3.7.6.4.3 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Operation
                  4. 4.11.2.3.7.6.4.4 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Auto Restart operation
                  5. 4.11.2.3.7.6.4.5 RX SA Hash
                  6. 4.11.2.3.7.6.4.6 RX Connection Hash
          4. 6.4.11.2.4 PRU_ICSSG TX MII Interface
            1. 6.4.11.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 6.4.11.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 6.4.11.2.4.1.1.1 TX L2 FIFO Features
                2. 6.4.11.2.4.1.1.2 2200
                3. 6.4.11.2.4.1.1.3 TX Insertion
                4. 6.4.11.2.4.1.1.4 TX Preemption
                  1. 4.11.2.4.1.1.4.1 TX Preemption Programming Model
              2. 6.4.11.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 6.4.11.2.5 PRU R31 Command Interface
          6. 6.4.11.2.6 Other Configuration Options
            1. 6.4.11.2.6.1 Nibble and Byte Order
            2. 6.4.11.2.6.2 MII_G_RT Preamble Source
            3. 6.4.11.2.6.3 PRU and MII Port Multiplexer
              1. 6.4.11.2.6.3.1 Receive Multiplexer
              2. 6.4.11.2.6.3.2 Transmit Multiplexer
            4. 6.4.11.2.6.4 RX L2 Scratch Pad
        3. 6.4.11.3 PRU_ICSSG PA_STATS Module
          1. 6.4.11.3.1 Statistics Page
          2. 6.4.11.3.2 Statistics Collection Modes
            1. 6.4.11.3.2.1 Manual Read Mode
          3. 6.4.11.3.3 Clock Stop
      12. 6.4.12 PRU_ICSSG MII MDIO Module
        1. 6.4.12.1 PRU_ICSSG MII MDIO Overview
        2. 6.4.12.2 PRU_ICSSG MII MDIO Functional Description
          1. 6.4.12.2.1 MDIO Clause 22 Frame Formats
            1. 6.4.12.2.1.1 PRU-ICSSG MDIO Control and Interface Signals
          2. 6.4.12.2.2 MDIO Clause 45 Frame Formats
          3. 6.4.12.2.3 PRU_ICSSG MII MDIO Interractions
          4. 6.4.12.2.4 PRU_ICSSG MII MDIO Interrupts
            1. 6.4.12.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 6.4.12.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 6.4.12.2.5 Manual Mode
        3. 6.4.12.3 PRU_ICSSG MII MDIO Receive/Transmit Frame Host Software Interface
      13. 6.4.13 PRU_ICSSG IEP
        1. 6.4.13.1 PRU_ICSSG IEP Overview
        2. 6.4.13.2 PRU_ICSSG IEP Functional Description
          1. 6.4.13.2.1 PRU_ICSSG IEP Clock Generation
          2. 6.4.13.2.2 PRU_ICSSG IEP Timer
            1. 6.4.13.2.2.1 PRU_ICSSG IEP Timer Features
          3. 6.4.13.2.3 32-Bit Shadow Mode
          4. 6.4.13.2.4 PRU_ICSSG IEP Timer Basic Programming Sequence
          5. 6.4.13.2.5 Industrial Ethernet Mapping
          6. 6.4.13.2.6 PRU_ICSSG IEP Sync0/Sync1 Module
            1. 6.4.13.2.6.1 PRU_ICSSG IEP Sync0/Sync1 Features
            2. 6.4.13.2.6.2 PRU_ICSSG IEP Sync0/Sync1 Generation Modes
          7. 6.4.13.2.7 PRU_ICSSG IEP WatchDog
          8. 6.4.13.2.8 PRU_ICSSG IEP DIGIO
            1. 6.4.13.2.8.1 PRU_ICSSG IEP DIGIO Features
            2. 6.4.13.2.8.2 2245
            3. 6.4.13.2.8.3 PRU_ICSSG IEP DIGIO Block Diagrams
            4. 6.4.13.2.8.4 PRU_ICSSG IEP Basic Programming Model
      14. 6.4.14 PRU_ICSSG Registers
        1. 6.4.14.1  PRU_ICSSG PRU_CTRL, RTU_PRU_CTRL, and TX_PRU_CTRL Registers
        2. 6.4.14.2  PRU_ICSSG PRU_DEBUG, RTU_PRU_DEBUG, and TX_PRU_DEBUG Registers
        3. 6.4.14.3  PRU_ICSSG_ECC_AGGR Registers
        4. 6.4.14.4  PRU_ICSSG_DDRAM Registers
        5. 6.4.14.5  PRU_ICSSG_CFG Registers
        6. 6.4.14.6  PRU_ECAP_ECAP0 Registers
        7. 6.4.14.7  PRU_ICSS_INTC_INTC Registers
        8. 6.4.14.8  PRU_UART_UART0 Registers
        9. 6.4.14.9  PRU_IEP_IEP Registers
        10. 6.4.14.10 PRU_MDIO_MDIO Registers
        11. 6.4.14.11 PRU_MII_RT_MII_RT Registers
        12. 6.4.14.12 PRU_MII_G_RT_MII_G_RT Registers
        13. 6.4.14.13 PRU_ICSSG_PA_STAT Registers
        14. 6.4.14.14 PRU_ICSSG_PA_STAT_QSTAT Registers
        15. 6.4.14.15 PRU_ICSSG_PA_STAT_CSTAT Registers
        16. 6.4.14.16 PRU_PROT_PROTECT Registers
        17. 6.4.14.17 PRU_RAT_SLICE_RAT_SLICE Registers
        18. 6.4.14.18 PRU_TASKS_MGR_TASKS_MGR_PRU_RTU_TX Registers
        19. 6.4.14.19 PRU_ICSSG_RAM Registers
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
      5. 7.1.5 Mailbox Registers
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
      5. 7.2.5 Spinlock Registers
  10. 8 Memory Controllers
    1. 8.1 DDR Subsystem (DDRSS)
      1. 8.1.1 DDRSS Overview
        1. 8.1.1.1 DDRSS Not Supported Features
      2. 8.1.2 DDRSS Environment
      3. 8.1.3 DDRSS Integration
        1. 8.1.3.1 DDRSS Integration in MAIN Domain
      4. 8.1.4 DDRSS Functional Description
        1. 8.1.4.1 Class of Service (CoS)
        2. 8.1.4.2 AXI Write Data All-Strobes
        3. 8.1.4.3 Inline ECC for SDRAM Data
          1. 8.1.4.3.1 ECC Cache
          2. 8.1.4.3.2 ECC Cache Flush
          3. 8.1.4.3.3 ECC Statistics
        4. 8.1.4.4 Address Alias Prevention
        5. 8.1.4.5 AXI Bus Timeout
        6. 8.1.4.6 DDRSS Interrupts
        7. 8.1.4.7 DDRSS Memory Regions
        8. 8.1.4.8 DDRSS Dynamic Frequency Change Interface
        9. 8.1.4.9 DDR Controller Functional Description
          1. 8.1.4.9.1 DDR PHY Interface (DFI)
          2. 8.1.4.9.2 Command Queue
            1. 8.1.4.9.2.1 Placement Logic
            2. 8.1.4.9.2.2 Command Selection Logic
          3. 8.1.4.9.3 Transaction Processing
          4. 8.1.4.9.4 Paging Policy
          5. 8.1.4.9.5 DDR Controller Initialization
      5. 8.1.5 DDR16SS Registers
        1. 8.1.5.1    REGS__SS_CFG__SSCFG_DDR16SS_SS_ID_REV_REG Registers
        2. 8.1.5.2    REGS__SS_CFG__SSCFG_DDR16SS_SS_CTL_REG Registers
        3. 8.1.5.3    REGS__SS_CFG__SSCFG_DDR16SS_V2A_CTL_REG Registers
        4. 8.1.5.4    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_MAT_REG Registers
        5. 8.1.5.5    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_MAT_REG Registers
        6. 8.1.5.6    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_MAT_REG Registers
        7. 8.1.5.7    REGS__SS_CFG__SSCFG_DDR16SS_V2A_DEF_PRI_MAP_REG Registers
        8. 8.1.5.8    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_PRI_MAP_REG Registers
        9. 8.1.5.9    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_PRI_MAP_REG Registers
        10. 8.1.5.10   REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_PRI_MAP_REG Registers
        11. 8.1.5.11   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG1_REG Registers
        12. 8.1.5.12   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG2_REG Registers
        13. 8.1.5.13   REGS__SS_CFG__SSCFG_DDR16SS_V2A_BUS_TO Registers
        14. 8.1.5.14   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_RAW_REG Registers
        15. 8.1.5.15   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_STAT_REG Registers
        16. 8.1.5.16   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_SET_REG Registers
        17. 8.1.5.17   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_CLR_REG Registers
        18. 8.1.5.18   REGS__SS_CFG__SSCFG_DDR16SS_V2A_EOI_REG Registers
        19. 8.1.5.19   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT_SEL_REG Registers
        20. 8.1.5.20   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT1_REG Registers
        21. 8.1.5.21   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT2_REG Registers
        22. 8.1.5.22   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT3_REG Registers
        23. 8.1.5.23   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT4_REG Registers
        24. 8.1.5.24   REGS__SS_CFG__SSCFG_DDR16SS_ECC_CTRL_REG Registers
        25. 8.1.5.25   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_INDX_REG Registers
        26. 8.1.5.26   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_VAL_REG Registers
        27. 8.1.5.27   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_STR_ADDR_REG Registers
        28. 8.1.5.28   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_END_ADDR_REG Registers
        29. 8.1.5.29   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_STR_ADDR_REG Registers
        30. 8.1.5.30   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_END_ADDR_REG Registers
        31. 8.1.5.31   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_STR_ADDR_REG Registers
        32. 8.1.5.32   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_END_ADDR_REG Registers
        33. 8.1.5.33   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_CNT_REG Registers
        34. 8.1.5.34   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_THRSH_REG Registers
        35. 8.1.5.35   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_ADR_LOG_REG Registers
        36. 8.1.5.36   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_MSK_LOG_REG Registers
        37. 8.1.5.37   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_ADR_LOG_REG Registers
        38. 8.1.5.38   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_MSK_LOG_REG Registers
        39. 8.1.5.39   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL1_REG Registers
        40. 8.1.5.40   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL2_REG Registers
        41. 8.1.5.41   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL3_REG Registers
        42. 8.1.5.42   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL4_REG Registers
        43. 8.1.5.43   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL5_REG Registers
        44. 8.1.5.44   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL6_REG Registers
        45. 8.1.5.45   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL7_REG Registers
        46. 8.1.5.46   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL8_REG Registers
        47. 8.1.5.47   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL9_REG Registers
        48. 8.1.5.48   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL10_REG Registers
        49. 8.1.5.49   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT1_REG Registers
        50. 8.1.5.50   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT2_REG Registers
        51. 8.1.5.51   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_0 Registers
        52. 8.1.5.52   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_1 Registers
        53. 8.1.5.53   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_2 Registers
        54. 8.1.5.54   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_3 Registers
        55. 8.1.5.55   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_4 Registers
        56. 8.1.5.56   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_5 Registers
        57. 8.1.5.57   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_6 Registers
        58. 8.1.5.58   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_7 Registers
        59. 8.1.5.59   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_8 Registers
        60. 8.1.5.60   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_9 Registers
        61. 8.1.5.61   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_10 Registers
        62. 8.1.5.62   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_11 Registers
        63. 8.1.5.63   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_12 Registers
        64. 8.1.5.64   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_13 Registers
        65. 8.1.5.65   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_14 Registers
        66. 8.1.5.66   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_15 Registers
        67. 8.1.5.67   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_16 Registers
        68. 8.1.5.68   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_17 Registers
        69. 8.1.5.69   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_18 Registers
        70. 8.1.5.70   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_19 Registers
        71. 8.1.5.71   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_20 Registers
        72. 8.1.5.72   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_21 Registers
        73. 8.1.5.73   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_22 Registers
        74. 8.1.5.74   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_23 Registers
        75. 8.1.5.75   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_24 Registers
        76. 8.1.5.76   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_25 Registers
        77. 8.1.5.77   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_26 Registers
        78. 8.1.5.78   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_27 Registers
        79. 8.1.5.79   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_28 Registers
        80. 8.1.5.80   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_29 Registers
        81. 8.1.5.81   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_30 Registers
        82. 8.1.5.82   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_31 Registers
        83. 8.1.5.83   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_32 Registers
        84. 8.1.5.84   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_33 Registers
        85. 8.1.5.85   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_34 Registers
        86. 8.1.5.86   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_35 Registers
        87. 8.1.5.87   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_36 Registers
        88. 8.1.5.88   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_37 Registers
        89. 8.1.5.89   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_38 Registers
        90. 8.1.5.90   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_39 Registers
        91. 8.1.5.91   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_40 Registers
        92. 8.1.5.92   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_41 Registers
        93. 8.1.5.93   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_42 Registers
        94. 8.1.5.94   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_43 Registers
        95. 8.1.5.95   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_44 Registers
        96. 8.1.5.96   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_45 Registers
        97. 8.1.5.97   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_46 Registers
        98. 8.1.5.98   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_47 Registers
        99. 8.1.5.99   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_48 Registers
        100. 8.1.5.100  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_49 Registers
        101. 8.1.5.101  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_50 Registers
        102. 8.1.5.102  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_51 Registers
        103. 8.1.5.103  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_52 Registers
        104. 8.1.5.104  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_53 Registers
        105. 8.1.5.105  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_54 Registers
        106. 8.1.5.106  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_55 Registers
        107. 8.1.5.107  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_56 Registers
        108. 8.1.5.108  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_57 Registers
        109. 8.1.5.109  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_58 Registers
        110. 8.1.5.110  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_59 Registers
        111. 8.1.5.111  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_60 Registers
        112. 8.1.5.112  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_61 Registers
        113. 8.1.5.113  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_62 Registers
        114. 8.1.5.114  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_63 Registers
        115. 8.1.5.115  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_64 Registers
        116. 8.1.5.116  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_65 Registers
        117. 8.1.5.117  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_66 Registers
        118. 8.1.5.118  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_67 Registers
        119. 8.1.5.119  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_68 Registers
        120. 8.1.5.120  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_69 Registers
        121. 8.1.5.121  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_70 Registers
        122. 8.1.5.122  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_71 Registers
        123. 8.1.5.123  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_72 Registers
        124. 8.1.5.124  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_73 Registers
        125. 8.1.5.125  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_74 Registers
        126. 8.1.5.126  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_75 Registers
        127. 8.1.5.127  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_76 Registers
        128. 8.1.5.128  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_77 Registers
        129. 8.1.5.129  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_78 Registers
        130. 8.1.5.130  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_79 Registers
        131. 8.1.5.131  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_80 Registers
        132. 8.1.5.132  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_81 Registers
        133. 8.1.5.133  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_82 Registers
        134. 8.1.5.134  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_83 Registers
        135. 8.1.5.135  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_84 Registers
        136. 8.1.5.136  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_85 Registers
        137. 8.1.5.137  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_86 Registers
        138. 8.1.5.138  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_87 Registers
        139. 8.1.5.139  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_88 Registers
        140. 8.1.5.140  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_89 Registers
        141. 8.1.5.141  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_90 Registers
        142. 8.1.5.142  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_91 Registers
        143. 8.1.5.143  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_92 Registers
        144. 8.1.5.144  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_93 Registers
        145. 8.1.5.145  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_94 Registers
        146. 8.1.5.146  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_95 Registers
        147. 8.1.5.147  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_96 Registers
        148. 8.1.5.148  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_97 Registers
        149. 8.1.5.149  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_98 Registers
        150. 8.1.5.150  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_99 Registers
        151. 8.1.5.151  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_100 Registers
        152. 8.1.5.152  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_101 Registers
        153. 8.1.5.153  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_102 Registers
        154. 8.1.5.154  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_103 Registers
        155. 8.1.5.155  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_104 Registers
        156. 8.1.5.156  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_105 Registers
        157. 8.1.5.157  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_106 Registers
        158. 8.1.5.158  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_107 Registers
        159. 8.1.5.159  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_108 Registers
        160. 8.1.5.160  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_109 Registers
        161. 8.1.5.161  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_110 Registers
        162. 8.1.5.162  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_111 Registers
        163. 8.1.5.163  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_112 Registers
        164. 8.1.5.164  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_113 Registers
        165. 8.1.5.165  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_114 Registers
        166. 8.1.5.166  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_115 Registers
        167. 8.1.5.167  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_116 Registers
        168. 8.1.5.168  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_117 Registers
        169. 8.1.5.169  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_118 Registers
        170. 8.1.5.170  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_119 Registers
        171. 8.1.5.171  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_120 Registers
        172. 8.1.5.172  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_121 Registers
        173. 8.1.5.173  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_122 Registers
        174. 8.1.5.174  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_123 Registers
        175. 8.1.5.175  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_124 Registers
        176. 8.1.5.176  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_125 Registers
        177. 8.1.5.177  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_126 Registers
        178. 8.1.5.178  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_127 Registers
        179. 8.1.5.179  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_128 Registers
        180. 8.1.5.180  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_129 Registers
        181. 8.1.5.181  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_130 Registers
        182. 8.1.5.182  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_131 Registers
        183. 8.1.5.183  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_132 Registers
        184. 8.1.5.184  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_133 Registers
        185. 8.1.5.185  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_134 Registers
        186. 8.1.5.186  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_135 Registers
        187. 8.1.5.187  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_136 Registers
        188. 8.1.5.188  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_137 Registers
        189. 8.1.5.189  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_138 Registers
        190. 8.1.5.190  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_139 Registers
        191. 8.1.5.191  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_140 Registers
        192. 8.1.5.192  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_141 Registers
        193. 8.1.5.193  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_142 Registers
        194. 8.1.5.194  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_143 Registers
        195. 8.1.5.195  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_144 Registers
        196. 8.1.5.196  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_145 Registers
        197. 8.1.5.197  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_146 Registers
        198. 8.1.5.198  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_147 Registers
        199. 8.1.5.199  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_148 Registers
        200. 8.1.5.200  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_149 Registers
        201. 8.1.5.201  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_150 Registers
        202. 8.1.5.202  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_151 Registers
        203. 8.1.5.203  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_152 Registers
        204. 8.1.5.204  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_153 Registers
        205. 8.1.5.205  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_154 Registers
        206. 8.1.5.206  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_155 Registers
        207. 8.1.5.207  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_156 Registers
        208. 8.1.5.208  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_157 Registers
        209. 8.1.5.209  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_158 Registers
        210. 8.1.5.210  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_159 Registers
        211. 8.1.5.211  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_160 Registers
        212. 8.1.5.212  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_161 Registers
        213. 8.1.5.213  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_162 Registers
        214. 8.1.5.214  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_163 Registers
        215. 8.1.5.215  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_164 Registers
        216. 8.1.5.216  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_165 Registers
        217. 8.1.5.217  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_166 Registers
        218. 8.1.5.218  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_167 Registers
        219. 8.1.5.219  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_168 Registers
        220. 8.1.5.220  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_169 Registers
        221. 8.1.5.221  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_170 Registers
        222. 8.1.5.222  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_171 Registers
        223. 8.1.5.223  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_172 Registers
        224. 8.1.5.224  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_173 Registers
        225. 8.1.5.225  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_174 Registers
        226. 8.1.5.226  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_175 Registers
        227. 8.1.5.227  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_176 Registers
        228. 8.1.5.228  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_177 Registers
        229. 8.1.5.229  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_178 Registers
        230. 8.1.5.230  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_179 Registers
        231. 8.1.5.231  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_180 Registers
        232. 8.1.5.232  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_181 Registers
        233. 8.1.5.233  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_182 Registers
        234. 8.1.5.234  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_183 Registers
        235. 8.1.5.235  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_184 Registers
        236. 8.1.5.236  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_185 Registers
        237. 8.1.5.237  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_186 Registers
        238. 8.1.5.238  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_187 Registers
        239. 8.1.5.239  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_188 Registers
        240. 8.1.5.240  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_189 Registers
        241. 8.1.5.241  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_190 Registers
        242. 8.1.5.242  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_191 Registers
        243. 8.1.5.243  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_192 Registers
        244. 8.1.5.244  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_193 Registers
        245. 8.1.5.245  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_194 Registers
        246. 8.1.5.246  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_195 Registers
        247. 8.1.5.247  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_196 Registers
        248. 8.1.5.248  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_197 Registers
        249. 8.1.5.249  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_198 Registers
        250. 8.1.5.250  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_199 Registers
        251. 8.1.5.251  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_200 Registers
        252. 8.1.5.252  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_201 Registers
        253. 8.1.5.253  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_202 Registers
        254. 8.1.5.254  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_203 Registers
        255. 8.1.5.255  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_204 Registers
        256. 8.1.5.256  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_205 Registers
        257. 8.1.5.257  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_206 Registers
        258. 8.1.5.258  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_207 Registers
        259. 8.1.5.259  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_208 Registers
        260. 8.1.5.260  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_209 Registers
        261. 8.1.5.261  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_210 Registers
        262. 8.1.5.262  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_211 Registers
        263. 8.1.5.263  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_212 Registers
        264. 8.1.5.264  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_213 Registers
        265. 8.1.5.265  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_214 Registers
        266. 8.1.5.266  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_215 Registers
        267. 8.1.5.267  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_216 Registers
        268. 8.1.5.268  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_217 Registers
        269. 8.1.5.269  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_218 Registers
        270. 8.1.5.270  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_219 Registers
        271. 8.1.5.271  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_220 Registers
        272. 8.1.5.272  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_221 Registers
        273. 8.1.5.273  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_222 Registers
        274. 8.1.5.274  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_223 Registers
        275. 8.1.5.275  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_224 Registers
        276. 8.1.5.276  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_225 Registers
        277. 8.1.5.277  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_226 Registers
        278. 8.1.5.278  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_227 Registers
        279. 8.1.5.279  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_228 Registers
        280. 8.1.5.280  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_229 Registers
        281. 8.1.5.281  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_230 Registers
        282. 8.1.5.282  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_231 Registers
        283. 8.1.5.283  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_232 Registers
        284. 8.1.5.284  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_233 Registers
        285. 8.1.5.285  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_234 Registers
        286. 8.1.5.286  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_235 Registers
        287. 8.1.5.287  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_236 Registers
        288. 8.1.5.288  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_237 Registers
        289. 8.1.5.289  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_238 Registers
        290. 8.1.5.290  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_239 Registers
        291. 8.1.5.291  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_240 Registers
        292. 8.1.5.292  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_241 Registers
        293. 8.1.5.293  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 Registers
        294. 8.1.5.294  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_243 Registers
        295. 8.1.5.295  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_244 Registers
        296. 8.1.5.296  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_245 Registers
        297. 8.1.5.297  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_246 Registers
        298. 8.1.5.298  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_247 Registers
        299. 8.1.5.299  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_248 Registers
        300. 8.1.5.300  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_249 Registers
        301. 8.1.5.301  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_250 Registers
        302. 8.1.5.302  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_251 Registers
        303. 8.1.5.303  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_252 Registers
        304. 8.1.5.304  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_253 Registers
        305. 8.1.5.305  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_254 Registers
        306. 8.1.5.306  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_255 Registers
        307. 8.1.5.307  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_256 Registers
        308. 8.1.5.308  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_257 Registers
        309. 8.1.5.309  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_258 Registers
        310. 8.1.5.310  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_259 Registers
        311. 8.1.5.311  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_260 Registers
        312. 8.1.5.312  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_261 Registers
        313. 8.1.5.313  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_262 Registers
        314. 8.1.5.314  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_263 Registers
        315. 8.1.5.315  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_264 Registers
        316. 8.1.5.316  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_265 Registers
        317. 8.1.5.317  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_266 Registers
        318. 8.1.5.318  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_267 Registers
        319. 8.1.5.319  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_268 Registers
        320. 8.1.5.320  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_269 Registers
        321. 8.1.5.321  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_270 Registers
        322. 8.1.5.322  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_271 Registers
        323. 8.1.5.323  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_272 Registers
        324. 8.1.5.324  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_273 Registers
        325. 8.1.5.325  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_274 Registers
        326. 8.1.5.326  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_275 Registers
        327. 8.1.5.327  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_276 Registers
        328. 8.1.5.328  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_277 Registers
        329. 8.1.5.329  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_278 Registers
        330. 8.1.5.330  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_279 Registers
        331. 8.1.5.331  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_280 Registers
        332. 8.1.5.332  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_281 Registers
        333. 8.1.5.333  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_282 Registers
        334. 8.1.5.334  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_283 Registers
        335. 8.1.5.335  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_284 Registers
        336. 8.1.5.336  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_285 Registers
        337. 8.1.5.337  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_286 Registers
        338. 8.1.5.338  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_287 Registers
        339. 8.1.5.339  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_288 Registers
        340. 8.1.5.340  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_289 Registers
        341. 8.1.5.341  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_290 Registers
        342. 8.1.5.342  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_291 Registers
        343. 8.1.5.343  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_292 Registers
        344. 8.1.5.344  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_293 Registers
        345. 8.1.5.345  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_294 Registers
        346. 8.1.5.346  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_295 Registers
        347. 8.1.5.347  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_296 Registers
        348. 8.1.5.348  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_297 Registers
        349. 8.1.5.349  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_298 Registers
        350. 8.1.5.350  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_299 Registers
        351. 8.1.5.351  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_300 Registers
        352. 8.1.5.352  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_301 Registers
        353. 8.1.5.353  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_302 Registers
        354. 8.1.5.354  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_303 Registers
        355. 8.1.5.355  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_304 Registers
        356. 8.1.5.356  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_305 Registers
        357. 8.1.5.357  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_306 Registers
        358. 8.1.5.358  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_307 Registers
        359. 8.1.5.359  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_308 Registers
        360. 8.1.5.360  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_309 Registers
        361. 8.1.5.361  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_310 Registers
        362. 8.1.5.362  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_311 Registers
        363. 8.1.5.363  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_312 Registers
        364. 8.1.5.364  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_313 Registers
        365. 8.1.5.365  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_314 Registers
        366. 8.1.5.366  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_315 Registers
        367. 8.1.5.367  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_316 Registers
        368. 8.1.5.368  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_317 Registers
        369. 8.1.5.369  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_318 Registers
        370. 8.1.5.370  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_319 Registers
        371. 8.1.5.371  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_320 Registers
        372. 8.1.5.372  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_321 Registers
        373. 8.1.5.373  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_322 Registers
        374. 8.1.5.374  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_323 Registers
        375. 8.1.5.375  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_324 Registers
        376. 8.1.5.376  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_325 Registers
        377. 8.1.5.377  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_326 Registers
        378. 8.1.5.378  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_327 Registers
        379. 8.1.5.379  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_328 Registers
        380. 8.1.5.380  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_329 Registers
        381. 8.1.5.381  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_330 Registers
        382. 8.1.5.382  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_331 Registers
        383. 8.1.5.383  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_332 Registers
        384. 8.1.5.384  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_333 Registers
        385. 8.1.5.385  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_334 Registers
        386. 8.1.5.386  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_335 Registers
        387. 8.1.5.387  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_336 Registers
        388. 8.1.5.388  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_337 Registers
        389. 8.1.5.389  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_338 Registers
        390. 8.1.5.390  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_339 Registers
        391. 8.1.5.391  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_340 Registers
        392. 8.1.5.392  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_341 Registers
        393. 8.1.5.393  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_342 Registers
        394. 8.1.5.394  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_343 Registers
        395. 8.1.5.395  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_344 Registers
        396. 8.1.5.396  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_345 Registers
        397. 8.1.5.397  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_346 Registers
        398. 8.1.5.398  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_347 Registers
        399. 8.1.5.399  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_348 Registers
        400. 8.1.5.400  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_349 Registers
        401. 8.1.5.401  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_350 Registers
        402. 8.1.5.402  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_351 Registers
        403. 8.1.5.403  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_352 Registers
        404. 8.1.5.404  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_353 Registers
        405. 8.1.5.405  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_354 Registers
        406. 8.1.5.406  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_355 Registers
        407. 8.1.5.407  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_356 Registers
        408. 8.1.5.408  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_357 Registers
        409. 8.1.5.409  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_358 Registers
        410. 8.1.5.410  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_359 Registers
        411. 8.1.5.411  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_360 Registers
        412. 8.1.5.412  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_361 Registers
        413. 8.1.5.413  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_362 Registers
        414. 8.1.5.414  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_363 Registers
        415. 8.1.5.415  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_364 Registers
        416. 8.1.5.416  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_365 Registers
        417. 8.1.5.417  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_366 Registers
        418. 8.1.5.418  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_367 Registers
        419. 8.1.5.419  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_368 Registers
        420. 8.1.5.420  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_369 Registers
        421. 8.1.5.421  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_370 Registers
        422. 8.1.5.422  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_371 Registers
        423. 8.1.5.423  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_372 Registers
        424. 8.1.5.424  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_373 Registers
        425. 8.1.5.425  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_374 Registers
        426. 8.1.5.426  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_375 Registers
        427. 8.1.5.427  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_376 Registers
        428. 8.1.5.428  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_377 Registers
        429. 8.1.5.429  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_378 Registers
        430. 8.1.5.430  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_379 Registers
        431. 8.1.5.431  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_380 Registers
        432. 8.1.5.432  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_381 Registers
        433. 8.1.5.433  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_382 Registers
        434. 8.1.5.434  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_383 Registers
        435. 8.1.5.435  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_384 Registers
        436. 8.1.5.436  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_385 Registers
        437. 8.1.5.437  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_386 Registers
        438. 8.1.5.438  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_387 Registers
        439. 8.1.5.439  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_388 Registers
        440. 8.1.5.440  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_389 Registers
        441. 8.1.5.441  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_390 Registers
        442. 8.1.5.442  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_391 Registers
        443. 8.1.5.443  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_392 Registers
        444. 8.1.5.444  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_393 Registers
        445. 8.1.5.445  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_394 Registers
        446. 8.1.5.446  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_395 Registers
        447. 8.1.5.447  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_396 Registers
        448. 8.1.5.448  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_397 Registers
        449. 8.1.5.449  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_398 Registers
        450. 8.1.5.450  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_399 Registers
        451. 8.1.5.451  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_400 Registers
        452. 8.1.5.452  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_401 Registers
        453. 8.1.5.453  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_402 Registers
        454. 8.1.5.454  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_403 Registers
        455. 8.1.5.455  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_404 Registers
        456. 8.1.5.456  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_405 Registers
        457. 8.1.5.457  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_406 Registers
        458. 8.1.5.458  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_407 Registers
        459. 8.1.5.459  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_408 Registers
        460. 8.1.5.460  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_409 Registers
        461. 8.1.5.461  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_410 Registers
        462. 8.1.5.462  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_411 Registers
        463. 8.1.5.463  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_412 Registers
        464. 8.1.5.464  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_413 Registers
        465. 8.1.5.465  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_414 Registers
        466. 8.1.5.466  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_415 Registers
        467. 8.1.5.467  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_416 Registers
        468. 8.1.5.468  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_417 Registers
        469. 8.1.5.469  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_418 Registers
        470. 8.1.5.470  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_419 Registers
        471. 8.1.5.471  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_420 Registers
        472. 8.1.5.472  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_421 Registers
        473. 8.1.5.473  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_422 Registers
        474. 8.1.5.474  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_0 Registers
        475. 8.1.5.475  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_1 Registers
        476. 8.1.5.476  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_2 Registers
        477. 8.1.5.477  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_3 Registers
        478. 8.1.5.478  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_4 Registers
        479. 8.1.5.479  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_5 Registers
        480. 8.1.5.480  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_6 Registers
        481. 8.1.5.481  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_7 Registers
        482. 8.1.5.482  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_8 Registers
        483. 8.1.5.483  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_9 Registers
        484. 8.1.5.484  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_10 Registers
        485. 8.1.5.485  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_11 Registers
        486. 8.1.5.486  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_12 Registers
        487. 8.1.5.487  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_13 Registers
        488. 8.1.5.488  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_14 Registers
        489. 8.1.5.489  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_15 Registers
        490. 8.1.5.490  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_16 Registers
        491. 8.1.5.491  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_17 Registers
        492. 8.1.5.492  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_18 Registers
        493. 8.1.5.493  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_19 Registers
        494. 8.1.5.494  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_20 Registers
        495. 8.1.5.495  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_21 Registers
        496. 8.1.5.496  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_22 Registers
        497. 8.1.5.497  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_23 Registers
        498. 8.1.5.498  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_24 Registers
        499. 8.1.5.499  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_25 Registers
        500. 8.1.5.500  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_26 Registers
        501. 8.1.5.501  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_27 Registers
        502. 8.1.5.502  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_28 Registers
        503. 8.1.5.503  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_29 Registers
        504. 8.1.5.504  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_30 Registers
        505. 8.1.5.505  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_31 Registers
        506. 8.1.5.506  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_32 Registers
        507. 8.1.5.507  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_33 Registers
        508. 8.1.5.508  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_34 Registers
        509. 8.1.5.509  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_35 Registers
        510. 8.1.5.510  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_36 Registers
        511. 8.1.5.511  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_37 Registers
        512. 8.1.5.512  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_38 Registers
        513. 8.1.5.513  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_39 Registers
        514. 8.1.5.514  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_40 Registers
        515. 8.1.5.515  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_41 Registers
        516. 8.1.5.516  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_42 Registers
        517. 8.1.5.517  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_43 Registers
        518. 8.1.5.518  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_44 Registers
        519. 8.1.5.519  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_45 Registers
        520. 8.1.5.520  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_46 Registers
        521. 8.1.5.521  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_47 Registers
        522. 8.1.5.522  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_48 Registers
        523. 8.1.5.523  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_49 Registers
        524. 8.1.5.524  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_50 Registers
        525. 8.1.5.525  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_51 Registers
        526. 8.1.5.526  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_52 Registers
        527. 8.1.5.527  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_53 Registers
        528. 8.1.5.528  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_54 Registers
        529. 8.1.5.529  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_55 Registers
        530. 8.1.5.530  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_56 Registers
        531. 8.1.5.531  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_57 Registers
        532. 8.1.5.532  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_58 Registers
        533. 8.1.5.533  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_59 Registers
        534. 8.1.5.534  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_60 Registers
        535. 8.1.5.535  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_61 Registers
        536. 8.1.5.536  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_62 Registers
        537. 8.1.5.537  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_63 Registers
        538. 8.1.5.538  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_64 Registers
        539. 8.1.5.539  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_65 Registers
        540. 8.1.5.540  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_66 Registers
        541. 8.1.5.541  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_67 Registers
        542. 8.1.5.542  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_68 Registers
        543. 8.1.5.543  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_69 Registers
        544. 8.1.5.544  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_70 Registers
        545. 8.1.5.545  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_71 Registers
        546. 8.1.5.546  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_72 Registers
        547. 8.1.5.547  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_73 Registers
        548. 8.1.5.548  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_74 Registers
        549. 8.1.5.549  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_75 Registers
        550. 8.1.5.550  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_76 Registers
        551. 8.1.5.551  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_77 Registers
        552. 8.1.5.552  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_78 Registers
        553. 8.1.5.553  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_79 Registers
        554. 8.1.5.554  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_80 Registers
        555. 8.1.5.555  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_81 Registers
        556. 8.1.5.556  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_82 Registers
        557. 8.1.5.557  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_83 Registers
        558. 8.1.5.558  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_84 Registers
        559. 8.1.5.559  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_85 Registers
        560. 8.1.5.560  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_86 Registers
        561. 8.1.5.561  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_87 Registers
        562. 8.1.5.562  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_88 Registers
        563. 8.1.5.563  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_89 Registers
        564. 8.1.5.564  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_90 Registers
        565. 8.1.5.565  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_91 Registers
        566. 8.1.5.566  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_92 Registers
        567. 8.1.5.567  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_93 Registers
        568. 8.1.5.568  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_94 Registers
        569. 8.1.5.569  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_95 Registers
        570. 8.1.5.570  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_96 Registers
        571. 8.1.5.571  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_97 Registers
        572. 8.1.5.572  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_98 Registers
        573. 8.1.5.573  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_99 Registers
        574. 8.1.5.574  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_100 Registers
        575. 8.1.5.575  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_101 Registers
        576. 8.1.5.576  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_102 Registers
        577. 8.1.5.577  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_103 Registers
        578. 8.1.5.578  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_104 Registers
        579. 8.1.5.579  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_105 Registers
        580. 8.1.5.580  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_106 Registers
        581. 8.1.5.581  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_107 Registers
        582. 8.1.5.582  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_108 Registers
        583. 8.1.5.583  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_109 Registers
        584. 8.1.5.584  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_110 Registers
        585. 8.1.5.585  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_111 Registers
        586. 8.1.5.586  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_112 Registers
        587. 8.1.5.587  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_113 Registers
        588. 8.1.5.588  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_114 Registers
        589. 8.1.5.589  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_115 Registers
        590. 8.1.5.590  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_116 Registers
        591. 8.1.5.591  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_117 Registers
        592. 8.1.5.592  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_118 Registers
        593. 8.1.5.593  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_119 Registers
        594. 8.1.5.594  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_120 Registers
        595. 8.1.5.595  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_121 Registers
        596. 8.1.5.596  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_122 Registers
        597. 8.1.5.597  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_123 Registers
        598. 8.1.5.598  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_124 Registers
        599. 8.1.5.599  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_125 Registers
        600. 8.1.5.600  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_126 Registers
        601. 8.1.5.601  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_127 Registers
        602. 8.1.5.602  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_128 Registers
        603. 8.1.5.603  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_129 Registers
        604. 8.1.5.604  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_130 Registers
        605. 8.1.5.605  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_131 Registers
        606. 8.1.5.606  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_132 Registers
        607. 8.1.5.607  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_133 Registers
        608. 8.1.5.608  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_134 Registers
        609. 8.1.5.609  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_135 Registers
        610. 8.1.5.610  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_136 Registers
        611. 8.1.5.611  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_137 Registers
        612. 8.1.5.612  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_138 Registers
        613. 8.1.5.613  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_139 Registers
        614. 8.1.5.614  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_140 Registers
        615. 8.1.5.615  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_141 Registers
        616. 8.1.5.616  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_142 Registers
        617. 8.1.5.617  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_143 Registers
        618. 8.1.5.618  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_144 Registers
        619. 8.1.5.619  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_145 Registers
        620. 8.1.5.620  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_146 Registers
        621. 8.1.5.621  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_147 Registers
        622. 8.1.5.622  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_148 Registers
        623. 8.1.5.623  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_149 Registers
        624. 8.1.5.624  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_150 Registers
        625. 8.1.5.625  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_151 Registers
        626. 8.1.5.626  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_152 Registers
        627. 8.1.5.627  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_153 Registers
        628. 8.1.5.628  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_154 Registers
        629. 8.1.5.629  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_155 Registers
        630. 8.1.5.630  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_156 Registers
        631. 8.1.5.631  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_157 Registers
        632. 8.1.5.632  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_158 Registers
        633. 8.1.5.633  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_159 Registers
        634. 8.1.5.634  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_160 Registers
        635. 8.1.5.635  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_161 Registers
        636. 8.1.5.636  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_162 Registers
        637. 8.1.5.637  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_163 Registers
        638. 8.1.5.638  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_164 Registers
        639. 8.1.5.639  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_165 Registers
        640. 8.1.5.640  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_166 Registers
        641. 8.1.5.641  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_167 Registers
        642. 8.1.5.642  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_168 Registers
        643. 8.1.5.643  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_169 Registers
        644. 8.1.5.644  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_170 Registers
        645. 8.1.5.645  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_171 Registers
        646. 8.1.5.646  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_172 Registers
        647. 8.1.5.647  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_173 Registers
        648. 8.1.5.648  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_174 Registers
        649. 8.1.5.649  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_175 Registers
        650. 8.1.5.650  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_176 Registers
        651. 8.1.5.651  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_177 Registers
        652. 8.1.5.652  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_178 Registers
        653. 8.1.5.653  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_179 Registers
        654. 8.1.5.654  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_180 Registers
        655. 8.1.5.655  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_181 Registers
        656. 8.1.5.656  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_182 Registers
        657. 8.1.5.657  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_183 Registers
        658. 8.1.5.658  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_184 Registers
        659. 8.1.5.659  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_185 Registers
        660. 8.1.5.660  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_186 Registers
        661. 8.1.5.661  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_187 Registers
        662. 8.1.5.662  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_188 Registers
        663. 8.1.5.663  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_189 Registers
        664. 8.1.5.664  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_190 Registers
        665. 8.1.5.665  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_191 Registers
        666. 8.1.5.666  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_192 Registers
        667. 8.1.5.667  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_193 Registers
        668. 8.1.5.668  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_194 Registers
        669. 8.1.5.669  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_195 Registers
        670. 8.1.5.670  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_196 Registers
        671. 8.1.5.671  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_197 Registers
        672. 8.1.5.672  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_198 Registers
        673. 8.1.5.673  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_199 Registers
        674. 8.1.5.674  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_200 Registers
        675. 8.1.5.675  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_201 Registers
        676. 8.1.5.676  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_202 Registers
        677. 8.1.5.677  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_203 Registers
        678. 8.1.5.678  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_204 Registers
        679. 8.1.5.679  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_205 Registers
        680. 8.1.5.680  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_206 Registers
        681. 8.1.5.681  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_207 Registers
        682. 8.1.5.682  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_208 Registers
        683. 8.1.5.683  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_209 Registers
        684. 8.1.5.684  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_210 Registers
        685. 8.1.5.685  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_211 Registers
        686. 8.1.5.686  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_212 Registers
        687. 8.1.5.687  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_213 Registers
        688. 8.1.5.688  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_214 Registers
        689. 8.1.5.689  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_215 Registers
        690. 8.1.5.690  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_216 Registers
        691. 8.1.5.691  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_217 Registers
        692. 8.1.5.692  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_218 Registers
        693. 8.1.5.693  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_219 Registers
        694. 8.1.5.694  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_220 Registers
        695. 8.1.5.695  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_221 Registers
        696. 8.1.5.696  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_222 Registers
        697. 8.1.5.697  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_223 Registers
        698. 8.1.5.698  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_224 Registers
        699. 8.1.5.699  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_225 Registers
        700. 8.1.5.700  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_226 Registers
        701. 8.1.5.701  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_227 Registers
        702. 8.1.5.702  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_228 Registers
        703. 8.1.5.703  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_229 Registers
        704. 8.1.5.704  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_230 Registers
        705. 8.1.5.705  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_231 Registers
        706. 8.1.5.706  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_232 Registers
        707. 8.1.5.707  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_233 Registers
        708. 8.1.5.708  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_234 Registers
        709. 8.1.5.709  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_235 Registers
        710. 8.1.5.710  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_236 Registers
        711. 8.1.5.711  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_237 Registers
        712. 8.1.5.712  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_238 Registers
        713. 8.1.5.713  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_239 Registers
        714. 8.1.5.714  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_240 Registers
        715. 8.1.5.715  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_241 Registers
        716. 8.1.5.716  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_242 Registers
        717. 8.1.5.717  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_243 Registers
        718. 8.1.5.718  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_244 Registers
        719. 8.1.5.719  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_245 Registers
        720. 8.1.5.720  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_246 Registers
        721. 8.1.5.721  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_247 Registers
        722. 8.1.5.722  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_248 Registers
        723. 8.1.5.723  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_249 Registers
        724. 8.1.5.724  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_250 Registers
        725. 8.1.5.725  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_251 Registers
        726. 8.1.5.726  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_252 Registers
        727. 8.1.5.727  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_253 Registers
        728. 8.1.5.728  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_254 Registers
        729. 8.1.5.729  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_255 Registers
        730. 8.1.5.730  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_256 Registers
        731. 8.1.5.731  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_257 Registers
        732. 8.1.5.732  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_258 Registers
        733. 8.1.5.733  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_259 Registers
        734. 8.1.5.734  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_260 Registers
        735. 8.1.5.735  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_261 Registers
        736. 8.1.5.736  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_262 Registers
        737. 8.1.5.737  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_263 Registers
        738. 8.1.5.738  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_264 Registers
        739. 8.1.5.739  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_265 Registers
        740. 8.1.5.740  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_266 Registers
        741. 8.1.5.741  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_267 Registers
        742. 8.1.5.742  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_268 Registers
        743. 8.1.5.743  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_269 Registers
        744. 8.1.5.744  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_270 Registers
        745. 8.1.5.745  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_271 Registers
        746. 8.1.5.746  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_272 Registers
        747. 8.1.5.747  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_273 Registers
        748. 8.1.5.748  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_274 Registers
        749. 8.1.5.749  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_275 Registers
        750. 8.1.5.750  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_276 Registers
        751. 8.1.5.751  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_277 Registers
        752. 8.1.5.752  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_278 Registers
        753. 8.1.5.753  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_279 Registers
        754. 8.1.5.754  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_280 Registers
        755. 8.1.5.755  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_281 Registers
        756. 8.1.5.756  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_282 Registers
        757. 8.1.5.757  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_283 Registers
        758. 8.1.5.758  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_284 Registers
        759. 8.1.5.759  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_285 Registers
        760. 8.1.5.760  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_286 Registers
        761. 8.1.5.761  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_287 Registers
        762. 8.1.5.762  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_288 Registers
        763. 8.1.5.763  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_289 Registers
        764. 8.1.5.764  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_290 Registers
        765. 8.1.5.765  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_291 Registers
        766. 8.1.5.766  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_292 Registers
        767. 8.1.5.767  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_293 Registers
        768. 8.1.5.768  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_294 Registers
        769. 8.1.5.769  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_295 Registers
        770. 8.1.5.770  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_296 Registers
        771. 8.1.5.771  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_297 Registers
        772. 8.1.5.772  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_298 Registers
        773. 8.1.5.773  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_299 Registers
        774. 8.1.5.774  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_300 Registers
        775. 8.1.5.775  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_301 Registers
        776. 8.1.5.776  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_302 Registers
        777. 8.1.5.777  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_303 Registers
        778. 8.1.5.778  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_304 Registers
        779. 8.1.5.779  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_305 Registers
        780. 8.1.5.780  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_306 Registers
        781. 8.1.5.781  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_307 Registers
        782. 8.1.5.782  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_308 Registers
        783. 8.1.5.783  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_309 Registers
        784. 8.1.5.784  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_310 Registers
        785. 8.1.5.785  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_311 Registers
        786. 8.1.5.786  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_312 Registers
        787. 8.1.5.787  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_313 Registers
        788. 8.1.5.788  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_314 Registers
        789. 8.1.5.789  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_315 Registers
        790. 8.1.5.790  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_316 Registers
        791. 8.1.5.791  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_317 Registers
        792. 8.1.5.792  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_318 Registers
        793. 8.1.5.793  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_319 Registers
        794. 8.1.5.794  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_320 Registers
        795. 8.1.5.795  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_321 Registers
        796. 8.1.5.796  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_322 Registers
        797. 8.1.5.797  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_323 Registers
        798. 8.1.5.798  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_324 Registers
        799. 8.1.5.799  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_325 Registers
        800. 8.1.5.800  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_326 Registers
        801. 8.1.5.801  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_327 Registers
        802. 8.1.5.802  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_328 Registers
        803. 8.1.5.803  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_329 Registers
        804. 8.1.5.804  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_330 Registers
        805. 8.1.5.805  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_331 Registers
        806. 8.1.5.806  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_332 Registers
        807. 8.1.5.807  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_333 Registers
        808. 8.1.5.808  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_334 Registers
        809. 8.1.5.809  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_335 Registers
        810. 8.1.5.810  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_336 Registers
        811. 8.1.5.811  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_337 Registers
        812. 8.1.5.812  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_338 Registers
        813. 8.1.5.813  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_339 Registers
        814. 8.1.5.814  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_340 Registers
        815. 8.1.5.815  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_341 Registers
        816. 8.1.5.816  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_342 Registers
        817. 8.1.5.817  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_343 Registers
        818. 8.1.5.818  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_344 Registers
        819. 8.1.5.819  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_0 Registers
        820. 8.1.5.820  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1 Registers
        821. 8.1.5.821  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_2 Registers
        822. 8.1.5.822  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_3 Registers
        823. 8.1.5.823  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_4 Registers
        824. 8.1.5.824  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_5 Registers
        825. 8.1.5.825  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_6 Registers
        826. 8.1.5.826  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_7 Registers
        827. 8.1.5.827  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_8 Registers
        828. 8.1.5.828  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_9 Registers
        829. 8.1.5.829  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_10 Registers
        830. 8.1.5.830  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_11 Registers
        831. 8.1.5.831  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_12 Registers
        832. 8.1.5.832  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_13 Registers
        833. 8.1.5.833  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_14 Registers
        834. 8.1.5.834  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_15 Registers
        835. 8.1.5.835  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_16 Registers
        836. 8.1.5.836  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_17 Registers
        837. 8.1.5.837  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_18 Registers
        838. 8.1.5.838  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_19 Registers
        839. 8.1.5.839  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_20 Registers
        840. 8.1.5.840  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_21 Registers
        841. 8.1.5.841  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_22 Registers
        842. 8.1.5.842  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_23 Registers
        843. 8.1.5.843  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_24 Registers
        844. 8.1.5.844  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_25 Registers
        845. 8.1.5.845  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_26 Registers
        846. 8.1.5.846  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_27 Registers
        847. 8.1.5.847  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_28 Registers
        848. 8.1.5.848  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_29 Registers
        849. 8.1.5.849  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_30 Registers
        850. 8.1.5.850  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_31 Registers
        851. 8.1.5.851  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_32 Registers
        852. 8.1.5.852  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_33 Registers
        853. 8.1.5.853  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_34 Registers
        854. 8.1.5.854  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_35 Registers
        855. 8.1.5.855  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_36 Registers
        856. 8.1.5.856  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_37 Registers
        857. 8.1.5.857  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_38 Registers
        858. 8.1.5.858  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_39 Registers
        859. 8.1.5.859  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_40 Registers
        860. 8.1.5.860  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_41 Registers
        861. 8.1.5.861  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_42 Registers
        862. 8.1.5.862  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_43 Registers
        863. 8.1.5.863  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_44 Registers
        864. 8.1.5.864  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_45 Registers
        865. 8.1.5.865  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_46 Registers
        866. 8.1.5.866  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_47 Registers
        867. 8.1.5.867  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_48 Registers
        868. 8.1.5.868  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_49 Registers
        869. 8.1.5.869  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_50 Registers
        870. 8.1.5.870  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_51 Registers
        871. 8.1.5.871  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_52 Registers
        872. 8.1.5.872  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_53 Registers
        873. 8.1.5.873  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_54 Registers
        874. 8.1.5.874  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_55 Registers
        875. 8.1.5.875  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_56 Registers
        876. 8.1.5.876  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_57 Registers
        877. 8.1.5.877  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_58 Registers
        878. 8.1.5.878  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_59 Registers
        879. 8.1.5.879  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_60 Registers
        880. 8.1.5.880  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_61 Registers
        881. 8.1.5.881  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_62 Registers
        882. 8.1.5.882  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_63 Registers
        883. 8.1.5.883  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_64 Registers
        884. 8.1.5.884  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_65 Registers
        885. 8.1.5.885  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_66 Registers
        886. 8.1.5.886  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_67 Registers
        887. 8.1.5.887  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_68 Registers
        888. 8.1.5.888  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_69 Registers
        889. 8.1.5.889  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_70 Registers
        890. 8.1.5.890  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_71 Registers
        891. 8.1.5.891  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_72 Registers
        892. 8.1.5.892  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_73 Registers
        893. 8.1.5.893  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_74 Registers
        894. 8.1.5.894  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_75 Registers
        895. 8.1.5.895  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_76 Registers
        896. 8.1.5.896  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_77 Registers
        897. 8.1.5.897  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_78 Registers
        898. 8.1.5.898  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_79 Registers
        899. 8.1.5.899  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_80 Registers
        900. 8.1.5.900  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_81 Registers
        901. 8.1.5.901  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_82 Registers
        902. 8.1.5.902  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_83 Registers
        903. 8.1.5.903  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_84 Registers
        904. 8.1.5.904  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_85 Registers
        905. 8.1.5.905  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_86 Registers
        906. 8.1.5.906  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_87 Registers
        907. 8.1.5.907  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_88 Registers
        908. 8.1.5.908  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_89 Registers
        909. 8.1.5.909  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_90 Registers
        910. 8.1.5.910  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_91 Registers
        911. 8.1.5.911  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_92 Registers
        912. 8.1.5.912  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_93 Registers
        913. 8.1.5.913  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_94 Registers
        914. 8.1.5.914  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_95 Registers
        915. 8.1.5.915  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_96 Registers
        916. 8.1.5.916  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_97 Registers
        917. 8.1.5.917  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_98 Registers
        918. 8.1.5.918  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_99 Registers
        919. 8.1.5.919  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_100 Registers
        920. 8.1.5.920  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_101 Registers
        921. 8.1.5.921  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_102 Registers
        922. 8.1.5.922  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_103 Registers
        923. 8.1.5.923  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_104 Registers
        924. 8.1.5.924  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_105 Registers
        925. 8.1.5.925  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_106 Registers
        926. 8.1.5.926  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_107 Registers
        927. 8.1.5.927  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_108 Registers
        928. 8.1.5.928  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_109 Registers
        929. 8.1.5.929  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_110 Registers
        930. 8.1.5.930  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_111 Registers
        931. 8.1.5.931  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_112 Registers
        932. 8.1.5.932  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_113 Registers
        933. 8.1.5.933  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_114 Registers
        934. 8.1.5.934  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_115 Registers
        935. 8.1.5.935  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_116 Registers
        936. 8.1.5.936  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_117 Registers
        937. 8.1.5.937  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_118 Registers
        938. 8.1.5.938  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_119 Registers
        939. 8.1.5.939  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_120 Registers
        940. 8.1.5.940  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_121 Registers
        941. 8.1.5.941  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_122 Registers
        942. 8.1.5.942  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_123 Registers
        943. 8.1.5.943  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_124 Registers
        944. 8.1.5.944  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_125 Registers
        945. 8.1.5.945  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_256 Registers
        946. 8.1.5.946  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_257 Registers
        947. 8.1.5.947  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_258 Registers
        948. 8.1.5.948  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_259 Registers
        949. 8.1.5.949  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_260 Registers
        950. 8.1.5.950  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_261 Registers
        951. 8.1.5.951  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_262 Registers
        952. 8.1.5.952  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_263 Registers
        953. 8.1.5.953  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_264 Registers
        954. 8.1.5.954  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_265 Registers
        955. 8.1.5.955  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_266 Registers
        956. 8.1.5.956  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_267 Registers
        957. 8.1.5.957  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_268 Registers
        958. 8.1.5.958  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_269 Registers
        959. 8.1.5.959  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_270 Registers
        960. 8.1.5.960  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_271 Registers
        961. 8.1.5.961  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_272 Registers
        962. 8.1.5.962  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_273 Registers
        963. 8.1.5.963  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_274 Registers
        964. 8.1.5.964  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_275 Registers
        965. 8.1.5.965  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_276 Registers
        966. 8.1.5.966  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_277 Registers
        967. 8.1.5.967  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_278 Registers
        968. 8.1.5.968  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_279 Registers
        969. 8.1.5.969  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_280 Registers
        970. 8.1.5.970  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_281 Registers
        971. 8.1.5.971  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_282 Registers
        972. 8.1.5.972  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_283 Registers
        973. 8.1.5.973  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_284 Registers
        974. 8.1.5.974  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_285 Registers
        975. 8.1.5.975  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_286 Registers
        976. 8.1.5.976  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_287 Registers
        977. 8.1.5.977  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_288 Registers
        978. 8.1.5.978  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_289 Registers
        979. 8.1.5.979  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_290 Registers
        980. 8.1.5.980  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_291 Registers
        981. 8.1.5.981  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_292 Registers
        982. 8.1.5.982  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_293 Registers
        983. 8.1.5.983  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_294 Registers
        984. 8.1.5.984  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_295 Registers
        985. 8.1.5.985  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_296 Registers
        986. 8.1.5.986  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_297 Registers
        987. 8.1.5.987  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_298 Registers
        988. 8.1.5.988  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_299 Registers
        989. 8.1.5.989  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_300 Registers
        990. 8.1.5.990  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_301 Registers
        991. 8.1.5.991  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_302 Registers
        992. 8.1.5.992  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_303 Registers
        993. 8.1.5.993  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_304 Registers
        994. 8.1.5.994  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_305 Registers
        995. 8.1.5.995  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_306 Registers
        996. 8.1.5.996  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_307 Registers
        997. 8.1.5.997  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_308 Registers
        998. 8.1.5.998  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_309 Registers
        999. 8.1.5.999  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_310 Registers
        1000. 8.1.5.1000 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_311 Registers
        1001. 8.1.5.1001 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_312 Registers
        1002. 8.1.5.1002 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_313 Registers
        1003. 8.1.5.1003 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_314 Registers
        1004. 8.1.5.1004 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_315 Registers
        1005. 8.1.5.1005 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_316 Registers
        1006. 8.1.5.1006 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_317 Registers
        1007. 8.1.5.1007 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_318 Registers
        1008. 8.1.5.1008 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_319 Registers
        1009. 8.1.5.1009 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_320 Registers
        1010. 8.1.5.1010 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_321 Registers
        1011. 8.1.5.1011 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_322 Registers
        1012. 8.1.5.1012 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_323 Registers
        1013. 8.1.5.1013 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_324 Registers
        1014. 8.1.5.1014 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_325 Registers
        1015. 8.1.5.1015 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_326 Registers
        1016. 8.1.5.1016 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_327 Registers
        1017. 8.1.5.1017 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_328 Registers
        1018. 8.1.5.1018 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_329 Registers
        1019. 8.1.5.1019 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_330 Registers
        1020. 8.1.5.1020 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_331 Registers
        1021. 8.1.5.1021 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_332 Registers
        1022. 8.1.5.1022 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_333 Registers
        1023. 8.1.5.1023 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_334 Registers
        1024. 8.1.5.1024 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_335 Registers
        1025. 8.1.5.1025 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_336 Registers
        1026. 8.1.5.1026 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_337 Registers
        1027. 8.1.5.1027 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_338 Registers
        1028. 8.1.5.1028 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_339 Registers
        1029. 8.1.5.1029 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_340 Registers
        1030. 8.1.5.1030 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_341 Registers
        1031. 8.1.5.1031 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_342 Registers
        1032. 8.1.5.1032 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_343 Registers
        1033. 8.1.5.1033 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_344 Registers
        1034. 8.1.5.1034 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_345 Registers
        1035. 8.1.5.1035 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_346 Registers
        1036. 8.1.5.1036 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_347 Registers
        1037. 8.1.5.1037 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_348 Registers
        1038. 8.1.5.1038 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_349 Registers
        1039. 8.1.5.1039 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_350 Registers
        1040. 8.1.5.1040 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_351 Registers
        1041. 8.1.5.1041 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_352 Registers
        1042. 8.1.5.1042 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_353 Registers
        1043. 8.1.5.1043 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_354 Registers
        1044. 8.1.5.1044 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_355 Registers
        1045. 8.1.5.1045 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_356 Registers
        1046. 8.1.5.1046 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_357 Registers
        1047. 8.1.5.1047 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_358 Registers
        1048. 8.1.5.1048 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_359 Registers
        1049. 8.1.5.1049 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_360 Registers
        1050. 8.1.5.1050 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_361 Registers
        1051. 8.1.5.1051 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_362 Registers
        1052. 8.1.5.1052 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_363 Registers
        1053. 8.1.5.1053 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_364 Registers
        1054. 8.1.5.1054 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_365 Registers
        1055. 8.1.5.1055 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_366 Registers
        1056. 8.1.5.1056 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_367 Registers
        1057. 8.1.5.1057 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_368 Registers
        1058. 8.1.5.1058 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_369 Registers
        1059. 8.1.5.1059 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_370 Registers
        1060. 8.1.5.1060 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_371 Registers
        1061. 8.1.5.1061 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_372 Registers
        1062. 8.1.5.1062 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_373 Registers
        1063. 8.1.5.1063 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_374 Registers
        1064. 8.1.5.1064 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_375 Registers
        1065. 8.1.5.1065 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_376 Registers
        1066. 8.1.5.1066 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_377 Registers
        1067. 8.1.5.1067 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_378 Registers
        1068. 8.1.5.1068 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_379 Registers
        1069. 8.1.5.1069 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_380 Registers
        1070. 8.1.5.1070 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_381 Registers
        1071. 8.1.5.1071 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_512 Registers
        1072. 8.1.5.1072 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_513 Registers
        1073. 8.1.5.1073 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_514 Registers
        1074. 8.1.5.1074 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_515 Registers
        1075. 8.1.5.1075 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_516 Registers
        1076. 8.1.5.1076 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_517 Registers
        1077. 8.1.5.1077 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_518 Registers
        1078. 8.1.5.1078 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_519 Registers
        1079. 8.1.5.1079 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_520 Registers
        1080. 8.1.5.1080 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_521 Registers
        1081. 8.1.5.1081 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_522 Registers
        1082. 8.1.5.1082 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_523 Registers
        1083. 8.1.5.1083 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_524 Registers
        1084. 8.1.5.1084 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_525 Registers
        1085. 8.1.5.1085 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_526 Registers
        1086. 8.1.5.1086 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_527 Registers
        1087. 8.1.5.1087 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_528 Registers
        1088. 8.1.5.1088 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_529 Registers
        1089. 8.1.5.1089 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_530 Registers
        1090. 8.1.5.1090 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_531 Registers
        1091. 8.1.5.1091 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_532 Registers
        1092. 8.1.5.1092 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_533 Registers
        1093. 8.1.5.1093 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_534 Registers
        1094. 8.1.5.1094 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_535 Registers
        1095. 8.1.5.1095 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_536 Registers
        1096. 8.1.5.1096 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_537 Registers
        1097. 8.1.5.1097 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_538 Registers
        1098. 8.1.5.1098 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_539 Registers
        1099. 8.1.5.1099 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_540 Registers
        1100. 8.1.5.1100 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_541 Registers
        1101. 8.1.5.1101 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_542 Registers
        1102. 8.1.5.1102 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_543 Registers
        1103. 8.1.5.1103 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_544 Registers
        1104. 8.1.5.1104 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_545 Registers
        1105. 8.1.5.1105 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_546 Registers
        1106. 8.1.5.1106 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_547 Registers
        1107. 8.1.5.1107 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_548 Registers
        1108. 8.1.5.1108 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_549 Registers
        1109. 8.1.5.1109 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_550 Registers
        1110. 8.1.5.1110 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_551 Registers
        1111. 8.1.5.1111 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_552 Registers
        1112. 8.1.5.1112 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_553 Registers
        1113. 8.1.5.1113 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_554 Registers
        1114. 8.1.5.1114 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_768 Registers
        1115. 8.1.5.1115 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_769 Registers
        1116. 8.1.5.1116 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_770 Registers
        1117. 8.1.5.1117 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_771 Registers
        1118. 8.1.5.1118 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_772 Registers
        1119. 8.1.5.1119 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_773 Registers
        1120. 8.1.5.1120 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_774 Registers
        1121. 8.1.5.1121 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_775 Registers
        1122. 8.1.5.1122 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_776 Registers
        1123. 8.1.5.1123 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_777 Registers
        1124. 8.1.5.1124 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_778 Registers
        1125. 8.1.5.1125 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_779 Registers
        1126. 8.1.5.1126 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_780 Registers
        1127. 8.1.5.1127 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_781 Registers
        1128. 8.1.5.1128 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_782 Registers
        1129. 8.1.5.1129 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_783 Registers
        1130. 8.1.5.1130 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_784 Registers
        1131. 8.1.5.1131 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_785 Registers
        1132. 8.1.5.1132 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_786 Registers
        1133. 8.1.5.1133 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_787 Registers
        1134. 8.1.5.1134 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_788 Registers
        1135. 8.1.5.1135 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_789 Registers
        1136. 8.1.5.1136 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_790 Registers
        1137. 8.1.5.1137 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_791 Registers
        1138. 8.1.5.1138 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_792 Registers
        1139. 8.1.5.1139 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_793 Registers
        1140. 8.1.5.1140 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_794 Registers
        1141. 8.1.5.1141 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_795 Registers
        1142. 8.1.5.1142 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_796 Registers
        1143. 8.1.5.1143 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_797 Registers
        1144. 8.1.5.1144 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_798 Registers
        1145. 8.1.5.1145 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_799 Registers
        1146. 8.1.5.1146 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_800 Registers
        1147. 8.1.5.1147 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_801 Registers
        1148. 8.1.5.1148 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_802 Registers
        1149. 8.1.5.1149 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_803 Registers
        1150. 8.1.5.1150 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_804 Registers
        1151. 8.1.5.1151 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_805 Registers
        1152. 8.1.5.1152 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_806 Registers
        1153. 8.1.5.1153 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_807 Registers
        1154. 8.1.5.1154 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_808 Registers
        1155. 8.1.5.1155 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_809 Registers
        1156. 8.1.5.1156 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_810 Registers
        1157. 8.1.5.1157 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1024 Registers
        1158. 8.1.5.1158 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1025 Registers
        1159. 8.1.5.1159 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1026 Registers
        1160. 8.1.5.1160 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1027 Registers
        1161. 8.1.5.1161 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1028 Registers
        1162. 8.1.5.1162 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1029 Registers
        1163. 8.1.5.1163 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1030 Registers
        1164. 8.1.5.1164 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1031 Registers
        1165. 8.1.5.1165 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1032 Registers
        1166. 8.1.5.1166 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1033 Registers
        1167. 8.1.5.1167 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1034 Registers
        1168. 8.1.5.1168 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1035 Registers
        1169. 8.1.5.1169 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1036 Registers
        1170. 8.1.5.1170 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1037 Registers
        1171. 8.1.5.1171 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1038 Registers
        1172. 8.1.5.1172 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1039 Registers
        1173. 8.1.5.1173 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1040 Registers
        1174. 8.1.5.1174 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1041 Registers
        1175. 8.1.5.1175 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1042 Registers
        1176. 8.1.5.1176 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1043 Registers
        1177. 8.1.5.1177 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1044 Registers
        1178. 8.1.5.1178 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1045 Registers
        1179. 8.1.5.1179 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1046 Registers
        1180. 8.1.5.1180 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1047 Registers
        1181. 8.1.5.1181 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1048 Registers
        1182. 8.1.5.1182 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1049 Registers
        1183. 8.1.5.1183 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1050 Registers
        1184. 8.1.5.1184 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1051 Registers
        1185. 8.1.5.1185 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1052 Registers
        1186. 8.1.5.1186 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1053 Registers
        1187. 8.1.5.1187 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1054 Registers
        1188. 8.1.5.1188 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1055 Registers
        1189. 8.1.5.1189 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1056 Registers
        1190. 8.1.5.1190 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1057 Registers
        1191. 8.1.5.1191 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1058 Registers
        1192. 8.1.5.1192 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1059 Registers
        1193. 8.1.5.1193 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1060 Registers
        1194. 8.1.5.1194 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1061 Registers
        1195. 8.1.5.1195 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1062 Registers
        1196. 8.1.5.1196 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1063 Registers
        1197. 8.1.5.1197 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1064 Registers
        1198. 8.1.5.1198 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1065 Registers
        1199. 8.1.5.1199 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1066 Registers
        1200. 8.1.5.1200 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1280 Registers
        1201. 8.1.5.1201 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1281 Registers
        1202. 8.1.5.1202 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1282 Registers
        1203. 8.1.5.1203 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1283 Registers
        1204. 8.1.5.1204 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1284 Registers
        1205. 8.1.5.1205 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1285 Registers
        1206. 8.1.5.1206 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1286 Registers
        1207. 8.1.5.1207 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1287 Registers
        1208. 8.1.5.1208 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1288 Registers
        1209. 8.1.5.1209 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1289 Registers
        1210. 8.1.5.1210 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1290 Registers
        1211. 8.1.5.1211 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1291 Registers
        1212. 8.1.5.1212 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1292 Registers
        1213. 8.1.5.1213 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1293 Registers
        1214. 8.1.5.1214 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1294 Registers
        1215. 8.1.5.1215 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1295 Registers
        1216. 8.1.5.1216 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1296 Registers
        1217. 8.1.5.1217 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1297 Registers
        1218. 8.1.5.1218 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1298 Registers
        1219. 8.1.5.1219 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1299 Registers
        1220. 8.1.5.1220 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1300 Registers
        1221. 8.1.5.1221 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1301 Registers
        1222. 8.1.5.1222 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1302 Registers
        1223. 8.1.5.1223 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1303 Registers
        1224. 8.1.5.1224 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1304 Registers
        1225. 8.1.5.1225 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1305 Registers
        1226. 8.1.5.1226 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1306 Registers
        1227. 8.1.5.1227 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1307 Registers
        1228. 8.1.5.1228 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1308 Registers
        1229. 8.1.5.1229 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1309 Registers
        1230. 8.1.5.1230 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1310 Registers
        1231. 8.1.5.1231 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1311 Registers
        1232. 8.1.5.1232 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1312 Registers
        1233. 8.1.5.1233 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1313 Registers
        1234. 8.1.5.1234 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1314 Registers
        1235. 8.1.5.1235 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1315 Registers
        1236. 8.1.5.1236 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1316 Registers
        1237. 8.1.5.1237 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1317 Registers
        1238. 8.1.5.1238 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1318 Registers
        1239. 8.1.5.1239 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1319 Registers
        1240. 8.1.5.1240 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1320 Registers
        1241. 8.1.5.1241 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1321 Registers
        1242. 8.1.5.1242 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1322 Registers
        1243. 8.1.5.1243 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1323 Registers
        1244. 8.1.5.1244 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1324 Registers
        1245. 8.1.5.1245 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1325 Registers
        1246. 8.1.5.1246 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1326 Registers
        1247. 8.1.5.1247 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1327 Registers
        1248. 8.1.5.1248 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1328 Registers
        1249. 8.1.5.1249 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1329 Registers
        1250. 8.1.5.1250 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1330 Registers
        1251. 8.1.5.1251 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1331 Registers
        1252. 8.1.5.1252 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1332 Registers
        1253. 8.1.5.1253 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1333 Registers
        1254. 8.1.5.1254 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1334 Registers
        1255. 8.1.5.1255 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1335 Registers
        1256. 8.1.5.1256 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1336 Registers
        1257. 8.1.5.1257 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1337 Registers
        1258. 8.1.5.1258 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1338 Registers
        1259. 8.1.5.1259 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1339 Registers
        1260. 8.1.5.1260 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1340 Registers
        1261. 8.1.5.1261 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1341 Registers
        1262. 8.1.5.1262 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1342 Registers
        1263. 8.1.5.1263 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1343 Registers
        1264. 8.1.5.1264 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1344 Registers
        1265. 8.1.5.1265 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1345 Registers
        1266. 8.1.5.1266 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1346 Registers
        1267. 8.1.5.1267 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1347 Registers
        1268. 8.1.5.1268 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1348 Registers
        1269. 8.1.5.1269 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1349 Registers
        1270. 8.1.5.1270 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1350 Registers
        1271. 8.1.5.1271 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1351 Registers
        1272. 8.1.5.1272 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1352 Registers
        1273. 8.1.5.1273 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1353 Registers
        1274. 8.1.5.1274 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1354 Registers
        1275. 8.1.5.1275 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1355 Registers
        1276. 8.1.5.1276 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1356 Registers
        1277. 8.1.5.1277 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1357 Registers
        1278. 8.1.5.1278 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1358 Registers
        1279. 8.1.5.1279 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1359 Registers
        1280. 8.1.5.1280 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1360 Registers
        1281. 8.1.5.1281 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1361 Registers
        1282. 8.1.5.1282 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1362 Registers
        1283. 8.1.5.1283 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1363 Registers
        1284. 8.1.5.1284 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1364 Registers
        1285. 8.1.5.1285 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1365 Registers
        1286. 8.1.5.1286 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1366 Registers
        1287. 8.1.5.1287 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1367 Registers
        1288. 8.1.5.1288 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1368 Registers
        1289. 8.1.5.1289 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1369 Registers
        1290. 8.1.5.1290 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1370 Registers
        1291. 8.1.5.1291 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1371 Registers
        1292. 8.1.5.1292 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1372 Registers
        1293. 8.1.5.1293 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1373 Registers
        1294. 8.1.5.1294 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1374 Registers
        1295. 8.1.5.1295 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1375 Registers
        1296. 8.1.5.1296 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1376 Registers
        1297. 8.1.5.1297 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1377 Registers
        1298. 8.1.5.1298 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1378 Registers
        1299. 8.1.5.1299 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1379 Registers
        1300. 8.1.5.1300 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1380 Registers
        1301. 8.1.5.1301 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1381 Registers
        1302. 8.1.5.1302 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1382 Registers
        1303. 8.1.5.1303 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1383 Registers
        1304. 8.1.5.1304 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1384 Registers
        1305. 8.1.5.1305 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1385 Registers
        1306. 8.1.5.1306 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1386 Registers
        1307. 8.1.5.1307 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1387 Registers
        1308. 8.1.5.1308 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1388 Registers
        1309. 8.1.5.1309 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1389 Registers
        1310. 8.1.5.1310 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1390 Registers
        1311. 8.1.5.1311 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1391 Registers
        1312. 8.1.5.1312 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1392 Registers
        1313. 8.1.5.1313 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1393 Registers
        1314. 8.1.5.1314 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1394 Registers
        1315. 8.1.5.1315 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1395 Registers
        1316. 8.1.5.1316 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1396 Registers
        1317. 8.1.5.1317 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1397 Registers
        1318. 8.1.5.1318 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1398 Registers
        1319. 8.1.5.1319 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1399 Registers
        1320. 8.1.5.1320 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1400 Registers
        1321. 8.1.5.1321 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1401 Registers
        1322. 8.1.5.1322 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1402 Registers
        1323. 8.1.5.1323 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1403 Registers
        1324. 8.1.5.1324 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1404 Registers
        1325. 8.1.5.1325 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1405 Registers
        1326. 8.1.5.1326 Access Table
    2. 8.2 Region-based Address Translation (RAT) Module
      1. 8.2.1 RAT Functional Description
        1. 8.2.1.1 RAT Availability
        2. 8.2.1.2 RAT Operation
        3. 8.2.1.3 RAT Error Logging
      2. 8.2.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GICSS)
        1. 9.2.1.1 GICSS Overview
          1. 9.2.1.1.1 GICSS Features
          2. 9.2.1.1.2 GICSS Not Supported Features
        2. 9.2.1.2 GICSS Integration
        3. 9.2.1.3 GICSS Functional Description
          1. 9.2.1.3.1 GICSS Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GICSS Interrupt Types
          4. 9.2.1.3.4 GICSS Interfaces
          5. 9.2.1.3.5 GICSS Interrupt Outputs
          6. 9.2.1.3.6 GICSS ECC Support
          7. 9.2.1.3.7 GICSS AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GICSS Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GICSS0_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 MCU_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 MCU_GPIOMUX_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 MAIN Domain Interrupt Maps
        1. 9.4.1.1 GICSS0 Interrupt Map
          1. 9.4.1.1.1 GICSS0 PPI Interrupt Map
          2. 9.4.1.1.2 GICSS0 SPI Interrupt Map
        2. 9.4.1.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.1.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.1.4 R5FSS1_CORE0 Interrupt Map
        5. 9.4.1.5 R5FSS1_CORE1 Interrupt Map
        6. 9.4.1.6 PRU_ICSSG0 Interrupt Map
        7. 9.4.1.7 PRU_ICSSG1 Interrupt Map
        8. 9.4.1.8 GPIOMUX_INTRTR0 Interrupt Map
        9. 9.4.1.9 ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_M4FSS Interrupt Map
        2. 9.4.2.2 MCU_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
    5. 9.5 Time Sync and Compare Interrupt Events
      1. 9.5.1 CMPEVT_INTRTR0 Interrupt Map
      2. 9.5.2 TIMESYNC_INTRTR0 Interrupt Map
  12. 10Time Sync
    1. 10.1 Time Sync Module (CPTS)
      1. 10.1.1 CPTS Overview
        1. 10.1.1.1 CPTS Features
        2. 10.1.1.2 CPTS Not Supported Features
      2. 10.1.2 CPTS Integration
      3. 10.1.3 CPTS Functional Description
        1. 10.1.3.1  CPTS Architecture
        2. 10.1.3.2  CPTS Initialization
        3. 10.1.3.3  32-bit Time Stamp Value
        4. 10.1.3.4  64-bit Time Stamp Value
          1. 10.1.3.4.1 64-Bit Timestamp Nudge
          2. 10.1.3.4.2 64-bit Timestamp PPM
        5. 10.1.3.5  Event FIFO
        6. 10.1.3.6  Timestamp Compare Output
          1. 10.1.3.6.1 Non-Toggle Mode
          2. 10.1.3.6.2 Toggle Mode
        7. 10.1.3.7  Timestamp Sync Output
        8. 10.1.3.8  Timestamp GENF Output
          1. 10.1.3.8.1 GENFn Nudge
          2. 10.1.3.8.2 GENFn PPM
        9. 10.1.3.9  Time Sync Events
          1. 10.1.3.9.1 Time Stamp Push Event
          2. 10.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 10.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 10.1.3.9.4 Hardware Time Stamp Push Event
        10. 10.1.3.10 Timestamp Compare Event
        11. 10.1.3.11 CPTS Interrupt Handling
      4. 10.1.4 CPTS Registers
    2. 10.2 Timer Manager
      1. 10.2.1 Timer Manager Overview
        1. 10.2.1.1 Timer Manager Features
        2. 10.2.1.2 Timer Manager Not Supported Features
      2. 10.2.2 Timer Manager Integration
      3. 10.2.3 Timer Manager Functional Description
        1. 10.2.3.1 Timer Manager Function Overview
        2. 10.2.3.2 Timer Counter
          1. 10.2.3.2.1 Timer Counter Rollover
        3. 10.2.3.3 Timer Control Module (FSM)
        4. 10.2.3.4 Timer Reprogramming
          1. 10.2.3.4.1 Periodic Hardware Timers
        5. 10.2.3.5 Event FIFO
        6. 10.2.3.6 Timer Manager Unmapped Events mapping
      4. 10.2.4 Timer Manager Programming Guide
        1. 10.2.4.1 Timer Manager Low-level Programming Models
          1. 10.2.4.1.1 Surrounding Modules Global Initialization
          2. 10.2.4.1.2 Initialization Sequence
          3. 10.2.4.1.3 Real-time Operating Requirements
            1. 10.2.4.1.3.1 Timer Touch
            2. 10.2.4.1.3.2 Timer Disable
            3. 10.2.4.1.3.3 Timer Enable
          4. 10.2.4.1.4 Power Up/Power Down Sequence
      5. 10.2.5 Timer Manager Registers
        1. 10.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 10.2.5.2 TIMERMGR_CFG_TIMERS Registers
    3. 10.3 Time Sync and Compare Events
      1. 10.3.1 Time Sync Architecture
        1. 10.3.1.1 Time Sync Architecture Overview
      2. 10.3.2 Time Sync Routers
        1. 10.3.2.1 Time Sync Routers Overview
        2. 10.3.2.2 Time Sync Routers Integration
          1. 10.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 10.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 10.3.2.3 Time Sync Routers Registers
          1. 10.3.2.3.1 TIMESYNC_EVENT_INTROUTER Registers
            1. 10.3.2.3.1.1 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.1.2 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.1.3 Access Table
          2. 10.3.2.3.2 CMP_EVENT_INTROUTER Registers
            1. 10.3.2.3.2.1 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.2.2 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.2.3 Access Table
      3. 10.3.3 Time Sync Event Sources
  13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
      1. 11.1.1 Overview
        1. 11.1.1.1 Ring Accelerator (RINGACC)
        2. 11.1.1.2 Secure Proxy (SEC_PROXY)
        3. 11.1.1.3 Interrupt Aggregator (INTAGGR)
        4. 11.1.1.4 Packet DMA (PKTDMA)
          1. 11.1.1.4.1 PKTDMA Submodule Descriptions
            1. 11.1.1.4.1.1  Bus Interface Unit
            2. 11.1.1.4.1.2  Config CR
            3. 11.1.1.4.1.3  Configuration Registers
              1. 11.1.1.4.1.3.1 RX State Mapping
              2. 11.1.1.4.1.3.2 TX State Mapping
            4. 11.1.1.4.1.4  Tx Packet DMA Unit
            5. 11.1.1.4.1.5  Tx Packet Coherency Unit
            6. 11.1.1.4.1.6  Tx Per Channel Buffers
            7. 11.1.1.4.1.7  Rx Per Channel Buffers
            8. 11.1.1.4.1.8  Rx Packet DMA Unit
            9. 11.1.1.4.1.9  Rx Packet Coherency Unit
            10. 11.1.1.4.1.10 Event Handler
          2. 11.1.1.4.2 Channel Classes
        5. 11.1.1.5 Block Copy DMA (BCDMA)
          1. 11.1.1.5.1 BCDMA Submodule Descriptions
            1. 11.1.1.5.1.1  Bus Interface Unit
            2. 11.1.1.5.1.2  Config CR
            3. 11.1.1.5.1.3  Configuration Registers
              1. 11.1.1.5.1.3.1 BCDMA Mapping Table
            4. 11.1.1.5.1.4  Read Unit(s)
            5. 11.1.1.5.1.5  TR Coherency Unit
            6. 11.1.1.5.1.6  Per-Copy-Channel Buffers
            7. 11.1.1.5.1.7  Tx Per-Split-Channel Buffers
            8. 11.1.1.5.1.8  Rx Per-Split-Channel Buffers
            9. 11.1.1.5.1.9  Write Unit(s)
            10. 11.1.1.5.1.10 Event Coherency Unit
            11. 11.1.1.5.1.11 Event Handler
          2. 11.1.1.5.2 Channel Classes
      2. 11.1.2 Definition of Terms
      3. 11.1.3 DMSS Hardware/Software Interface
        1. 11.1.3.1 Data Buffers
        2. 11.1.3.2 Descriptors
          1. 11.1.3.2.1 Host Packet Descriptor
          2. 11.1.3.2.2 Host Buffer Descriptor
          3. 11.1.3.2.3 Transfer Request Descriptor
        3. 11.1.3.3 Transfer Request Record
          1. 11.1.3.3.1 Overview
          2. 11.1.3.3.2 Addressing Algorithm
            1. 11.1.3.3.2.1 Linear Addressing (Forward)
          3. 11.1.3.3.3 Transfer Request Formats
          4. 11.1.3.3.4 Flags Field Definition
            1. 11.1.3.3.4.1 Type: TR Type Field
            2. 11.1.3.3.4.2 EVENT_SIZE: Event Generation Definition
            3. 11.1.3.3.4.3 TRIGGER_INFO: TR Triggers
            4. 11.1.3.3.4.4 TRIGGERX_TYPE: Trigger Type
            5. 11.1.3.3.4.5 TRIGGERX: Trigger Selection
            6. 11.1.3.3.4.6 Configuration Specific Flags Definition
          5. 11.1.3.3.5 TR Address and Size Attributes
            1. 11.1.3.3.5.1  ICNT0
            2. 11.1.3.3.5.2  ICNT1
            3. 11.1.3.3.5.3  ADDR
            4. 11.1.3.3.5.4  DIM1
            5. 11.1.3.3.5.5  ICNT2
            6. 11.1.3.3.5.6  ICNT3
            7. 11.1.3.3.5.7  DIM2
            8. 11.1.3.3.5.8  DIM3
            9. 11.1.3.3.5.9  DDIM1
            10. 11.1.3.3.5.10 DADDR
            11. 11.1.3.3.5.11 DDIM2
            12. 11.1.3.3.5.12 DDIM3
            13. 11.1.3.3.5.13 DICNT0
            14. 11.1.3.3.5.14 DICNT1
            15. 11.1.3.3.5.15 DICNT2
            16. 11.1.3.3.5.16 DICNT3
        4. 11.1.3.4 Transfer Response Record
          1. 11.1.3.4.1 STATUS Field Definition
            1. 11.1.3.4.1.1 STATUS_TYPE Definitions
              1. 11.1.3.4.1.1.1 Transfer Error
              2. 11.1.3.4.1.1.2 Aborted Error
              3. 11.1.3.4.1.1.3 Submission Error
              4. 11.1.3.4.1.1.4 Unsupported Feature
              5. 11.1.3.4.1.1.5 Transfer Exception
              6. 11.1.3.4.1.1.6 Teardown Flush
        5. 11.1.3.5 Channels
        6. 11.1.3.6 Flows
        7. 11.1.3.7 Queues
          1. 11.1.3.7.1 Queue Types
            1. 11.1.3.7.1.1 Transmit Queues
            2. 11.1.3.7.1.2 Transmit Completion Queues
            3. 11.1.3.7.1.3 Free Descriptor / Buffer Queues
            4. 11.1.3.7.1.4 Receive Queues
            5. 11.1.3.7.1.5 Ring Based Queues Implementation
      4. 11.1.4 Operational Description
        1. 11.1.4.1  Resource Allocation
        2. 11.1.4.2  PKTDMA/BCDMA - Ring Operation
          1. 11.1.4.2.1 Queue Initialization
          2. 11.1.4.2.2 Queueing Entries
          3. 11.1.4.2.3 De-queueing Entries
        3. 11.1.4.3  PKTDMA/BCDMA - Output Event Generation
        4. 11.1.4.4  PKTDMA - Transmit Channel Setup
        5. 11.1.4.5  PKTDMA - Transmit Channel Pause
        6. 11.1.4.6  PKTDMA - Transmit Channel Teardown
        7. 11.1.4.7  PKTDMA - Transmit Operation
        8. 11.1.4.8  PKTDMA - Receive Free Descriptor / Buffer Queue Setup
        9. 11.1.4.9  PKTDMA - Receive Channel Setup
        10. 11.1.4.10 PKTDMA - Receive Channel Teardown
        11. 11.1.4.11 PKTDMA - Receive Channel Pause
        12. 11.1.4.12 PKTDMA - Receive Operation
        13. 11.1.4.13 BCDMA - Block Copy Channel Setup
        14. 11.1.4.14 BCDMA - Block Copy Channel Pause
        15. 11.1.4.15 BCDMA - Block Copy Channel Teardown
        16. 11.1.4.16 BCDMA - Block Copy Operation (TR Packet)
        17. 11.1.4.17 BCDMA - Block Copy Error/Exception Handling
          1. 11.1.4.17.1 Null Icnt0 Error
          2. 11.1.4.17.2 Unsupported TR Type
          3. 11.1.4.17.3 Bus Errors
        18. 11.1.4.18 BCDMA - Split Transmit Channel Setup
        19. 11.1.4.19 BCDMA - Split Transmit Operation Pause
        20. 11.1.4.20 BCDMA - Split Transmit Channel Teardown
        21. 11.1.4.21 BCDMA - Split Transmit Operation (TR Packet)
        22. 11.1.4.22 BCDMA - Split Transmit Error / Exception Handling
          1. 11.1.4.22.1 Null Icnt0 Error
          2. 11.1.4.22.2 Unsupported TR Type
          3. 11.1.4.22.3 Bus Errors
        23. 11.1.4.23 BCDMA - Split Receive Channel Setup
        24. 11.1.4.24 BCDMA - Split Receive Channel Pause
        25. 11.1.4.25 BCDMA - Split Receive Channel Teardown
        26. 11.1.4.26 BCDMA - Split Receive Operation (TR Packet)
        27. 11.1.4.27 BCDMA - Split Receive Error / Exception Handling
          1. 11.1.4.27.1 PKTDMA Exception Conditions
            1. 11.1.4.27.1.1 Descriptor Starvation
            2. 11.1.4.27.1.2 Protocol Errors
            3. 11.1.4.27.1.3 Dropped Packets
            4. 11.1.4.27.1.4 Long Packet
          2. 11.1.4.27.2 BCDMA Exception Conditions
            1. 11.1.4.27.2.1 Reception of EOL Delimiter
            2. 11.1.4.27.2.2 EOP Asserted Prematurely (Short Packet)
            3. 11.1.4.27.2.3 EOP Asserted Late (Long Packets)
            4. 11.1.4.27.2.4 Descriptor Starvation
    2. 11.2 Data Movement Subsystem (DMSS)
      1. 11.2.1 Data Movement Subsystem (DMSS)
        1. 11.2.1.1 DMSS Overview
        2. 11.2.1.2 DMSS Integration
          1. 11.2.1.2.1 DMSS Integration Attributes
          2. 11.2.1.2.2 DMSS Clocks
          3. 11.2.1.2.3 DMSS Resets
          4. 11.2.1.2.4 DMSS Interrupt Requests
          5. 11.2.1.2.5 DMSS L2G Interrupt Inputs
          6. 11.2.1.2.6 DMSS DMA Events
          7. 11.2.1.2.7 Global Event Map
          8. 11.2.1.2.8 PSI-L System Thread Map
        3. 11.2.1.3 DMSS Functional Description
        4. 11.2.1.4 DMSS Interrupt Configuration
          1. 11.2.1.4.1 DMSS Event and Interrupt Flow
            1. 11.2.1.4.1.1 DMSS Interrupt Description
        5. 11.2.1.5 DMSS Top-Level Registers
          1. 11.2.1.5.1 DMASS_PKTDMA_0 Registers
          2. 11.2.1.5.2 DMASS_BCDMA_0 Registers
      2. 11.2.2 Ring Accelerator (RINGACC)
        1. 11.2.2.1 RINGACC Overview
          1. 11.2.2.1.1 RINGACC Features
          2. 11.2.2.1.2 RINGACC Not Supported Features
          3. 11.2.2.1.3 RINGACC Parameters
        2. 11.2.2.2 RINGACC Integration
          1. 11.2.2.2.1 RINGACC Integration Attributes
          2. 11.2.2.2.2 RINGACC Clocks
          3. 11.2.2.2.3 RINGACC Resets
          4. 11.2.2.2.4 RINGACC Interrupt Requests
          5. 11.2.2.2.5 RINGACC Outbound Events
        3. 11.2.2.3 RINGACC Functional Description
          1. 11.2.2.3.1 Block Diagram
            1. 11.2.2.3.1.1  Configuration Registers
            2. 11.2.2.3.1.2  Source Command FIFO
            3. 11.2.2.3.1.3  Source Write Data FIFO
            4. 11.2.2.3.1.4  Source Read Data FIFO
            5. 11.2.2.3.1.5  Source Write Status FIFO
            6. 11.2.2.3.1.6  Main State Machine
            7. 11.2.2.3.1.7  Destination Command FIFO
            8. 11.2.2.3.1.8  Destination Write Data FIFO
            9. 11.2.2.3.1.9  Destination Read Data FIFO
            10. 11.2.2.3.1.10 Destination Write Status FIFO
          2. 11.2.2.3.2 RINGACC Functional Operation
            1. 11.2.2.3.2.1 Queue Modes
              1. 11.2.2.3.2.1.1 Ring Mode
              2. 11.2.2.3.2.1.2 Messaging Mode
              3. 11.2.2.3.2.1.3 Credentials Mode
              4. 11.2.2.3.2.1.4 Peek Support
              5. 11.2.2.3.2.1.5 Index Register Operation
            2. 11.2.2.3.2.2 VBUSM Target Ring Operations
            3. 11.2.2.3.2.3 VBUSM Initiator Interface Command ID Selection
            4. 11.2.2.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 11.2.2.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 11.2.2.3.2.6 Host Doorbell Access
            7. 11.2.2.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 11.2.2.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 11.2.2.3.2.9 Mismatched Element Size Handling
          3. 11.2.2.3.3 Events
          4. 11.2.2.3.4 Bus Error Handling
          5. 11.2.2.3.5 Monitors
            1. 11.2.2.3.5.1 Threshold Monitor
            2. 11.2.2.3.5.2 Watermark Monitor
            3. 11.2.2.3.5.3 Starvation Monitor
            4. 11.2.2.3.5.4 Statistics Monitor
            5. 11.2.2.3.5.5 Overflow
            6. 11.2.2.3.5.6 Ring Update Port
            7. 11.2.2.3.5.7 Tracing
        4. 11.2.2.4 RINGACC Registers
          1. 11.2.2.4.1 DMASS_RINGACC_0 Registers
      3. 11.2.3 Secure Proxy (SEC_PROXY)
        1. 11.2.3.1 Secure Proxy Overview
          1. 11.2.3.1.1 Secure Proxy Features
          2. 11.2.3.1.2 Secure Proxy Parameters
          3. 11.2.3.1.3 Secure Proxy Not Supported Features
        2. 11.2.3.2 Secure Proxy Integration
          1. 11.2.3.2.1 Secure Proxy Integration Attributes
          2. 11.2.3.2.2 Secure Proxy Clocks
          3. 11.2.3.2.3 Secure Proxy Resets
          4. 11.2.3.2.4 Secure Proxy Interrupt Requests
          5. 11.2.3.2.5 Secure Proxy DMA Events
        3. 11.2.3.3 Secure Proxy Functional Description
          1. 11.2.3.3.1  Targets
          2. 11.2.3.3.2  Buffers
          3. 11.2.3.3.3  Proxy Thread Sizes
          4. 11.2.3.3.4  Proxy Thread Interleaving
          5. 11.2.3.3.5  Proxy States
          6. 11.2.3.3.6  Proxy Host Access
          7. 11.2.3.3.7  Permission Inheritance
          8. 11.2.3.3.8  Resource Association
          9. 11.2.3.3.9  Direction
          10. 11.2.3.3.10 Threshold Events
          11. 11.2.3.3.11 Error Events
          12. 11.2.3.3.12 Bus Error and Credits
          13. 11.2.3.3.13 Debug
        4. 11.2.3.4 Secure Proxy Registers
          1. 11.2.3.4.1 DMASS_SEC_PROXY_0 Registers
      4. 11.2.4 Interrupt Aggregator (INTAGGR)
        1. 11.2.4.1 INTAGGR Overview
          1. 11.2.4.1.1 INTAGGR Features
          2. 11.2.4.1.2 INTAGGR Parameters
        2. 11.2.4.2 INTAGGR Integration
          1. 11.2.4.2.1 INTAGGR Integration Attributes
          2. 11.2.4.2.2 INTAGGR Clocks
          3. 11.2.4.2.3 INTAGGR Resets
          4. 11.2.4.2.4 INTAGGR Interrupt Requests
          5. 11.2.4.2.5 INTAGGR DMA Events
        3. 11.2.4.3 INTAGGR Functional Description
          1. 11.2.4.3.1 Submodule Descriptions
          2. 11.2.4.3.2 General Functionality
        4. 11.2.4.4 INTAGGR Registers
          1. 11.2.4.4.1 DMASS_INTAGGR_0 Registers
      5. 11.2.5 Packet Streaming Interface Link (PSI-L)
        1. 11.2.5.1 PSI-L Overview
        2. 11.2.5.2 PSI-L Functional Description
          1. 11.2.5.2.1 PSI-L Introduction
          2. 11.2.5.2.2 PSI-L Operation
        3. 11.2.5.3 PSI-L Configuration Registers
          1. 11.2.5.3.1 DMASS_PSILCFG_0 Registers
          2. 11.2.5.3.2 DMASS_PSILSS_0 Registers
    3. 11.3 Peripheral DMA (PDMA)
      1. 11.3.1 PDMA Controller
        1. 11.3.1.1 PDMA Overview
          1. 11.3.1.1.1 PDMA Features
            1. 11.3.1.1.1.1 PDMA0 Features
            2. 11.3.1.1.1.2 PDMA1 Features
        2. 11.3.1.2 PDMA Integration
          1. 11.3.1.2.1 PDMA Integration in MAIN Domain
        3. 11.3.1.3 PDMA Functional Description
          1. 11.3.1.3.1 PDMA Functional Blocks
            1. 11.3.1.3.1.1 Scheduler
            2. 11.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 11.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 11.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 11.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 11.3.1.3.2 PDMA General Functionality
            1. 11.3.1.3.2.1 Operational States
            2. 11.3.1.3.2.2 Clock Stop
            3. 11.3.1.3.2.3 Emulation Control
          3. 11.3.1.3.3 PDMA Events and Flow Control
            1. 11.3.1.3.3.1 Channel Types
              1. 11.3.1.3.3.1.1 X-Y FIFO Mode
              2. 11.3.1.3.3.1.2 MCAN Mode
            2. 11.3.1.3.3.2 Channel Triggering
            3. 11.3.1.3.3.3 Completion Events
          4. 11.3.1.3.4 PDMA Transmit Operation
            1. 11.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 11.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 11.3.1.3.4.3 Destination Channel Initialization
              1. 11.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 11.3.1.3.4.3.2 Static Transfer Request Setup
              3. 11.3.1.3.4.3.3 PSI-L Destination Thread Enables
            4. 11.3.1.3.4.4 Data Transfer
              1. 11.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 11.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 11.3.1.3.4.4.2 MCAN Mode Channel
                1. 11.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 11.3.1.3.4.4.3 AASRC Mode Channel
            5. 11.3.1.3.4.5 Tx Pause
            6. 11.3.1.3.4.6 Tx Teardown
            7. 11.3.1.3.4.7 Tx Channel Reset
            8. 11.3.1.3.4.8 Tx Debug/State Registers
          5. 11.3.1.3.5 PDMA Receive Operation
            1. 11.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 11.3.1.3.5.2 Source Channel Initialization
              1. 11.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 11.3.1.3.5.2.2 Static Transfer Request Setup
              3. 11.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 11.3.1.3.5.3 Data Transfer
              1. 11.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 11.3.1.3.5.3.2 MCAN Mode Channel
                1. 11.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 11.3.1.3.5.3.3 AASRC Mode Channel
            4. 11.3.1.3.5.4 Rx Pause
            5. 11.3.1.3.5.5 Rx Teardown
            6. 11.3.1.3.5.6 Rx Channel Reset
            7. 11.3.1.3.5.7 Rx Debug/State Register
          6. 11.3.1.3.6 PDMA ECC Support
        4. 11.3.1.4 PDMA Registers
          1. 11.3.1.4.1 PDMA0 ECC Registers
          2. 11.3.1.4.2 PDMA1 ECC Registers
          3. 11.3.1.4.3 PDMA PSI-L TX Configuration Registers
          4. 11.3.1.4.4 PDMA PSI-L RX Configuration Registers
      2. 11.3.2 PDMA Sources
        1. 11.3.2.1 PDMA0 Event Map
        2. 11.3.2.2 PDMA1 Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MAIN Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in MCU Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 4200
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in MCU Domain
          2. 12.1.3.3.2 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.4.1 MCSPI Overview
          1. 12.1.4.1.1 SPI Features
          2. 12.1.4.1.2 SPI Not Supported Features
        2. 12.1.4.2 MCSPI Environment
          1. 12.1.4.2.1 Basic MCSPI Pins for Controller Mode
          2. 12.1.4.2.2 Basic MCSPI Pins for Peripheral Mode
          3. 12.1.4.2.3 MCSPI Protocol and Data Format
            1. 12.1.4.2.3.1 Transfer Format
          4. 12.1.4.2.4 MCSPI in Controller Mode
          5. 12.1.4.2.5 MCSPI in Peripheral Mode
        3. 12.1.4.3 MCSPI Integration
          1. 12.1.4.3.1 MCSPI Integration in MCU Domain
          2. 12.1.4.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.4.4 MCSPI Functional Description
          1. 12.1.4.4.1 SPI Block Diagram
          2. 12.1.4.4.2 MCSPI Reset
          3. 12.1.4.4.3 MCSPI Controller Mode
            1. 12.1.4.4.3.1 Controller Mode Features
            2. 12.1.4.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.4.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.4.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.4.4.3.5 Single-Channel Controller Mode
              1. 12.1.4.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.4.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.4.4.3.5.3 Turbo Mode
            6. 12.1.4.4.3.6 Start-Bit Mode
            7. 12.1.4.4.3.7 Chip-Select Timing Control
            8. 12.1.4.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.4.4.3.8.1 Clock Ratio Granularity
          4. 12.1.4.4.4 MCSPI Peripheral Mode
            1. 12.1.4.4.4.1 Dedicated Resources
            2. 12.1.4.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.4.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.4.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.4.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.4.4.6 MCSPI FIFO Buffer Management
            1. 12.1.4.4.6.1 Buffer Almost Full
            2. 12.1.4.4.6.2 Buffer Almost Empty
            3. 12.1.4.4.6.3 End of Transfer Management
            4. 12.1.4.4.6.4 Multiple MCSPI Word Access
            5. 12.1.4.4.6.5 First MCSPI Word Delay
          7. 12.1.4.4.7 MCSPI Interrupts
            1. 12.1.4.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.4.4.7.1.1 TXx_EMPTY
              2. 12.1.4.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.1.3 RXx_ FULL
              4. 12.1.4.4.7.1.4 End Of Word Count
            2. 12.1.4.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.4.4.7.2.1 TXx_EMPTY
              2. 12.1.4.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.2.3 RXx_FULL
              4. 12.1.4.4.7.2.4 RX0_OVERFLOW
              5. 12.1.4.4.7.2.5 End Of Word Count
            3. 12.1.4.4.7.3 Interrupt-Driven Operation
            4. 12.1.4.4.7.4 Polling
          8. 12.1.4.4.8 MCSPI DMA Requests
          9. 12.1.4.4.9 MCSPI Power Saving Management
            1. 12.1.4.4.9.1 Normal Mode
            2. 12.1.4.4.9.2 Idle Mode
              1. 12.1.4.4.9.2.1 Force-Idle Mode
        5. 12.1.4.5 MCSPI Programming Guide
          1. 12.1.4.5.1 MCSPI Global Initialization
            1. 12.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.4.5.1.2 MCSPI Global Initialization
              1. 12.1.4.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.4.5.2 MCSPI Operational Mode Configuration
            1. 12.1.4.5.2.1 MCSPI Operational Modes
              1. 12.1.4.5.2.1.1 Common Transfer Sequence
              2. 12.1.4.5.2.1.2 End of Transfer Sequences
              3. 12.1.4.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.4.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.4.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.4.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.4.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.4.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.4.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.4.5.2.1.7 Peripheral Receive-Only
              8. 12.1.4.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.4.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.4.5.2.1.8.5 Transmit-Only
                6. 12.1.4.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.4.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.4.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.4.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.4.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.4.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.4.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.4.6 MCSPI Registers
      5. 12.1.5 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.5.1 UART Overview
          1. 12.1.5.1.1 UART Features
          2. 12.1.5.1.2 IrDA Features
          3. 12.1.5.1.3 CIR Features
          4. 12.1.5.1.4 UART Not Supported Features
        2. 12.1.5.2 UART Environment
          1. 12.1.5.2.1 UART Functional Interfaces
            1. 12.1.5.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.5.2.1.2 UART Interface Description
            3. 12.1.5.2.1.3 UART Protocol and Data Format
            4. 12.1.5.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.5.2.2 RS-485 Functional Interfaces
            1. 12.1.5.2.2.1 System Using RS-485 Communication
            2. 12.1.5.2.2.2 RS-485 Interface Description
          3. 12.1.5.2.3 IrDA Functional Interfaces
            1. 12.1.5.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.5.2.3.2 IrDA Interface Description
            3. 12.1.5.2.3.3 IrDA Protocol and Data Format
              1. 12.1.5.2.3.3.1 SIR Mode
                1. 12.1.5.2.3.3.1.1 Frame Format
                2. 12.1.5.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.5.2.3.3.1.3 Abort Sequence
                4. 12.1.5.2.3.3.1.4 Pulse Shaping
                5. 12.1.5.2.3.3.1.5 Encoder
                6. 12.1.5.2.3.3.1.6 Decoder
                7. 12.1.5.2.3.3.1.7 IR Address Checking
              2. 12.1.5.2.3.3.2 SIR Free-Format Mode
              3. 12.1.5.2.3.3.3 MIR Mode
                1. 12.1.5.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.5.2.3.3.3.2 SIP Generation
              4. 12.1.5.2.3.3.4 FIR Mode
          4. 12.1.5.2.4 CIR Functional Interfaces
            1. 12.1.5.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.5.2.4.2 CIR Interface Description
            3. 12.1.5.2.4.3 CIR Protocol and Data Format
              1. 12.1.5.2.4.3.1 Carrier Modulation
              2. 12.1.5.2.4.3.2 Pulse Duty Cycle
              3. 12.1.5.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.5.3 UART Integration
          1. 12.1.5.3.1 UART Integration in MCU Domain
          2. 12.1.5.3.2 UART Integration in MAIN Domain
        4. 12.1.5.4 UART Functional Description
          1. 12.1.5.4.1 UART Block Diagram
          2. 12.1.5.4.2 UART Clock Configuration
          3. 12.1.5.4.3 UART Software Reset
            1. 12.1.5.4.3.1 Independent TX/RX
          4. 12.1.5.4.4 UART Power Management
            1. 12.1.5.4.4.1 UART Mode Power Management
              1. 12.1.5.4.4.1.1 Module Power Saving
              2. 12.1.5.4.4.1.2 System Power Saving
            2. 12.1.5.4.4.2 IrDA Mode Power Management
              1. 12.1.5.4.4.2.1 Module Power Saving
              2. 12.1.5.4.4.2.2 System Power Saving
            3. 12.1.5.4.4.3 CIR Mode Power Management
              1. 12.1.5.4.4.3.1 Module Power Saving
              2. 12.1.5.4.4.3.2 System Power Saving
            4. 12.1.5.4.4.4 Local Power Management
          5. 12.1.5.4.5 UART Interrupt Requests
            1. 12.1.5.4.5.1 UART Mode Interrupt Management
              1. 12.1.5.4.5.1.1 UART Interrupts
              2. 12.1.5.4.5.1.2 Wake-Up Interrupt
            2. 12.1.5.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.5.4.5.2.1 IrDA Interrupts
              2. 12.1.5.4.5.2.2 Wake-Up Interrupts
            3. 12.1.5.4.5.3 CIR Mode Interrupt Management
              1. 12.1.5.4.5.3.1 CIR Interrupts
              2. 12.1.5.4.5.3.2 Wake-Up Interrupts
          6. 12.1.5.4.6 UART FIFO Management
            1. 12.1.5.4.6.1 FIFO Trigger
              1. 12.1.5.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.5.4.6.1.2 Receive FIFO Trigger
            2. 12.1.5.4.6.2 FIFO Interrupt Mode
            3. 12.1.5.4.6.3 FIFO Polled Mode Operation
            4. 12.1.5.4.6.4 FIFO DMA Mode Operation
              1. 12.1.5.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.5.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.5.4.6.4.3 DMA Transmission
              4. 12.1.5.4.6.4.4 DMA Reception
          7. 12.1.5.4.7 UART Mode Selection
            1. 12.1.5.4.7.1 Register Access Modes
              1. 12.1.5.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.5.4.7.1.2 Register Access Submode
              3. 12.1.5.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.5.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.5.4.7.2.1 Registers Available for the UART Function
              2. 12.1.5.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.5.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.5.4.8 UART Protocol Formatting
            1. 12.1.5.4.8.1 UART Mode
              1. 12.1.5.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.5.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.1.3 UART Data Formatting
                1. 12.1.5.4.8.1.3.1 Frame Formatting
                2. 12.1.5.4.8.1.3.2 Hardware Flow Control
                3. 12.1.5.4.8.1.3.3 Software Flow Control
                  1. 1.5.4.8.1.3.3.1 Receive (RX)
                  2. 1.5.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.5.4.8.1.3.4 Autobauding Modes
                5. 12.1.5.4.8.1.3.5 Error Detection
                6. 12.1.5.4.8.1.3.6 Overrun During Receive
                7. 12.1.5.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.5.4.8.1.3.7.1 Time-Out Counter
                  2. 1.5.4.8.1.3.7.2 Break Condition
            2. 12.1.5.4.8.2 RS-485 Mode
              1. 12.1.5.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.5.4.8.3 IrDA Mode
              1. 12.1.5.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.5.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.3.3 IrDA Data Formatting
                1. 12.1.5.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.5.4.8.3.3.2  IrDA Reception Control
                3. 12.1.5.4.8.3.3.3  IR Address Checking
                4. 12.1.5.4.8.3.3.4  Frame Closing
                5. 12.1.5.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.5.4.8.3.3.6  Error Detection
                7. 12.1.5.4.8.3.3.7  Underrun During Transmission
                8. 12.1.5.4.8.3.3.8  Overrun During Receive
                9. 12.1.5.4.8.3.3.9  Status FIFO
                10. 12.1.5.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.5.4.8.3.3.11 Time-guard
              4. 12.1.5.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.5.4.8.3.4.1 Abort Sequence
                2. 12.1.5.4.8.3.4.2 Pulse Shaping
                3. 12.1.5.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.5.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.5.4.8.4 CIR Mode
              1. 12.1.5.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.5.4.8.4.2 CIR Data Formatting
                1. 12.1.5.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.5.4.8.4.2.2 CIR Transmission
                3. 12.1.5.4.8.4.2.3 CIR Reception
        5. 12.1.5.5 UART Programming Guide
          1. 12.1.5.5.1 UART Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 UART Module Global Initialization
          2. 12.1.5.5.2 UART Mode selection
          3. 12.1.5.5.3 UART Submode selection
          4. 12.1.5.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.5.5.4.1 DMA mode Settings
            2. 12.1.5.5.4.2 FIFO Trigger Settings
          5. 12.1.5.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.5.5.5.1 Baud rate settings
            2. 12.1.5.5.5.2 Interrupt settings
            3. 12.1.5.5.5.3 Protocol settings
            4. 12.1.5.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.5.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.5.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.5.5.6.1 Hardware Flow Control Configuration
            2. 12.1.5.5.6.2 Software Flow Control Configuration
          7. 12.1.5.5.7 IrDA Programming Model
            1. 12.1.5.5.7.1 SIR mode
              1. 12.1.5.5.7.1.1 Receive
              2. 12.1.5.5.7.1.2 Transmit
            2. 12.1.5.5.7.2 MIR mode
              1. 12.1.5.5.7.2.1 Receive
              2. 12.1.5.5.7.2.2 Transmit
            3. 12.1.5.5.7.3 FIR mode
              1. 12.1.5.5.7.3.1 Receive
              2. 12.1.5.5.7.3.2 Transmit
        6. 12.1.5.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet Switch (CPSW3G)
        1. 12.2.1.1 CPSW0 Overview
          1. 12.2.1.1.1 CPSW0 Features
          2. 12.2.1.1.2 CPSW0 Not Supported Features
          3. 12.2.1.1.3 CPSW Terminology
        2. 12.2.1.2 CPSW0 Environment
          1. 12.2.1.2.1 CPSW0 RMII Interface
          2. 12.2.1.2.2 CPSW0 RGMII Interface
        3. 12.2.1.3 CPSW0 Integration
        4. 12.2.1.4 CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_3G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1  Multicast Address Table Entry
                2. 12.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 12.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 12.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 12.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 12.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 12.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 12.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 12.2.1.4.6.1.9.9  EtherType Table Entry
                10. 12.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 12.2.1.4.6.1.9.11 IPv6 Table Entry High
                12. 12.2.1.4.6.1.9.12 IPv6 Table Entry Low
              10. 12.2.1.4.6.1.10 Multicast Address
                1. 12.2.1.4.6.1.10.1 Multicast Ranges
              11. 12.2.1.4.6.1.11 Aging and Auto Aging
              12. 12.2.1.4.6.1.12 ALE Policing and Classification
                1. 12.2.1.4.6.1.12.1 ALE Policing
                2. 12.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 12.2.1.4.6.1.12.3 ALE Classification
                  1. 2.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping
              13. 12.2.1.4.6.1.13 Mirroring
              14. 12.2.1.4.6.1.14 Trunking
              15. 12.2.1.4.6.1.15 DSCP
              16. 12.2.1.4.6.1.16 Packet Forwarding Processes
                1. 12.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.16.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.16.3 Egress Process
                4. 12.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 12.2.1.4.6.1.17 VLAN Aware Mode
              18. 12.2.1.4.6.1.18 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 12.2.1.4.6.10.1.1 CRC Insertion
                2. 12.2.1.4.6.10.1.2 MTXER
                3. 12.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 12.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 12.2.1.4.6.10.1.5 Back Off
                6. 12.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 12.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.1.4.6.18.8  Rx Cut Thru with No Delay
              9. 12.2.1.4.6.18.9  Rx Cut Thru with Delay
              10. 12.2.1.4.6.18.10 Rx Cut Thru Store-and-Forward
              11. 12.2.1.4.6.18.11 Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.11.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.1.4.6.18.11.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.1.4.6.18.11.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.1.4.6.18.11.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.1.4.6.18.11.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.1.4.6.18.11.6  Collisions (Offset = 3A048h)
                7. 12.2.1.4.6.18.11.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.1.4.6.18.11.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.1.4.6.18.11.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.1.4.6.18.11.10 Late Collisions (Offset = 3A058h)
                11. 12.2.1.4.6.18.11.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.1.4.6.18.11.12 Tx Octets (Offset = 3A064h)
                13. 12.2.1.4.6.18.11.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.1.4.6.18.11.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 12.2.1.4.6.18.11.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.1.4.6.18.11.16 IET Transmit Merge Hold Count (Offset = 3A150h)
                17. 12.2.1.4.6.18.11.17 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                18. 12.2.1.4.6.18.11.18 Tx CRC Errors
                19. 12.2.1.4.6.18.11.19 Tx Cut Thru
                20. 12.2.1.4.6.18.11.20 Tx Cut Thru Store-and-Forward
              12. 12.2.1.4.6.18.12 Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.12.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.1.4.6.18.12.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.1.4.6.18.12.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.1.4.6.18.12.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.1.4.6.18.12.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.1.4.6.18.12.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.1.4.6.18.12.7 Net Octets (Offset = 3A080h)
              13. 12.2.1.4.6.18.13 4714
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 4742
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_3G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_3G Ingress)
            3. 12.2.1.4.8.3 Cut-Thru
              1. 12.2.1.4.8.3.1 Host Port Cut-Thru Operations
              2. 12.2.1.4.8.3.2 Cut-Thru Error Packets
            4. 12.2.1.4.8.4 Port Speed
            5. 12.2.1.4.8.5 CPPI Checksum Offload
              1. 12.2.1.4.8.5.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.5.1.1 IPV4 UDP
                2. 12.2.1.4.8.5.1.2 IPV4 TCP
                3. 12.2.1.4.8.5.1.3 IPV6 UDP
                4. 12.2.1.4.8.5.1.4 IPV6 TCP
            6. 12.2.1.4.8.6 CPPI Receive Checksum Offload
            7. 12.2.1.4.8.7 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 CPSW0 Registers
          1. 12.2.1.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  CPSW0_MDIO Registers
          3. 12.2.1.6.3  CPSW0_CPTS Registers
          4. 12.2.1.6.4  CPSW0_CONTROL Registers
          5. 12.2.1.6.5  CPSW0_CPINT Registers
          6. 12.2.1.6.6  CPSW0_RAM Registers
          7. 12.2.1.6.7  CPSW0_STAT0 Registers
          8. 12.2.1.6.8  CPSW0_STATN Registers
          9. 12.2.1.6.9  CPSW0_ALE Registers
          10. 12.2.1.6.10 CPSW0_PCSR Registers
          11. 12.2.1.6.11 CPSW0_ECC Registers
      2. 12.2.2 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.2.1 PCIe Subsystem Overview
          1. 12.2.2.1.1 PCIe Subsystem Features
          2. 12.2.2.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.2.2 PCIe Subsystem Environment
        3. 12.2.2.3 PCIe Subsystem Integration
        4. 12.2.2.4 PCIe Subsystem Functional Description
          1. 12.2.2.4.1  PCIe Subsystem Block Diagram
            1. 12.2.2.4.1.1 PCIe PHY Interface
              1. 12.2.2.4.1.1.1 PCIe Core Module
            2. 12.2.2.4.1.2 Custom Logic
          2. 12.2.2.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.2.4.2.1 PCIe Conventional Reset
            2. 12.2.2.4.2.2 PCIe Function Level Reset
            3. 12.2.2.4.2.3 PCIe Reset Isolation
              1. 12.2.2.4.2.3.1 Root Complex Reset with Device Not Reset
              2. 12.2.2.4.2.3.2 Device Reset with Root Complex Not Reset
              3. 12.2.2.4.2.3.3 End Point Device Reset with Root Complex Not Reset
              4. 12.2.2.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.2.4.2.4 PCIe Reset Limitations
            5. 12.2.2.4.2.5 PCIe Reset Requirements
          3. 12.2.2.4.3  PCIe Subsystem Power Management
            1. 12.2.2.4.3.1 CBA Power Management
          4. 12.2.2.4.4  PCIe Subsystem Interrupts
            1. 12.2.2.4.4.1 Interrupts Aggregation
            2. 12.2.2.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.2.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.2.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.2.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.2.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.2.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.2.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.2.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.2.4.4.3.5 PTM Valid Interrupt
            4. 12.2.2.4.4.4 Interrupt Generation in RC Mode
            5. 12.2.2.4.4.5 Interrupt Reception in RC Mode
              1. 12.2.2.4.4.5.1 PCIe Legacy Interrupt Reception in RC Mode
              2. 12.2.2.4.4.5.2 MSI/MSI-X Interrupt Reception in RC Mode
              3. 12.2.2.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.2.4.4.6 Common Interrupt Reception in RC and EP Modes
              1. 12.2.2.4.4.6.1 PCIe Local Interrupt
              2. 12.2.2.4.4.6.2 PHY Interrupt
              3. 12.2.2.4.4.6.3 Link down Interrupt
              4. 12.2.2.4.4.6.4 Transaction Error Interrupts
              5. 12.2.2.4.4.6.5 Power Management Event Interrupt
            7. 12.2.2.4.4.7 ECC Aggregator Interrupts
            8. 12.2.2.4.4.8 CPTS Interrupt
          5. 12.2.2.4.5  PCIe Subsystem DMA Support
            1. 12.2.2.4.5.1 PCIe DMA Support in RC Mode
            2. 12.2.2.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.2.4.6  PCIe Subsystem Transactions
            1. 12.2.2.4.6.1 PCIe Supported Transactions
            2. 12.2.2.4.6.2 PCIe Transaction Limitations
          7. 12.2.2.4.7  PCIe Subsystem Address Translation
            1. 12.2.2.4.7.1 PCIe Inbound Address Translation
              1. 12.2.2.4.7.1.1 Root Complex Inbound PCIe to AXI Address Translation
              2. 12.2.2.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.2.4.7.2 PCIe Outbound Address Translation
              1. 12.2.2.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.2.4.8  PCIe Subsystem Quality-of-Service (QoS)
          9. 12.2.2.4.9  PCIe Subsystem Precision Time Measurement (PTM)
          10. 12.2.2.4.10 PCIe Subsystem Loopback
            1. 12.2.2.4.10.1 PCIe Loopback
              1. 12.2.2.4.10.1.1 PCIe Loopback Initiator Mode
              2. 12.2.2.4.10.1.2 PCIe Loopback Target Mode
          11. 12.2.2.4.11 PCIe Subsystem Error Handling
          12. 12.2.2.4.12 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.2.4.12.1 ECC Aggregators
            2. 12.2.2.4.12.2 RAM ECC Inversion
        5. 12.2.2.5 PCIe Subsystem Registers
          1. 12.2.2.5.1 PCIE Registers
      3. 12.2.3 Serializer/Deserializer (SerDes)
        1. 12.2.3.1 SerDes Overview
          1. 12.2.3.1.1 SerDes Features
          2. 12.2.3.1.2 Not Supported Features
          3. 12.2.3.1.3 Industry Standards Compatibility
        2. 12.2.3.2 SerDes Environment
          1. 12.2.3.2.1 SerDes I/Os
        3. 12.2.3.3 SerDes Integration
          1. 12.2.3.3.1 WIZ Settings
            1. 12.2.3.3.1.1 Interface Selection
            2. 12.2.3.3.1.2 Internal Reference Clock Selection
        4. 12.2.3.4 SerDes Functional Description
          1. 12.2.3.4.1 SerDes Block Diagram
      4. 12.2.4 Universal Serial Bus Subsystem (USBSS)
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
          1. 12.2.4.2.1 USB I/Os
          2. 12.2.4.2.2 USB Subsystem Application
          3. 12.2.4.2.3 VBUS Sense
        3. 12.2.4.3 USB Integration
          1. 12.2.4.3.1 Resets, Interrupts, and Clocks
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Controller Reset
          2. 12.2.4.4.2 Overcurrent Detection
          3. 12.2.4.4.3 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB_RAMS_INJ_CFG Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1.       4890
        2. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        3. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        4. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MAIN Domain
        5. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS Regions
            1. 12.3.1.4.2.1 FSS Regions Boot Size Configuration
          3. 12.3.1.4.3 FSS Memory Regions
        6. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Power Up/Down Sequence
        7. 12.3.1.6 FSS Registers
          1. 12.3.1.6.1 FSS Registers
          2. 12.3.1.6.2 FSS_FSAS_0 Registers
          3. 12.3.1.6.3 FSS_OSPI_0 Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1.       4911
        2. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        3. 12.3.2.2 OSPI Environment
        4. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MAIN Domain
        5. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
              4. 12.3.2.4.2.1.4 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        6. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        7. 12.3.2.6 OSPI Registers
      3. 12.3.3 General-Purpose Memory Controller (GPMC)
        1. 12.3.3.1 GPMC Overview
          1. 12.3.3.1.1 GPMC Features
          2. 12.3.3.1.2 GPMC Not Supported Features
        2. 12.3.3.2 GPMC Environment
          1. 12.3.3.2.1 GPMC Modes
          2. 12.3.3.2.2 GPMC I/O Signals
        3. 12.3.3.3 GPMC Integration
          1. 12.3.3.3.1 GPMC Integration in MAIN Domain
        4. 12.3.3.4 GPMC Functional Description
          1. 12.3.3.4.1  GPMC Block Diagram
          2. 12.3.3.4.2  GPMC Clock Configuration
          3. 12.3.3.4.3  GPMC Power Management
          4. 12.3.3.4.4  GPMC Interrupt Requests
          5. 12.3.3.4.5  GPMC Interconnect Port Interface
          6. 12.3.3.4.6  GPMC Address and Data Bus
            1. 12.3.3.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.3.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.3.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.3.4.7.2 Access Protocol
              1. 12.3.3.4.7.2.1 Supported Devices
              2. 12.3.3.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.3.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.3.4.7.3 External Signals
              1. 12.3.3.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.3.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.3.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.3.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.3.4.7.3.1.5 Wait With NAND Device
                6. 12.3.3.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.3.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.3.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.3.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.3.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.3.4.7.3.2 DIR Pin
              3. 12.3.3.4.7.3.3 Reset
              4. 12.3.3.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.3.4.7.4 Error Handling
          8. 12.3.3.4.8  GPMC Timing Setting
            1. 12.3.3.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.3.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.3.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.3.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.3.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.3.4.8.6  GPMC_CLKOUT
            7. 12.3.3.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.3.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.3.4.8.8.1 Access Time on Read Access
              2. 12.3.3.4.8.8.2 Access Time on Write Access
            9. 12.3.3.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.3.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.3.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.3.4.8.10 Bus Keeping Support
          9. 12.3.3.4.9  GPMC NOR Access Description
            1. 12.3.3.4.9.1 Asynchronous Access Description
              1. 12.3.3.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.3.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.3.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.3.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.3.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.3.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.3.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.3.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.3.4.9.2 Synchronous Access Description
              1. 12.3.3.4.9.2.1 Synchronous Single Read
              2. 12.3.3.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.3.4.9.2.3 Synchronous Single Write
              4. 12.3.3.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.3.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.3.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.3.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.3.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.3.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.3.4.9.4 Page and Burst Support
            5. 12.3.3.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.3.4.10 GPMC pSRAM Access Specificities
          11. 12.3.3.4.11 GPMC NAND Access Description
            1. 12.3.3.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.3.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.3.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.3.4.11.1.3 Command Latch Cycle
              4. 12.3.3.4.11.1.4 Address Latch Cycle
              5. 12.3.3.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.3.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.3.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.3.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.3.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.3.4.11.2 NAND Device-Ready Pin
              1. 12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.3.4.11.3 ECC Calculator
              1. 12.3.3.4.11.3.1 Hamming Code
                1. 12.3.3.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.3.4.11.3.1.2 ECC Enabling
                3. 12.3.3.4.11.3.1.3 ECC Computation
                4. 12.3.3.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.3.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.3.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.3.4.11.3.2 BCH Code
                1. 12.3.3.4.11.3.2.1 Requirements
                2. 12.3.3.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.3.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.3.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.3.4.11.3.2.2.3 Wrapping Modes
                    1. 3.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 3.4.11.3.2.2.3.2  Mode 0x1
                    3. 3.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 3.4.11.3.2.2.3.4  Mode 0x2
                    5. 3.4.11.3.2.2.3.5  Mode 0x3
                    6. 3.4.11.3.2.2.3.6  Mode 0x7
                    7. 3.4.11.3.2.2.3.7  Mode 0x8
                    8. 3.4.11.3.2.2.3.8  Mode 0x4
                    9. 3.4.11.3.2.2.3.9  Mode 0x9
                    10. 3.4.11.3.2.2.3.10 Mode 0x5
                    11. 3.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 3.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.3.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.3.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.3.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.3.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.3.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.3.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.3.4.11.4.2 Prefetch Mode
              3. 12.3.3.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.3.4.11.4.4 Write-Posting Mode
              5. 12.3.3.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.3.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.3.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.3.4.12 GPMC Memory Regions
          13. 12.3.3.4.13 GPMC Use Cases and Tips
            1. 12.3.3.4.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.3.4.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.3.4.13.1.2 Typical GPMC Setup
                1. 12.3.3.4.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.3.4.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.3.4.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.3.4.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.3.4.13.2.1 Supported Memories or Devices
                1. 12.3.3.4.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.3.4.13.2.1.2 NAND Interface Protocol
                3. 12.3.3.4.13.2.1.3 NOR Interface Protocol
                4. 12.3.3.4.13.2.1.4 Other Technologies
        5. 12.3.3.5 GPMC Basic Programming Model
          1. 12.3.3.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.3.5.2 GPMC Initialization
          3. 12.3.3.5.3 GPMC Configuration in NOR Mode
          4. 12.3.3.5.4 GPMC Configuration in NAND Mode
          5. 12.3.3.5.5 Set Memory Access
          6. 12.3.3.5.6 GPMC Timing Parameters
            1. 12.3.3.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.3.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.3.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.3.6 GPMC Registers
      4. 12.3.4 Error Location Module (ELM)
        1. 12.3.4.1 ELM Overview
          1. 12.3.4.1.1 ELM Features
          2. 12.3.4.1.2 ELM Not Supported Features
        2. 12.3.4.2 ELM Integration
          1. 12.3.4.2.1 ELM Integration in MAIN Domain
        3. 12.3.4.3 ELM Functional Description
          1. 12.3.4.3.1 ELM Software Reset
          2. 12.3.4.3.2 ELM Power Management
          3. 12.3.4.3.3 ELM Interrupt Requests
          4. 12.3.4.3.4 ELM Processing Initialization
          5. 12.3.4.3.5 ELM Processing Sequence
          6. 12.3.4.3.6 ELM Processing Completion
        4. 12.3.4.4 ELM Basic Programming Model
          1. 12.3.4.4.1 ELM Low-Level Programming Model
            1. 12.3.4.4.1.1 Processing Initialization
            2. 12.3.4.4.1.2 Read Results
            3. 12.3.4.4.1.3 5138
          2. 12.3.4.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.4.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.4.5 ELM Registers
      5. 12.3.5 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.5.1 MMCSD Overview
          1. 12.3.5.1.1 MMCSD Features
          2. 12.3.5.1.2 MMCSD Not Supported Features
        2. 12.3.5.2 MMCSD Environment
          1. 12.3.5.2.1 Protocol and Data Format
            1. 12.3.5.2.1.1 Protocol
            2. 12.3.5.2.1.2 Data Format
              1. 12.3.5.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.5.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.5.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.5.3 MMCSD Integration
          1. 12.3.5.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.5.4 MMCSD Functional Description
          1. 12.3.5.4.1 Block Diagram
          2. 12.3.5.4.2 Memory Regions
          3. 12.3.5.4.3 Interrupt Requests
          4. 12.3.5.4.4 ECC Support
            1. 12.3.5.4.4.1 ECC Aggregator
          5. 12.3.5.4.5 Advanced DMA
        5. 12.3.5.5 MMCSD Programming Guide
          1. 12.3.5.5.1 Sequences
            1. 12.3.5.5.1.1  SD Card Detection
            2. 12.3.5.5.1.2  SD Clock Control
              1. 12.3.5.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.5.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.5.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.5.5.1.3  SD Bus Power Control
            4. 12.3.5.5.1.4  Changing Bus Width
            5. 12.3.5.5.1.5  Timeout Setting on DAT Line
            6. 12.3.5.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.5.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.5.5.1.7  SD Transaction Generation
              1. 12.3.5.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.5.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.5.5.1.7.1.3 5178
              2. 12.3.5.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.2.1 Not using DMA
                2. 12.3.5.5.1.7.2.2 Using SDMA
                3. 12.3.5.5.1.7.2.3 Using ADMA
            8. 12.3.5.5.1.8  Abort Transaction
              1. 12.3.5.5.1.8.1 Asynchronous Abort
              2. 12.3.5.5.1.8.2 Synchronous Abort
            9. 12.3.5.5.1.9  Changing Bus Speed Mode
            10. 12.3.5.5.1.10 Error Recovery
              1. 12.3.5.5.1.10.1 Error Interrupt Recovery
              2. 12.3.5.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.5.5.1.11 Wakeup Control (Optional)
            12. 12.3.5.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.5.5.1.12.1 Suspend Sequence
              2. 12.3.5.5.1.12.2 Resume Sequence
              3. 12.3.5.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.5.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.5.5.2 Driver Flow Sequence
            1. 12.3.5.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.5.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.5.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.5.5.2.2 Boot Operation
              1. 12.3.5.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.5.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.5.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.5.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.5.5.2.3.1 Sampling Clock Tuning
              2. 12.3.5.5.2.3.2 Tuning Modes
              3. 12.3.5.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.5.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.5.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.5.5.2.4.2 Task Issuance Sequence
              3. 12.3.5.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.5.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.5.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.5.6 MMCSD Registers
          1. 12.3.5.6.1 MMCSD0 Subsystem Registers
          2. 12.3.5.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.5.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.5.6.4 MMCSD0 Host Controller Registers
          5. 12.3.5.6.5 MMCSD1 Subsystem Registers
          6. 12.3.5.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.5.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.5.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Modular Controller Area Network (MCAN)
        1. 12.4.1.1 MCAN Overview
          1. 12.4.1.1.1 MCAN Features
          2. 12.4.1.1.2 MCAN Not Supported Features
        2. 12.4.1.2 MCAN Environment
          1. 12.4.1.2.1 CAN Network Basics
        3. 12.4.1.3 MCAN Integration
          1. 12.4.1.3.1 MCAN Integration in MAIN Domain
        4. 12.4.1.4 MCAN Functional Description
          1. 12.4.1.4.1  Module Clocking Requirements
          2. 12.4.1.4.2  Interrupt and DMA Requests
            1. 12.4.1.4.2.1 Interrupt Requests
            2. 12.4.1.4.2.2 DMA Requests
          3. 12.4.1.4.3  Operating Modes
            1. 12.4.1.4.3.1 Software Initialization
            2. 12.4.1.4.3.2 Normal Operation
            3. 12.4.1.4.3.3 CAN FD Operation
            4. 12.4.1.4.3.4 Transmitter Delay Compensation
              1. 12.4.1.4.3.4.1 Description
              2. 12.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.1.4.3.5 Restricted Operation Mode
            6. 12.4.1.4.3.6 Bus Monitoring Mode
            7. 12.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.1.4.3.8 Power Down (Sleep Mode)
              1. 12.4.1.4.3.8.1 External Clock Stop Mode
              2. 12.4.1.4.3.8.2 Suspend Mode
              3. 12.4.1.4.3.8.3 Wakeup request
            9. 12.4.1.4.3.9 Test Modes
              1. 12.4.1.4.3.9.1 Internal Loopback Mode
          4. 12.4.1.4.4  Timestamp Generation
            1. 12.4.1.4.4.1 External Timestamp Counter
          5. 12.4.1.4.5  Timeout Counter
          6. 12.4.1.4.6  ECC Support
            1. 12.4.1.4.6.1 ECC Wrapper
            2. 12.4.1.4.6.2 ECC Aggregator
          7. 12.4.1.4.7  Rx Handling
            1. 12.4.1.4.7.1 Acceptance Filtering
              1. 12.4.1.4.7.1.1 Range Filter
              2. 12.4.1.4.7.1.2 Filter for specific IDs
              3. 12.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.1.4.7.1.4 Standard Message ID Filtering
              5. 12.4.1.4.7.1.5 Extended Message ID Filtering
            2. 12.4.1.4.7.2 Rx FIFOs
              1. 12.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.1.4.7.3 Dedicated Rx Buffers
              1. 12.4.1.4.7.3.1 Rx Buffer Handling
            4. 12.4.1.4.7.4 Debug on CAN Support
          8. 12.4.1.4.8  Tx Handling
            1. 12.4.1.4.8.1 Transmit Pause
            2. 12.4.1.4.8.2 Dedicated Tx Buffers
            3. 12.4.1.4.8.3 Tx FIFO
            4. 12.4.1.4.8.4 Tx Queue
            5. 12.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.1.4.8.7 Transmit Cancellation
            8. 12.4.1.4.8.8 Tx Event Handling
          9. 12.4.1.4.9  FIFO Acknowledge Handling
          10. 12.4.1.4.10 Message RAM
            1. 12.4.1.4.10.1 Message RAM Configuration
            2. 12.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.1.4.10.3 Tx Buffer Element
            4. 12.4.1.4.10.4 Tx Event FIFO Element
            5. 12.4.1.4.10.5 Standard Message ID Filter Element
            6. 12.4.1.4.10.6 Extended Message ID Filter Element
        5. 12.4.1.5 MCAN Registers
          1. 12.4.1.5.1 MCAN Subsystem Registers
          2. 12.4.1.5.2 MCAN Core Registers
          3. 12.4.1.5.3 MCAN ECC Aggregator Registers
      2. 12.4.2 Enhanced Capture (ECAP) Module
        1. 12.4.2.1 ECAP Overview
          1. 12.4.2.1.1 ECAP Features
        2. 12.4.2.2 ECAP Environment
          1. 12.4.2.2.1 ECAP I/O Interface
        3. 12.4.2.3 ECAP Integration
          1. 12.4.2.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.2.4 ECAP Functional Description
          1. 12.4.2.4.1 Capture and APWM Operating Modes
            1. 12.4.2.4.1.1 ECAP Capture Mode Description
              1. 12.4.2.4.1.1.1 ECAP Event Prescaler
              2. 12.4.2.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.2.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.2.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.2.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.2.4.1.1.6 ECAP Interrupt Control
              7. 12.4.2.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.2.4.1.2 ECAP APWM Mode Operation
          2. 12.4.2.4.2 Summary of ECAP Functional Registers
        5. 12.4.2.5 ECAP Use Cases
          1. 12.4.2.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.2.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.2.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.2.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.2.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.2.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.2.5.5 Application of the APWM Mode
            1. 12.4.2.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.2.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.2.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.2.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.2.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.2.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.2.6 ECAP Registers
      3. 12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.3.1 EPWM Overview
          1. 12.4.3.1.1 EPWM Features
          2. 12.4.3.1.2 EPWM Not Supported Features
          3. 12.4.3.1.3 Multiple EPWM Module Details
        2. 12.4.3.2 EPWM Environment
        3. 12.4.3.3 EPWM Integration
          1. 12.4.3.3.1 EPWM Additional Integration Details
            1. 12.4.3.3.1.1 EPWM Tripzone Connectivity
            2. 12.4.3.3.1.2 Daisy-Chain Connectivity between EPWM Modules
            3. 12.4.3.3.1.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
            4. 12.4.3.3.1.4 EPWM Modules Time-Base Clock Gating
        4. 12.4.3.4 EPWM Functional Description
          1. 12.4.3.4.1  EPWM Submodule Features
            1. 12.4.3.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.3.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.3.4.2.1 Overview
            2. 12.4.3.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.3.4.2.3 Calculating PWM Period and Frequency
              1. 12.4.3.4.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.3.4.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.3.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.3.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.3.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.3.4.3.1 Overview
            2. 12.4.3.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.3.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.3.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.3.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.3.4.4.1 Overview
            2. 12.4.3.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.3.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.3.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.3.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.3.4.5.1 Overview
            2. 12.4.3.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.3.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.3.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.3.4.6.1 Overview
            2. 12.4.3.4.6.2 5369
            3. 12.4.3.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.3.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.3.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.3.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.3.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.3.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.3.4.7.1 Overview
            2. 12.4.3.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.3.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.3.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.3.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.3.4.8.1 Overview
            2. 12.4.3.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.3.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.3.4.8.4 Operation Overview of the EPWM SOCx Pulse Generator
          9. 12.4.3.4.9  EPWM Functional Register Groups
          10. 12.4.3.4.10 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.3.5 EPWM Registers
      4. 12.4.4 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.4.1 EQEP Overview
          1. 12.4.4.1.1 EQEP Features
          2. 12.4.4.1.2 EQEP Not Supported Features
        2. 12.4.4.2 EQEP Environment
          1. 12.4.4.2.1 EQEP I/O Interface
        3. 12.4.4.3 EQEP Integration
          1. 12.4.4.3.1 Device Specific EQEP Features
        4. 12.4.4.4 EQEP Functional Description
          1. 12.4.4.4.1 EQEP Inputs
          2. 12.4.4.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.4.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.4.4.2.1.1 Quadrature Count Mode
              2. 12.4.4.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.4.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.4.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.4.4.2.2 EQEP Input Polarity Selection
            3. 12.4.4.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.4.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.4.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.4.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.4.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.4.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.4.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.4.4.3.2 EQEP Position Counter Latch
              1. 12.4.4.4.3.2.1 Index Event Latch
              2. 12.4.4.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.4.4.3.3 EQEP Position Counter Initialization
            4. 12.4.4.4.3.4 EQEP Position-Compare Unit
          4. 12.4.4.4.4 EQEP Edge Capture Unit
          5. 12.4.4.4.5 EQEP Watchdog
          6. 12.4.4.4.6 Unit Timer Base
          7. 12.4.4.4.7 EQEP Interrupt Structure
          8. 12.4.4.4.8 Summary of EQEP Functional Registers
        5. 12.4.4.5 EQEP Registers
      5. 12.4.5 Fast Serial Interface (FSI)
        1. 12.4.5.1 FSI Overview
          1. 12.4.5.1.1 FSI Features
          2. 12.4.5.1.2 FSI Not Supported Featurs
        2. 12.4.5.2 FSI Environment
          1. 12.4.5.2.1 Signal Description
        3. 12.4.5.3 FSI Integration
          1. 12.4.5.3.1 FSI Interrupts
            1. 12.4.5.3.1.1 Transmitter Interrupts
            2. 12.4.5.3.1.2 Receiver Interrupts
            3. 12.4.5.3.1.3 Configuring Interrupts
            4. 12.4.5.3.1.4 Handling Interrupts
        4. 12.4.5.4 FSI Functional Description
          1. 12.4.5.4.1 FSI Functional Description
          2. 12.4.5.4.2 FSI Transmitter Module (FSI_TX)
            1. 12.4.5.4.2.1 Initialization
            2. 12.4.5.4.2.2 FSI_TX Clocking
            3. 12.4.5.4.2.3 Transmitting Frames
              1. 12.4.5.4.2.3.1 Software Triggered Frames
              2. 12.4.5.4.2.3.2 Ping Frame Generation
                1. 12.4.5.4.2.3.2.1 Automatic Ping Frames
                2. 12.4.5.4.2.3.2.2 Software Triggered Ping Frame
            4. 12.4.5.4.2.4 Transmit Buffer Management
            5. 12.4.5.4.2.5 CRC Submodule
            6. 12.4.5.4.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
            7. 12.4.5.4.2.7 Reset
          3. 12.4.5.4.3 FSI Receiver Module (FSI_RX)
            1. 12.4.5.4.3.1  Initialization
            2. 12.4.5.4.3.2  FSI_RX Clocking
            3. 12.4.5.4.3.3  Receiving Frames
            4. 12.4.5.4.3.4  Ping Frame Watchdog
            5. 12.4.5.4.3.5  Frame Watchdog
            6. 12.4.5.4.3.6  Delay Line Control
            7. 12.4.5.4.3.7  Buffer Management
            8. 12.4.5.4.3.8  CRC Submodule
            9. 12.4.5.4.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 12.4.5.4.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 12.4.5.4.3.11 FSI_RX Reset
          4. 12.4.5.4.4 Frame Format
            1. 12.4.5.4.4.1 FSI Frame Phases
            2. 12.4.5.4.4.2 Frame Types
              1. 12.4.5.4.4.2.1 Ping Frames
              2. 12.4.5.4.4.2.2 Error Frames
              3. 12.4.5.4.4.2.3 Data Frames
            3. 12.4.5.4.4.3 Multi-Lane Transmission
          5. 12.4.5.4.5 Flush Sequence
          6. 12.4.5.4.6 Internal Loopback
          7. 12.4.5.4.7 CRC Generation
          8. 12.4.5.4.8 ECC Module
          9. 12.4.5.4.9 FSI-SPI Compatibility Mode
            1. 12.4.5.4.9.1 Available SPI Modes
              1. 12.4.5.4.9.1.1 FSITX as SPI Controller, Transmit Only
                1. 12.4.5.4.9.1.1.1 Initialization
                2. 12.4.5.4.9.1.1.2 Operation
              2. 12.4.5.4.9.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 12.4.5.4.9.1.2.1 Initialization
                2. 12.4.5.4.9.1.2.2 Operation
              3. 12.4.5.4.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 12.4.5.4.9.1.3.1 Initialization
                2. 12.4.5.4.9.1.3.2 Operation
        5. 12.4.5.5 FSI Programing Guide
          1. 12.4.5.5.1 Establishing the Communication Link
            1. 12.4.5.5.1.1 Establishing the Communication Link from the Main Device
            2. 12.4.5.5.1.2 Establishing the Communication Link from the Remote Device
          2. 12.4.5.5.2 Register Protection
          3. 12.4.5.5.3 Emulation Mode
        6. 12.4.5.6 FSI Registers
          1. 12.4.5.6.1 FSITX Registers
          2. 12.4.5.6.2 FSIRX Registers
    5. 12.5 Timer Modules
      1. 12.5.1 Global Timebase Counter (GTC)
        1. 12.5.1.1 Global Timebase Counter (GTC)
          1. 12.5.1.1.1 GTC Overview
            1. 12.5.1.1.1.1 GTC Features
            2. 12.5.1.1.1.2 GTC Not Supported Features
          2. 12.5.1.1.2 GTC Integration
        2. 12.5.1.2 GTC Functional Description
          1. 12.5.1.2.1 GTC Block Diagram
          2. 12.5.1.2.2 GTC Counter
          3. 12.5.1.2.3 GTC Register Partitioning
        3. 12.5.1.3 GTC Registers
          1. 12.5.1.3.1  GTC_CFG0_GTC_PID Registers
          2. 12.5.1.3.2  GTC_CFG0_GTC_GTC_PID Registers
          3. 12.5.1.3.3  GTC_CFG0_GTC_PUSHEVT Registers
          4. 12.5.1.3.4  GTC_CFG1_GTC_CNTCR Registers
          5. 12.5.1.3.5  GTC_CFG1_GTC_CNTSR Registers
          6. 12.5.1.3.6  GTC_CFG1_GTC_CNTCV_LO Registers
          7. 12.5.1.3.7  GTC_CFG1_GTC_CNTCV_HI Registers
          8. 12.5.1.3.8  GTC_CFG1_GTC_CNTFID0 Registers
          9. 12.5.1.3.9  GTC_CFG1_GTC_CNTFID1 Registers
          10. 12.5.1.3.10 GTC_CFG2_GTC_CNTCVS_LO Registers
          11. 12.5.1.3.11 GTC_CFG2_GTC_CNTCVS_HI Registers
          12. 12.5.1.3.12 GTC_CFG3_GTC_CNTTIDR Registers
          13. 12.5.1.3.13 Access Table
      2. 12.5.2 RTI-Windowed Watchdog Timer (WWDT)
        1. 12.5.2.1 RTI Overview
          1. 12.5.2.1.1 RTI Features
          2. 12.5.2.1.2 RTI Not Supported Features
        2. 12.5.2.2 RTI Integration
          1. 12.5.2.2.1 RTI Integration in MCU Domain
          2. 12.5.2.2.2 RTI Integration in MAIN Domain
        3. 12.5.2.3 RTI Functional Description
          1. 12.5.2.3.1 RTI Digital Windowed Watchdog
            1. 12.5.2.3.1.1 RTI Debug Mode Behavior
            2. 12.5.2.3.1.2 RTI Low Power Mode Operation
          2. 12.5.2.3.2 RTI Digital Watchdog
          3. 12.5.2.3.3 RTI Counter Operation
        4. 12.5.2.4 RTI Registers
      3. 12.5.3 Timers
        1. 12.5.3.1 Timers Overview
          1. 12.5.3.1.1 Timers Features
          2. 12.5.3.1.2 Timers Not Supported Features
        2. 12.5.3.2 Timers Environment
          1. 12.5.3.2.1 Timer External System Interface
        3. 12.5.3.3 Timers Integration
          1. 12.5.3.3.1 Timers Integration in MCU Domain
          2. 12.5.3.3.2 Timers Integration in MAIN Domain
        4. 12.5.3.4 Timers Functional Description
          1. 12.5.3.4.1  Timer Block Diagram
          2. 12.5.3.4.2  Timer Power Management
            1. 12.5.3.4.2.1 Wake-Up Capability
          3. 12.5.3.4.3  Timer Software Reset
          4. 12.5.3.4.4  Timer Interrupts
          5. 12.5.3.4.5  Timer Mode Functionality
            1. 12.5.3.4.5.1 1-ms Tick Generation
          6. 12.5.3.4.6  Timer Capture Mode Functionality
          7. 12.5.3.4.7  Timer Compare Mode Functionality
          8. 12.5.3.4.8  Timer Prescaler Functionality
          9. 12.5.3.4.9  Timer Pulse-Width Modulation
          10. 12.5.3.4.10 Timer Counting Rate
          11. 12.5.3.4.11 Timer Under Emulation
          12. 12.5.3.4.12 Accessing Timer Registers
            1. 12.5.3.4.12.1 Writing to Timer Registers
              1. 12.5.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.5.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.5.3.4.12.2 Reading From Timer Counter Registers
              1. 12.5.3.4.12.2.1 Read Posted
              2. 12.5.3.4.12.2.2 Read Non-Posted
          13. 12.5.3.4.13 Timer Posted Mode Selection
        5. 12.5.3.5 Timers Low-Level Programming Models
          1. 12.5.3.5.1 Timer Global Initialization
            1. 12.5.3.5.1.1 Main Sequence – Timer Module Global Initialization
          2. 12.5.3.5.2 Timer Operational Mode Configuration
            1. 12.5.3.5.2.1 Timer Mode
              1. 12.5.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.5.3.5.2.2 Timer Compare Mode
              1. 12.5.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.5.3.5.2.3 Timer Capture Mode
              1. 12.5.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.5.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.5.3.5.2.3.3 Subsequence – Detect Event
            4. 12.5.3.5.2.4 Timer PWM Mode
              1. 12.5.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.5.3.6 Timers Registers
    6. 12.6 Internal Diagnostics Modules
      1. 12.6.1 Dual Clock Comparator (DCC)
        1. 12.6.1.1 DCC Overview
          1. 12.6.1.1.1 DCC Features
          2. 12.6.1.1.2 DCC Not Supported Features
        2. 12.6.1.2 DCC Integration
          1. 12.6.1.2.1 DCC Integration in MCU Domain
            1. 12.6.1.2.1.1 MCU DCC Input Source Clock Mapping
          2. 12.6.1.2.2 DCC Integration in MAIN Domain
            1. 12.6.1.2.2.1 DCC Input Source Clock Mapping
        3. 12.6.1.3 DCC Functional Description
          1. 12.6.1.3.1 DCC Counter Operation
          2. 12.6.1.3.2 DCC Low Power Mode Operation
          3. 12.6.1.3.3 DCC Suspend Mode Behavior
          4. 12.6.1.3.4 DCC Single-Shot Mode
          5. 12.6.1.3.5 DCC Continuous mode
            1. 12.6.1.3.5.1 DCC Continue on Error
            2. 12.6.1.3.5.2 DCC Error Count
          6. 12.6.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.6.1.3.7 DCC Error Trajectory record
            1. 12.6.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.6.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.6.1.3.7.3 DCC FIFO Details
            4. 12.6.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.6.1.3.8 DCC Count read registers
        4. 12.6.1.4 DCC Registers
      2. 12.6.2 Error Signaling Module (ESM)
        1. 12.6.2.1 ESM Overview
          1. 12.6.2.1.1 ESM Features
        2. 12.6.2.2 ESM Environment
        3. 12.6.2.3 ESM Integration
          1. 12.6.2.3.1 ESM Integration in MCU Domain
          2. 12.6.2.3.2 ESM Integration in MAIN Domain
        4. 12.6.2.4 ESM Functional Description
          1. 12.6.2.4.1 ESM Interrupt Requests
            1. 12.6.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.6.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.6.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.6.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.6.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.6.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.6.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.6.2.4.2 ESM Error Event Inputs
          3. 12.6.2.4.3 ESM Error Pin Output
          4. 12.6.2.4.4 PWM Mode
          5. 12.6.2.4.5 ESM Minimum Time Interval
          6. 12.6.2.4.6 ESM Protection for Registers
          7. 12.6.2.4.7 ESM Clock Stop
        5. 12.6.2.5 ESM Registers
      3. 12.6.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.6.3.1 MCRC Overview
          1. 12.6.3.1.1 MCRC Features
          2. 12.6.3.1.2 MCRC Not Supported Features
        2. 12.6.3.2 MCRC Integration
        3. 12.6.3.3 MCRC Functional Description
          1. 12.6.3.3.1  MCRC Block Diagram
          2. 12.6.3.3.2  MCRC General Operation
          3. 12.6.3.3.3  MCRC Modes of Operation
            1. 12.6.3.3.3.1 AUTO Mode
            2. 12.6.3.3.3.2 Semi-CPU Mode
            3. 12.6.3.3.3.3 Full-CPU Mode
          4. 12.6.3.3.4  PSA Signature Register
          5. 12.6.3.3.5  PSA Sector Signature Register
          6. 12.6.3.3.6  CRC Value Register
          7. 12.6.3.3.7  Raw Data Register
          8. 12.6.3.3.8  Example DMA Controller Setup
            1. 12.6.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.6.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.6.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.6.3.3.9  Pattern Count Register
          10. 12.6.3.3.10 Sector Count Register/Current Sector Register
          11. 12.6.3.3.11 Interrupts
            1. 12.6.3.3.11.1 Overrun Interrupt
            2. 12.6.3.3.11.2 Timeout Interrupt
            3. 12.6.3.3.11.3 Underrun Interrupt
            4. 12.6.3.3.11.4 Compression Complete Interrupt
            5. 12.6.3.3.11.5 Interrupt Offset Register
            6. 12.6.3.3.11.6 Error Handling
          12. 12.6.3.3.12 Power Down Mode
          13. 12.6.3.3.13 Emulation
        4. 12.6.3.4 MCRC Programming Examples
          1. 12.6.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.6.3.4.1.1 DMA Setup
            2. 12.6.3.4.1.2 Timer Setup
            3. 12.6.3.4.1.3 CRC Setup
          2. 12.6.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.6.3.4.2.1 DMA Setup
            2. 12.6.3.4.2.2 CRC Setup
          3. 12.6.3.4.3 Example: Semi-CPU Mode
            1. 12.6.3.4.3.1 DMA Setup
            2. 12.6.3.4.3.2 Timer Setup
            3. 12.6.3.4.3.3 CRC Setup
          4. 12.6.3.4.4 Example: Full-CPU Mode
            1. 12.6.3.4.4.1 CRC Setup
        5. 12.6.3.5 MCRC Registers
      4. 12.6.4 ECC Aggregator
        1. 12.6.4.1 ECC Aggregator Overview
          1. 12.6.4.1.1 ECC Aggregator Features
        2. 12.6.4.2 ECC Aggregator Integration
        3. 12.6.4.3 ECC Aggregator Functional Description
          1. 12.6.4.3.1 ECC Aggregator Block Diagram
          2. 12.6.4.3.2 ECC Aggregator Register Groups
          3. 12.6.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.6.4.3.4 Serial Write Operation
          5. 12.6.4.3.5 Interrupts
          6. 12.6.4.3.6 Inject Only Mode
        4. 12.6.4.4 ECC Aggregators Interconnect
        5. 12.6.4.5 ECC Aggregator Registers
  15. 13On-Chip Debug
    1. 13.1 On-Chip Debug Overview
    2. 13.2 On-Chip Debug Features
    3.     5688
    4. 13.3 On-Chip Debug Functional Description
      1. 13.3.1  On-Chip Debug Block Diagram
      2. 13.3.2  Device Interfaces
        1. 13.3.2.1 JTAG Interface
        2. 13.3.2.2 Trigger and Debug Boot Mode Interface
        3. 13.3.2.3 Trace Port Interface
      3. 13.3.3  Debug and Boundary Scan Access and Control
      4. 13.3.4  Debug Boot Modes and Boundary Scan Compliance
      5. 13.3.5  Power, Reset, Clock Management
      6. 13.3.6  Debug Cross Triggering
      7. 13.3.7  R5FSS0/R5FSS1 Debug
      8. 13.3.8  DMSC Debug
      9. 13.3.9  A53SS0 Debug
      10. 13.3.10 PRU_ICSSG0/PRU_ICSSG1 Debug
      11. 13.3.11 SoC Debug and Trace
        1. 13.3.11.1 Software messaging trace
        2. 13.3.11.2 Debug-Aware Peripherals
        3. 13.3.11.3 Traffic Monitoring With Bus Probes
        4. 13.3.11.4 Global timestamping for trace
      12. 13.3.12 Trace Traffic
        1. 13.3.12.1 Trace Sources
        2. 13.3.12.2 Trace Infrasctructure
        3. 13.3.12.3 Trace Sinks
      13. 13.3.13 Application Support
  16. 14Revision History
12.2.2.5.1 PCIE Registers

Table 12-1466 core__ecc_aggr0__regs, PCIE0_CORE_ECC_AGGR0 Registers, Base Address=0071 8000H, Length=1024
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_rev Aggregator Revision Register 0071 8000h
8h 32 PCIE0_vector ECC Vector Register 0071 8008h
Ch 32 PCIE0_stat Misc Status 0071 800Ch
10h 32 PCIE0_reserved_svbus Reserved Area for Serial VBUS Registers 0071 8010h
3Ch 32 PCIE0_sec_eoi_reg EOI Register 0071 803Ch
40h 32 PCIE0_sec_status_reg0 Interrupt Status Register 0 0071 8040h
80h 32 PCIE0_sec_enable_set_reg0 Interrupt Enable Set Register 0 0071 8080h
C0h 32 PCIE0_sec_enable_clr_reg0 Interrupt Enable Clear Register 0 0071 80C0h
13Ch 32 PCIE0_ded_eoi_reg EOI Register 0071 813Ch
140h 32 PCIE0_ded_status_reg0 Interrupt Status Register 0 0071 8140h
180h 32 PCIE0_ded_enable_set_reg0 Interrupt Enable Set Register 0 0071 8180h
1C0h 32 PCIE0_ded_enable_clr_reg0 Interrupt Enable Clear Register 0 0071 81C0h
200h 32 PCIE0_aggr_enable_set AGGR interrupt enable set Register 0071 8200h
204h 32 PCIE0_aggr_enable_clr AGGR interrupt enable clear Register 0071 8204h
208h 32 PCIE0_aggr_status_set AGGR interrupt status set Register 0071 8208h
20Ch 32 PCIE0_aggr_status_clr AGGR interrupt status clear Register 0071 820Ch

Table 12-1467 core__ecc_aggr1__regs, PCIE0_CORE_ECC_AGGR1 Registers, Base Address=0071 9000H, Length=1024
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_rev Aggregator Revision Register 0071 9000h
8h 32 PCIE0_vector ECC Vector Register 0071 9008h
Ch 32 PCIE0_stat Misc Status 0071 900Ch
10h 32 PCIE0_reserved_svbus Reserved Area for Serial VBUS Registers 0071 9010h
3Ch 32 PCIE0_sec_eoi_reg EOI Register 0071 903Ch
40h 32 PCIE0_sec_status_reg0 Interrupt Status Register 0 0071 9040h
80h 32 PCIE0_sec_enable_set_reg0 Interrupt Enable Set Register 0 0071 9080h
C0h 32 PCIE0_sec_enable_clr_reg0 Interrupt Enable Clear Register 0 0071 90C0h
13Ch 32 PCIE0_ded_eoi_reg EOI Register 0071 913Ch
140h 32 PCIE0_ded_status_reg0 Interrupt Status Register 0 0071 9140h
180h 32 PCIE0_ded_enable_set_reg0 Interrupt Enable Set Register 0 0071 9180h
1C0h 32 PCIE0_ded_enable_clr_reg0 Interrupt Enable Clear Register 0 0071 91C0h
200h 32 PCIE0_aggr_enable_set AGGR interrupt enable set Register 0071 9200h
204h 32 PCIE0_aggr_enable_clr AGGR interrupt enable clear Register 0071 9204h
208h 32 PCIE0_aggr_status_set AGGR interrupt status set Register 0071 9208h
20Ch 32 PCIE0_aggr_status_clr AGGR interrupt status clear Register 0071 920Ch

Table 12-1468 core__dbn_cfg__pcie_core_reg, PCIE0_CORE_DBN_CFG_PCIE_CORE Registers, Base Address=0D00 0000H, Length=8388608
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_RC_i_rc_pcie_base_i_vendor_id_device_id 0D00 0000h
4h 32 PCIE0_RC_i_rc_pcie_base_i_command_status 0D00 0004h
8h 32 PCIE0_RC_i_rc_pcie_base_i_revision_id_class_code 0D00 0008h
Ch 32 PCIE0_RC_i_rc_pcie_base_i_bist_header_latency_cache_line 0D00 000Ch
10h 32 PCIE0_RC_i_rc_pcie_base_i_RC_BAR_0 0D00 0010h
14h 32 PCIE0_RC_i_rc_pcie_base_i_RC_BAR_1 0D00 0014h
18h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_bus_numbers 0D00 0018h
1Ch 32 PCIE0_RC_i_rc_pcie_base_i_pcie_io_base_limit 0D00 001Ch
20h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_mem_base_limit 0D00 0020h
24h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_prefetch_base_limit 0D00 0024h
28h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_prefetch_base_upper 0D00 0028h
2Ch 32 PCIE0_RC_i_rc_pcie_base_i_pcie_prefetch_limit_upper 0D00 002Ch
30h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_io_base_limit_upper 0D00 0030h
34h 32 PCIE0_RC_i_rc_pcie_base_i_capabilities_pointer 0D00 0034h
38h 32 PCIE0_RC_i_rc_pcie_base_rsvd_0E 0D00 0038h
3Ch 32 PCIE0_RC_i_rc_pcie_base_i_intrpt_line_intrpt_pin 0D00 003Ch
80h 32 PCIE0_RC_i_rc_pcie_base_i_pwr_mgmt_cap 0D00 0080h
84h 32 PCIE0_RC_i_rc_pcie_base_i_pwr_mgmt_ctrl_stat_rep 0D00 0084h
90h 32 PCIE0_RC_i_rc_pcie_base_i_msi_ctrl_reg 0D00 0090h
94h 32 PCIE0_RC_i_rc_pcie_base_i_msi_msg_low_addr 0D00 0094h
98h 32 PCIE0_RC_i_rc_pcie_base_i_msi_msg_hi_addr 0D00 0098h
9Ch 32 PCIE0_RC_i_rc_pcie_base_i_msi_msg_data 0D00 009Ch
A0h 32 PCIE0_RC_i_rc_pcie_base_i_msi_mask 0D00 00A0h
A4h 32 PCIE0_RC_i_rc_pcie_base_i_msi_pending_bits 0D00 00A4h
B0h 32 PCIE0_RC_i_rc_pcie_base_i_msix_ctrl 0D00 00B0h
B4h 32 PCIE0_RC_i_rc_pcie_base_i_msix_tbl_offset 0D00 00B4h
B8h 32 PCIE0_RC_i_rc_pcie_base_i_msix_pending_intrpt 0D00 00B8h
C0h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_cap_list 0D00 00C0h
C4h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_cap 0D00 00C4h
C8h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_dev_ctrl_status 0D00 00C8h
CCh 32 PCIE0_RC_i_rc_pcie_base_i_link_cap 0D00 00CCh
D0h 32 PCIE0_RC_i_rc_pcie_base_i_link_ctrl_status 0D00 00D0h
D4h 32 PCIE0_RC_i_rc_pcie_base_i_slot_capability 0D00 00D4h
D8h 32 PCIE0_RC_i_rc_pcie_base_i_slot_ctrl_status 0D00 00D8h
DCh 32 PCIE0_RC_i_rc_pcie_base_i_root_ctrl_cap 0D00 00DCh
E0h 32 PCIE0_RC_i_rc_pcie_base_i_root_status 0D00 00E0h
E4h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_cap_2 0D00 00E4h
E8h 32 PCIE0_RC_i_rc_pcie_base_i_pcie_dev_ctrl_status_2 0D00 00E8h
ECh 32 PCIE0_RC_i_rc_pcie_base_i_link_cap_2 0D00 00ECh
F0h 32 PCIE0_RC_i_rc_pcie_base_i_link_ctrl_status_2 0D00 00F0h
100h 32 PCIE0_RC_i_rc_pcie_base_i_AER_enhncd_cap 0D00 0100h
104h 32 PCIE0_RC_i_rc_pcie_base_i_uncorr_err_status 0D00 0104h
108h 32 PCIE0_RC_i_rc_pcie_base_i_uncorr_err_mask 0D00 0108h
10Ch 32 PCIE0_RC_i_rc_pcie_base_i_uncorr_err_severity 0D00 010Ch
110h 32 PCIE0_RC_i_rc_pcie_base_i_corr_err_status 0D00 0110h
114h 32 PCIE0_RC_i_rc_pcie_base_i_corr_err_mask 0D00 0114h
118h 32 PCIE0_RC_i_rc_pcie_base_i_adv_err_cap_ctl 0D00 0118h
11Ch 32 PCIE0_RC_i_rc_pcie_base_i_hdr_log_0 0D00 011Ch
120h 32 PCIE0_RC_i_rc_pcie_base_i_hdr_log_1 0D00 0120h
124h 32 PCIE0_RC_i_rc_pcie_base_i_hdr_log_2 0D00 0124h
128h 32 PCIE0_RC_i_rc_pcie_base_i_hdr_log_3 0D00 0128h
12Ch 32 PCIE0_RC_i_rc_pcie_base_i_root_err_cmd 0D00 012Ch
130h 32 PCIE0_RC_i_rc_pcie_base_i_root_err_stat 0D00 0130h
134h 32 PCIE0_RC_i_rc_pcie_base_i_err_src_id 0D00 0134h
138h 32 PCIE0_RC_i_rc_pcie_base_i_tlp_pre_log_0 0D00 0138h
150h 32 PCIE0_RC_i_rc_pcie_base_i_dev_ser_num_cap_hdr 0D00 0150h
154h 32 PCIE0_RC_i_rc_pcie_base_i_dev_ser_num_0 0D00 0154h
158h 32 PCIE0_RC_i_rc_pcie_base_i_dev_ser_num_1 0D00 0158h
300h 32 PCIE0_RC_i_rc_pcie_base_i_sec_pcie_cap_hdr_reg 0D00 0300h
304h 32 PCIE0_RC_i_rc_pcie_base_i_link_control3 0D00 0304h
308h 32 PCIE0_RC_i_rc_pcie_base_i_lane_error_status 0D00 0308h
30Ch 32 PCIE0_RC_i_rc_pcie_base_i_lane_equalization_control_0 0D00 030Ch
4C0h 32 PCIE0_RC_i_VC_cap_struct_i_VC_enh_cap_header_reg 0D00 04C0h
4C4h 32 PCIE0_RC_i_VC_cap_struct_i_port_vc_cap_reg_1 0D00 04C4h
4C8h 32 PCIE0_RC_i_VC_cap_struct_i_port_vc_cap_reg_2 0D00 04C8h
4CCh 32 PCIE0_RC_i_VC_cap_struct_i_port_vc_ctrl_sts_reg 0D00 04CCh
4D0h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_cap_reg_0 0D00 04D0h
4D4h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_ctrl_reg_0 0D00 04D4h
4D8h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_sts_reg_0 0D00 04D8h
4DCh 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_cap_reg_1 0D00 04DCh
4E0h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_ctrl_reg_1 0D00 04E0h
4E4h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_sts_reg_1 0D00 04E4h
4E8h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_cap_reg_2 0D00 04E8h
4ECh 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_ctrl_reg_2 0D00 04ECh
4F0h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_sts_reg_2 0D00 04F0h
4F4h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_cap_reg_3 0D00 04F4h
4F8h 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_ctrl_reg_3 0D00 04F8h
4FCh 32 PCIE0_RC_i_VC_cap_struct_i_vc_res_sts_reg_3 0D00 04FCh
900h 32 PCIE0_RC_i_regf_L1_PM_cap_struct_i_L1_PM_ext_cap_hdr 0D00 0900h
904h 32 PCIE0_RC_i_regf_L1_PM_cap_struct_i_L1_PM_cap 0D00 0904h
908h 32 PCIE0_RC_i_regf_L1_PM_cap_struct_i_L1_PM_ctrl_1 0D00 0908h
90Ch 32 PCIE0_RC_i_regf_L1_PM_cap_struct_i_L1_PM_ctrl_2 0D00 090Ch
A20h 32 PCIE0_RC_i_regf_ptm_cap_i_ptm_extended_capability_header_reg 0D00 0A20h
A24h 32 PCIE0_RC_i_regf_ptm_cap_i_ptm_capabilities_reg 0D00 0A24h
A28h 32 PCIE0_RC_i_regf_ptm_cap_i_ptm_control_reg 0D00 0A28h
100000h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pl_config_0_reg 0D10 0000h
100004h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pl_config_1_reg 0D10 0004h
100008h 32 PCIE0_LM_i_regf_lm_pcie_base_i_dll_tmr_config_reg 0D10 0008h
10000Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_0_reg 0D10 000Ch
100010h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_1_reg 0D10 0010h
100014h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_0_reg 0D10 0014h
100018h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_1_reg 0D10 0018h
10001Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_update_int_config_0_reg 0D10 001Ch
100020h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_update_int_config_1_reg 0D10 0020h
100024h 32 PCIE0_LM_i_regf_lm_pcie_base_i_L0S_timeout_limit_reg 0D10 0024h
100028h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transmit_tlp_count_reg 0D10 0028h
10002Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_transmit_tlp_payload_dword_count_reg 0D10 002Ch
100030h 32 PCIE0_LM_i_regf_lm_pcie_base_i_receive_tlp_count_reg 0D10 0030h
100034h 32 PCIE0_LM_i_regf_lm_pcie_base_i_receive_tlp_payload_dword_count_reg 0D10 0034h
100038h 32 PCIE0_LM_i_regf_lm_pcie_base_i_compln_tmout_lim_0_reg 0D10 0038h
10003Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_compln_tmout_lim_1_reg 0D10 003Ch
100040h 32 PCIE0_LM_i_regf_lm_pcie_base_i_L1_st_reentry_delay_reg 0D10 0040h
100044h 32 PCIE0_LM_i_regf_lm_pcie_base_i_vendor_id_reg 0D10 0044h
100048h 32 PCIE0_LM_i_regf_lm_pcie_base_i_aspm_L1_entry_tmout_delay_reg 0D10 0048h
10004Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_pme_turnoff_ack_delay_reg 0D10 004Ch
100050h 32 PCIE0_LM_i_regf_lm_pcie_base_i_linkwidth_control_reg 0D10 0050h
100054h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pl_config_2_reg 0D10 0054h
100070h 32 PCIE0_LM_i_regf_lm_pcie_base_i_multi_vc_conrol_reg 0D10 0070h
100074h 32 PCIE0_LM_i_regf_lm_pcie_base_i_sris_control_reg 0D10 0074h
100080h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_0_reg_vc1 0D10 0080h
100084h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_1_reg_vc1 0D10 0084h
100088h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_0_reg_vc1 0D10 0088h
10008Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_1_reg_vc1 0D10 008Ch
100090h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_0_reg_vc2 0D10 0090h
100094h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_1_reg_vc2 0D10 0094h
100098h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_0_reg_vc2 0D10 0098h
10009Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_1_reg_vc2 0D10 009Ch
1000A0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_0_reg_vc3 0D10 00A0h
1000A4h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rcv_cred_lim_1_reg_vc3 0D10 00A4h
1000A8h 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_0_reg_vc3 0D10 00A8h
1000ACh 32 PCIE0_LM_i_regf_lm_pcie_base_i_transm_cred_lim_1_reg_vc3 0D10 00ACh
1000F0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_fc_init_delay_reg 0D10 00F0h
100100h 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_hdr_log_0_reg 0D10 0100h
100104h 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_hdr_log_1_reg 0D10 0104h
100108h 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_hdr_log_2_reg 0D10 0108h
10010Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_hdr_log_3_reg 0D10 010Ch
100110h 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_func_num_reg 0D10 0110h
100114h 32 PCIE0_LM_i_regf_lm_pcie_base_i_shdw_ur_err_reg 0D10 0114h
100140h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pm_clk_frequency_reg 0D10 0140h
100144h 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_dllp_count_gen1_reg 0D10 0144h
100148h 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_dllp_count_gen2_reg 0D10 0148h
10014Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_dllp_count_gen3_reg 0D10 014Ch
100158h 32 PCIE0_LM_i_regf_lm_pcie_base_i_vendor_defined_message_tag_reg 0D10 0158h
100200h 32 PCIE0_LM_i_regf_lm_pcie_base_i_negotiated_lane_map_reg 0D10 0200h
100204h 32 PCIE0_LM_i_regf_lm_pcie_base_i_receive_fts_count_reg 0D10 0204h
100208h 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_mux_control_reg 0D10 0208h
10020Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_local_error_status_register 0D10 020Ch
100210h 32 PCIE0_LM_i_regf_lm_pcie_base_i_local_intrpt_mask_reg 0D10 0210h
100214h 32 PCIE0_LM_i_regf_lm_pcie_base_i_lcrc_err_count_reg 0D10 0214h
100218h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ecc_corr_err_count_reg 0D10 0218h
10021Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_ltr_snoop_lat_reg 0D10 021Ch
100220h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ltr_msg_gen_ctl_reg 0D10 0220h
100224h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pme_service_timeout_delay_reg 0D10 0224h
100228h 32 PCIE0_LM_i_regf_lm_pcie_base_i_root_port_requestor_id_reg 0D10 0228h
10022Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_ep_bus_device_number_reg 0D10 022Ch
100234h 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_mux_control_2_reg 0D10 0234h
100238h 32 PCIE0_LM_i_regf_lm_pcie_base_i_phy_status_1_reg 0D10 0238h
10023Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_debug_mux_control_3_reg 0D10 023Ch
100300h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rc_BAR_config_reg 0D10 0300h
100360h 32 PCIE0_LM_i_regf_lm_pcie_base_i_gen3_default_preset_reg 0D10 0360h
100364h 32 PCIE0_LM_i_regf_lm_pcie_base_i_gen3_link_eq_timeout_2ms_reg 0D10 0364h
100368h 32 PCIE0_LM_i_regf_lm_pcie_base_i_pipe_fifo_latency_ctrl_reg 0D10 0368h
10037Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_gen3_link_eq_ctrl_reg 0D10 037Ch
100380h 32 PCIE0_LM_i_regf_lm_pcie_base_i_gen3_link_eq_debug_status_reg_lane0 0D10 0380h
100C80h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ecc_corr_err_count_reg_axi 0D10 0C80h
100C88h 32 PCIE0_LM_i_regf_lm_pcie_base_low_power_debug_and_control0 0D10 0C88h
100C8Ch 32 PCIE0_LM_i_regf_lm_pcie_base_low_power_debug_and_control1 0D10 0C8Ch
100C90h 32 PCIE0_LM_i_regf_lm_pcie_base_low_power_debug_and_control2 0D10 0C90h
100C94h 32 PCIE0_LM_i_regf_lm_pcie_base_tl_internal_control 0D10 0C94h
100D00h 32 PCIE0_LM_i_regf_lm_pcie_base_i_local_error_status_2_register 0D10 0D00h
100D04h 32 PCIE0_LM_i_regf_lm_pcie_base_i_local_intrpt_mask_2_reg 0D10 0D04h
100DA0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ld_ctrl 0D10 0DA0h
100DA4h 32 PCIE0_LM_i_regf_lm_pcie_base_rx_elec_idle_filter_control 0D10 0DA4h
100DA8h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_local_control_reg 0D10 0DA8h
100DACh 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_local_status_reg 0D10 0DACh
100DB0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_latency_parameters_index_reg 0D10 0DB0h
100DB4h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_latency_parameters_reg 0D10 0DB4h
100DB8h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_1_reg 0D10 0DB8h
100DBCh 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_2_reg 0D10 0DBCh
100DC0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_3_reg 0D10 0DC0h
100DC4h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_4_reg 0D10 0DC4h
100DC8h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_5_reg 0D10 0DC8h
100DCCh 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_6_reg 0D10 0DCCh
100DD0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_7_reg 0D10 0DD0h
100DD4h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_8_reg 0D10 0DD4h
100DD8h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_9_reg 0D10 0DD8h
100DDCh 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_10_reg 0D10 0DDCh
100DE0h 32 PCIE0_LM_i_regf_lm_pcie_base_i_ptm_context_11_reg 0D10 0DE0h
100E4Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_eq_debug_mon_control_reg 0D10 0E4Ch
100E50h 32 PCIE0_LM_i_regf_lm_pcie_base_i_eq_debug_mon_status0_reg 0D10 0E50h
100E54h 32 PCIE0_LM_i_regf_lm_pcie_base_i_eq_debug_mon_status_reg 0D10 0E54h
100E5Ch 32 PCIE0_LM_i_regf_lm_pcie_base_i_axi_feature_reg 0D10 0E5Ch
100E60h 32 PCIE0_LM_i_regf_lm_pcie_base_i_link_eq_control_2_reg 0D10 0E60h
100E64h 32 PCIE0_LM_i_regf_lm_pcie_base_i_core_feature_reg 0D10 0E64h
100E88h 32 PCIE0_LM_i_regf_lm_pcie_base_i_rx_invert_polarity_reg 0D10 0E88h
400000h 32 PCIE0_atu_wrapper_ob_0_addr0 0D40 0000h
400004h 32 PCIE0_atu_wrapper_ob_0_addr1 0D40 0004h
400008h 32 PCIE0_atu_wrapper_ob_0_desc0 0D40 0008h
40000Ch 32 PCIE0_atu_wrapper_ob_0_desc1 0D40 000Ch
400014h 32 PCIE0_atu_wrapper_ob_0_desc3 0D40 0014h
400018h 32 PCIE0_atu_wrapper_ob_0_axi_addr0 0D40 0018h
40001Ch 32 PCIE0_atu_wrapper_ob_0_axi_addr1 0D40 001Ch
400020h 32 PCIE0_atu_wrapper_ob_1_addr0 0D40 0020h
400024h 32 PCIE0_atu_wrapper_ob_1_addr1 0D40 0024h
400028h 32 PCIE0_atu_wrapper_ob_1_desc0 0D40 0028h
40002Ch 32 PCIE0_atu_wrapper_ob_1_desc1 0D40 002Ch
400034h 32 PCIE0_atu_wrapper_ob_1_desc3 0D40 0034h
400038h 32 PCIE0_atu_wrapper_ob_1_axi_addr0 0D40 0038h
40003Ch 32 PCIE0_atu_wrapper_ob_1_axi_addr1 0D40 003Ch
400040h 32 PCIE0_atu_wrapper_ob_2_addr0 0D40 0040h
400044h 32 PCIE0_atu_wrapper_ob_2_addr1 0D40 0044h
400048h 32 PCIE0_atu_wrapper_ob_2_desc0 0D40 0048h
40004Ch 32 PCIE0_atu_wrapper_ob_2_desc1 0D40 004Ch
400054h 32 PCIE0_atu_wrapper_ob_2_desc3 0D40 0054h
400058h 32 PCIE0_atu_wrapper_ob_2_axi_addr0 0D40 0058h
40005Ch 32 PCIE0_atu_wrapper_ob_2_axi_addr1 0D40 005Ch
400060h 32 PCIE0_atu_wrapper_ob_3_addr0 0D40 0060h
400064h 32 PCIE0_atu_wrapper_ob_3_addr1 0D40 0064h
400068h 32 PCIE0_atu_wrapper_ob_3_desc0 0D40 0068h
40006Ch 32 PCIE0_atu_wrapper_ob_3_desc1 0D40 006Ch
400074h 32 PCIE0_atu_wrapper_ob_3_desc3 0D40 0074h
400078h 32 PCIE0_atu_wrapper_ob_3_axi_addr0 0D40 0078h
40007Ch 32 PCIE0_atu_wrapper_ob_3_axi_addr1 0D40 007Ch
400080h 32 PCIE0_atu_wrapper_ob_4_addr0 0D40 0080h
400084h 32 PCIE0_atu_wrapper_ob_4_addr1 0D40 0084h
400088h 32 PCIE0_atu_wrapper_ob_4_desc0 0D40 0088h
40008Ch 32 PCIE0_atu_wrapper_ob_4_desc1 0D40 008Ch
400094h 32 PCIE0_atu_wrapper_ob_4_desc3 0D40 0094h
400098h 32 PCIE0_atu_wrapper_ob_4_axi_addr0 0D40 0098h
40009Ch 32 PCIE0_atu_wrapper_ob_4_axi_addr1 0D40 009Ch
4000A0h 32 PCIE0_atu_wrapper_ob_5_addr0 0D40 00A0h
4000A4h 32 PCIE0_atu_wrapper_ob_5_addr1 0D40 00A4h
4000A8h 32 PCIE0_atu_wrapper_ob_5_desc0 0D40 00A8h
4000ACh 32 PCIE0_atu_wrapper_ob_5_desc1 0D40 00ACh
4000B4h 32 PCIE0_atu_wrapper_ob_5_desc3 0D40 00B4h
4000B8h 32 PCIE0_atu_wrapper_ob_5_axi_addr0 0D40 00B8h
4000BCh 32 PCIE0_atu_wrapper_ob_5_axi_addr1 0D40 00BCh
4000C0h 32 PCIE0_atu_wrapper_ob_6_addr0 0D40 00C0h
4000C4h 32 PCIE0_atu_wrapper_ob_6_addr1 0D40 00C4h
4000C8h 32 PCIE0_atu_wrapper_ob_6_desc0 0D40 00C8h
4000CCh 32 PCIE0_atu_wrapper_ob_6_desc1 0D40 00CCh
4000D4h 32 PCIE0_atu_wrapper_ob_6_desc3 0D40 00D4h
4000D8h 32 PCIE0_atu_wrapper_ob_6_axi_addr0 0D40 00D8h
4000DCh 32 PCIE0_atu_wrapper_ob_6_axi_addr1 0D40 00DCh
4000E0h 32 PCIE0_atu_wrapper_ob_7_addr0 0D40 00E0h
4000E4h 32 PCIE0_atu_wrapper_ob_7_addr1 0D40 00E4h
4000E8h 32 PCIE0_atu_wrapper_ob_7_desc0 0D40 00E8h
4000ECh 32 PCIE0_atu_wrapper_ob_7_desc1 0D40 00ECh
4000F4h 32 PCIE0_atu_wrapper_ob_7_desc3 0D40 00F4h
4000F8h 32 PCIE0_atu_wrapper_ob_7_axi_addr0 0D40 00F8h
4000FCh 32 PCIE0_atu_wrapper_ob_7_axi_addr1 0D40 00FCh
400100h 32 PCIE0_atu_wrapper_ob_8_addr0 0D40 0100h
400104h 32 PCIE0_atu_wrapper_ob_8_addr1 0D40 0104h
400108h 32 PCIE0_atu_wrapper_ob_8_desc0 0D40 0108h
40010Ch 32 PCIE0_atu_wrapper_ob_8_desc1 0D40 010Ch
400114h 32 PCIE0_atu_wrapper_ob_8_desc3 0D40 0114h
400118h 32 PCIE0_atu_wrapper_ob_8_axi_addr0 0D40 0118h
40011Ch 32 PCIE0_atu_wrapper_ob_8_axi_addr1 0D40 011Ch
400120h 32 PCIE0_atu_wrapper_ob_9_addr0 0D40 0120h
400124h 32 PCIE0_atu_wrapper_ob_9_addr1 0D40 0124h
400128h 32 PCIE0_atu_wrapper_ob_9_desc0 0D40 0128h
40012Ch 32 PCIE0_atu_wrapper_ob_9_desc1 0D40 012Ch
400134h 32 PCIE0_atu_wrapper_ob_9_desc3 0D40 0134h
400138h 32 PCIE0_atu_wrapper_ob_9_axi_addr0 0D40 0138h
40013Ch 32 PCIE0_atu_wrapper_ob_9_axi_addr1 0D40 013Ch
400140h 32 PCIE0_atu_wrapper_ob_10_addr0 0D40 0140h
400144h 32 PCIE0_atu_wrapper_ob_10_addr1 0D40 0144h
400148h 32 PCIE0_atu_wrapper_ob_10_desc0 0D40 0148h
40014Ch 32 PCIE0_atu_wrapper_ob_10_desc1 0D40 014Ch
400154h 32 PCIE0_atu_wrapper_ob_10_desc3 0D40 0154h
400158h 32 PCIE0_atu_wrapper_ob_10_axi_addr0 0D40 0158h
40015Ch 32 PCIE0_atu_wrapper_ob_10_axi_addr1 0D40 015Ch
400160h 32 PCIE0_atu_wrapper_ob_11_addr0 0D40 0160h
400164h 32 PCIE0_atu_wrapper_ob_11_addr1 0D40 0164h
400168h 32 PCIE0_atu_wrapper_ob_11_desc0 0D40 0168h
40016Ch 32 PCIE0_atu_wrapper_ob_11_desc1 0D40 016Ch
400174h 32 PCIE0_atu_wrapper_ob_11_desc3 0D40 0174h
400178h 32 PCIE0_atu_wrapper_ob_11_axi_addr0 0D40 0178h
40017Ch 32 PCIE0_atu_wrapper_ob_11_axi_addr1 0D40 017Ch
400180h 32 PCIE0_atu_wrapper_ob_12_addr0 0D40 0180h
400184h 32 PCIE0_atu_wrapper_ob_12_addr1 0D40 0184h
400188h 32 PCIE0_atu_wrapper_ob_12_desc0 0D40 0188h
40018Ch 32 PCIE0_atu_wrapper_ob_12_desc1 0D40 018Ch
400194h 32 PCIE0_atu_wrapper_ob_12_desc3 0D40 0194h
400198h 32 PCIE0_atu_wrapper_ob_12_axi_addr0 0D40 0198h
40019Ch 32 PCIE0_atu_wrapper_ob_12_axi_addr1 0D40 019Ch
4001A0h 32 PCIE0_atu_wrapper_ob_13_addr0 0D40 01A0h
4001A4h 32 PCIE0_atu_wrapper_ob_13_addr1 0D40 01A4h
4001A8h 32 PCIE0_atu_wrapper_ob_13_desc0 0D40 01A8h
4001ACh 32 PCIE0_atu_wrapper_ob_13_desc1 0D40 01ACh
4001B4h 32 PCIE0_atu_wrapper_ob_13_desc3 0D40 01B4h
4001B8h 32 PCIE0_atu_wrapper_ob_13_axi_addr0 0D40 01B8h
4001BCh 32 PCIE0_atu_wrapper_ob_13_axi_addr1 0D40 01BCh
4001C0h 32 PCIE0_atu_wrapper_ob_14_addr0 0D40 01C0h
4001C4h 32 PCIE0_atu_wrapper_ob_14_addr1 0D40 01C4h
4001C8h 32 PCIE0_atu_wrapper_ob_14_desc0 0D40 01C8h
4001CCh 32 PCIE0_atu_wrapper_ob_14_desc1 0D40 01CCh
4001D4h 32 PCIE0_atu_wrapper_ob_14_desc3 0D40 01D4h
4001D8h 32 PCIE0_atu_wrapper_ob_14_axi_addr0 0D40 01D8h
4001DCh 32 PCIE0_atu_wrapper_ob_14_axi_addr1 0D40 01DCh
4001E0h 32 PCIE0_atu_wrapper_ob_15_addr0 0D40 01E0h
4001E4h 32 PCIE0_atu_wrapper_ob_15_addr1 0D40 01E4h
4001E8h 32 PCIE0_atu_wrapper_ob_15_desc0 0D40 01E8h
4001ECh 32 PCIE0_atu_wrapper_ob_15_desc1 0D40 01ECh
4001F4h 32 PCIE0_atu_wrapper_ob_15_desc3 0D40 01F4h
4001F8h 32 PCIE0_atu_wrapper_ob_15_axi_addr0 0D40 01F8h
4001FCh 32 PCIE0_atu_wrapper_ob_15_axi_addr1 0D40 01FCh
400200h 32 PCIE0_atu_wrapper_ob_16_addr0 0D40 0200h
400204h 32 PCIE0_atu_wrapper_ob_16_addr1 0D40 0204h
400208h 32 PCIE0_atu_wrapper_ob_16_desc0 0D40 0208h
40020Ch 32 PCIE0_atu_wrapper_ob_16_desc1 0D40 020Ch
400214h 32 PCIE0_atu_wrapper_ob_16_desc3 0D40 0214h
400218h 32 PCIE0_atu_wrapper_ob_16_axi_addr0 0D40 0218h
40021Ch 32 PCIE0_atu_wrapper_ob_16_axi_addr1 0D40 021Ch
400220h 32 PCIE0_atu_wrapper_ob_17_addr0 0D40 0220h
400224h 32 PCIE0_atu_wrapper_ob_17_addr1 0D40 0224h
400228h 32 PCIE0_atu_wrapper_ob_17_desc0 0D40 0228h
40022Ch 32 PCIE0_atu_wrapper_ob_17_desc1 0D40 022Ch
400234h 32 PCIE0_atu_wrapper_ob_17_desc3 0D40 0234h
400238h 32 PCIE0_atu_wrapper_ob_17_axi_addr0 0D40 0238h
40023Ch 32 PCIE0_atu_wrapper_ob_17_axi_addr1 0D40 023Ch
400240h 32 PCIE0_atu_wrapper_ob_18_addr0 0D40 0240h
400244h 32 PCIE0_atu_wrapper_ob_18_addr1 0D40 0244h
400248h 32 PCIE0_atu_wrapper_ob_18_desc0 0D40 0248h
40024Ch 32 PCIE0_atu_wrapper_ob_18_desc1 0D40 024Ch
400254h 32 PCIE0_atu_wrapper_ob_18_desc3 0D40 0254h
400258h 32 PCIE0_atu_wrapper_ob_18_axi_addr0 0D40 0258h
40025Ch 32 PCIE0_atu_wrapper_ob_18_axi_addr1 0D40 025Ch
400260h 32 PCIE0_atu_wrapper_ob_19_addr0 0D40 0260h
400264h 32 PCIE0_atu_wrapper_ob_19_addr1 0D40 0264h
400268h 32 PCIE0_atu_wrapper_ob_19_desc0 0D40 0268h
40026Ch 32 PCIE0_atu_wrapper_ob_19_desc1 0D40 026Ch
400274h 32 PCIE0_atu_wrapper_ob_19_desc3 0D40 0274h
400278h 32 PCIE0_atu_wrapper_ob_19_axi_addr0 0D40 0278h
40027Ch 32 PCIE0_atu_wrapper_ob_19_axi_addr1 0D40 027Ch
400280h 32 PCIE0_atu_wrapper_ob_20_addr0 0D40 0280h
400284h 32 PCIE0_atu_wrapper_ob_20_addr1 0D40 0284h
400288h 32 PCIE0_atu_wrapper_ob_20_desc0 0D40 0288h
40028Ch 32 PCIE0_atu_wrapper_ob_20_desc1 0D40 028Ch
400294h 32 PCIE0_atu_wrapper_ob_20_desc3 0D40 0294h
400298h 32 PCIE0_atu_wrapper_ob_20_axi_addr0 0D40 0298h
40029Ch 32 PCIE0_atu_wrapper_ob_20_axi_addr1 0D40 029Ch
4002A0h 32 PCIE0_atu_wrapper_ob_21_addr0 0D40 02A0h
4002A4h 32 PCIE0_atu_wrapper_ob_21_addr1 0D40 02A4h
4002A8h 32 PCIE0_atu_wrapper_ob_21_desc0 0D40 02A8h
4002ACh 32 PCIE0_atu_wrapper_ob_21_desc1 0D40 02ACh
4002B4h 32 PCIE0_atu_wrapper_ob_21_desc3 0D40 02B4h
4002B8h 32 PCIE0_atu_wrapper_ob_21_axi_addr0 0D40 02B8h
4002BCh 32 PCIE0_atu_wrapper_ob_21_axi_addr1 0D40 02BCh
4002C0h 32 PCIE0_atu_wrapper_ob_22_addr0 0D40 02C0h
4002C4h 32 PCIE0_atu_wrapper_ob_22_addr1 0D40 02C4h
4002C8h 32 PCIE0_atu_wrapper_ob_22_desc0 0D40 02C8h
4002CCh 32 PCIE0_atu_wrapper_ob_22_desc1 0D40 02CCh
4002D4h 32 PCIE0_atu_wrapper_ob_22_desc3 0D40 02D4h
4002D8h 32 PCIE0_atu_wrapper_ob_22_axi_addr0 0D40 02D8h
4002DCh 32 PCIE0_atu_wrapper_ob_22_axi_addr1 0D40 02DCh
4002E0h 32 PCIE0_atu_wrapper_ob_23_addr0 0D40 02E0h
4002E4h 32 PCIE0_atu_wrapper_ob_23_addr1 0D40 02E4h
4002E8h 32 PCIE0_atu_wrapper_ob_23_desc0 0D40 02E8h
4002ECh 32 PCIE0_atu_wrapper_ob_23_desc1 0D40 02ECh
4002F4h 32 PCIE0_atu_wrapper_ob_23_desc3 0D40 02F4h
4002F8h 32 PCIE0_atu_wrapper_ob_23_axi_addr0 0D40 02F8h
4002FCh 32 PCIE0_atu_wrapper_ob_23_axi_addr1 0D40 02FCh
400300h 32 PCIE0_atu_wrapper_ob_24_addr0 0D40 0300h
400304h 32 PCIE0_atu_wrapper_ob_24_addr1 0D40 0304h
400308h 32 PCIE0_atu_wrapper_ob_24_desc0 0D40 0308h
40030Ch 32 PCIE0_atu_wrapper_ob_24_desc1 0D40 030Ch
400314h 32 PCIE0_atu_wrapper_ob_24_desc3 0D40 0314h
400318h 32 PCIE0_atu_wrapper_ob_24_axi_addr0 0D40 0318h
40031Ch 32 PCIE0_atu_wrapper_ob_24_axi_addr1 0D40 031Ch
400320h 32 PCIE0_atu_wrapper_ob_25_addr0 0D40 0320h
400324h 32 PCIE0_atu_wrapper_ob_25_addr1 0D40 0324h
400328h 32 PCIE0_atu_wrapper_ob_25_desc0 0D40 0328h
40032Ch 32 PCIE0_atu_wrapper_ob_25_desc1 0D40 032Ch
400334h 32 PCIE0_atu_wrapper_ob_25_desc3 0D40 0334h
400338h 32 PCIE0_atu_wrapper_ob_25_axi_addr0 0D40 0338h
40033Ch 32 PCIE0_atu_wrapper_ob_25_axi_addr1 0D40 033Ch
400340h 32 PCIE0_atu_wrapper_ob_26_addr0 0D40 0340h
400344h 32 PCIE0_atu_wrapper_ob_26_addr1 0D40 0344h
400348h 32 PCIE0_atu_wrapper_ob_26_desc0 0D40 0348h
40034Ch 32 PCIE0_atu_wrapper_ob_26_desc1 0D40 034Ch
400354h 32 PCIE0_atu_wrapper_ob_26_desc3 0D40 0354h
400358h 32 PCIE0_atu_wrapper_ob_26_axi_addr0 0D40 0358h
40035Ch 32 PCIE0_atu_wrapper_ob_26_axi_addr1 0D40 035Ch
400360h 32 PCIE0_atu_wrapper_ob_27_addr0 0D40 0360h
400364h 32 PCIE0_atu_wrapper_ob_27_addr1 0D40 0364h
400368h 32 PCIE0_atu_wrapper_ob_27_desc0 0D40 0368h
40036Ch 32 PCIE0_atu_wrapper_ob_27_desc1 0D40 036Ch
400374h 32 PCIE0_atu_wrapper_ob_27_desc3 0D40 0374h
400378h 32 PCIE0_atu_wrapper_ob_27_axi_addr0 0D40 0378h
40037Ch 32 PCIE0_atu_wrapper_ob_27_axi_addr1 0D40 037Ch
400380h 32 PCIE0_atu_wrapper_ob_28_addr0 0D40 0380h
400384h 32 PCIE0_atu_wrapper_ob_28_addr1 0D40 0384h
400388h 32 PCIE0_atu_wrapper_ob_28_desc0 0D40 0388h
40038Ch 32 PCIE0_atu_wrapper_ob_28_desc1 0D40 038Ch
400394h 32 PCIE0_atu_wrapper_ob_28_desc3 0D40 0394h
400398h 32 PCIE0_atu_wrapper_ob_28_axi_addr0 0D40 0398h
40039Ch 32 PCIE0_atu_wrapper_ob_28_axi_addr1 0D40 039Ch
4003A0h 32 PCIE0_atu_wrapper_ob_29_addr0 0D40 03A0h
4003A4h 32 PCIE0_atu_wrapper_ob_29_addr1 0D40 03A4h
4003A8h 32 PCIE0_atu_wrapper_ob_29_desc0 0D40 03A8h
4003ACh 32 PCIE0_atu_wrapper_ob_29_desc1 0D40 03ACh
4003B4h 32 PCIE0_atu_wrapper_ob_29_desc3 0D40 03B4h
4003B8h 32 PCIE0_atu_wrapper_ob_29_axi_addr0 0D40 03B8h
4003BCh 32 PCIE0_atu_wrapper_ob_29_axi_addr1 0D40 03BCh
4003C0h 32 PCIE0_atu_wrapper_ob_31_addr0 0D40 03C0h
4003C4h 32 PCIE0_atu_wrapper_ob_31_addr1 0D40 03C4h
4003C8h 32 PCIE0_atu_wrapper_ob_31_desc0 0D40 03C8h
4003CCh 32 PCIE0_atu_wrapper_ob_31_desc1 0D40 03CCh
4003D4h 32 PCIE0_atu_wrapper_ob_31_desc3 0D40 03D4h
4003D8h 32 PCIE0_atu_wrapper_ob_31_axi_addr0 0D40 03D8h
4003DCh 32 PCIE0_atu_wrapper_ob_31_axi_addr1 0D40 03DCh
4003E0h 32 PCIE0_atu_wrapper_ob_32_addr0 0D40 03E0h
4003E4h 32 PCIE0_atu_wrapper_ob_32_addr1 0D40 03E4h
4003E8h 32 PCIE0_atu_wrapper_ob_32_desc0 0D40 03E8h
4003ECh 32 PCIE0_atu_wrapper_ob_32_desc1 0D40 03ECh
4003F4h 32 PCIE0_atu_wrapper_ob_32_desc3 0D40 03F4h
4003F8h 32 PCIE0_atu_wrapper_ob_32_axi_addr0 0D40 03F8h
4003FCh 32 PCIE0_atu_wrapper_ob_32_axi_addr1 0D40 03FCh
400800h 32 PCIE0_atu_wrapper_ib_0_addr0 0D40 0800h
400804h 32 PCIE0_atu_wrapper_ib_0_addr1 0D40 0804h
400808h 32 PCIE0_atu_wrapper_ib_1_addr0 0D40 0808h
40080Ch 32 PCIE0_atu_wrapper_ib_1_addr1 0D40 080Ch
400810h 32 PCIE0_atu_wrapper_ib_7_addr0 0D40 0810h
400814h 32 PCIE0_atu_wrapper_ib_7_addr1 0D40 0814h
400820h 32 PCIE0_atu_credit_threshold_c0 0D40 0820h
400824h 32 PCIE0_atu_link_down_indicator_bit_L0 0D40 0824h

Table 12-1469 core__user_cfg__user_cfg, PCIE0_CORE_USER_CFG_USER_CFG Registers, Base Address=0F10 0000H, Length=1024
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_revid 0F10 0000h
4h 32 PCIE0_cmd_status 0F10 0004h
8h 32 PCIE0_rstcmd 0F10 0008h
Ch 32 PCIE0_initcfg 0F10 000Ch
10h 32 PCIE0_pmcmd 0F10 0010h
14h 32 PCIE0_linkstatus 0F10 0014h
18h 32 PCIE0_legacy_intr_set 0F10 0018h
1Ch 32 PCIE0_legacy_int_pending 0F10 001Ch
20h 32 PCIE0_msi_stat 0F10 0020h
24h 32 PCIE0_msi_vector 0F10 0024h
28h 32 PCIE0_msi_mask_pf0 0F10 0028h
40h 32 PCIE0_msi_pending_status_pf0 0F10 0040h
A4h 32 PCIE0_msix_stat 0F10 00A4h
A8h 32 PCIE0_msix_mask 0F10 00A8h
B4h 32 PCIE0_flr_done 0F10 00B4h
BCh 32 PCIE0_ptm_cfg 0F10 00BCh
C0h 32 PCIE0_ptm_timer_low 0F10 00C0h
C4h 32 PCIE0_ptm_timer_high 0F10 00C4h
C8h 32 PCIE0_eoi_vector 0F10 00C8h

Table 12-1470 core__vmap_ob__mmrs, PCIE0_CORE_VMAP_OB_MMRS Registers, Base Address=0F10 1000H, Length=4096
Offset Length Acronym Register Name PCIE0 Physical Address
300h+ Formula 32 PCIE0_ext_desc_j 0F10 1300h+ Formula
400h 32 PCIE0_ob_virtid_match 0F10 1400h

Table 12-1471 core__pcie_intd_cfg__intd_cfg, PCIE0_CORE_PCIE_INTD_CFG_INTD_CFG Registers, Base Address=0F10 2000H, Length=4096
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_REVISION 0F10 2000h
100h 32 PCIE0_enable_reg_sys_0 0F10 2100h
104h 32 PCIE0_enable_reg_sys_1 0F10 2104h
108h 32 PCIE0_enable_reg_sys_2 0F10 2108h
300h 32 PCIE0_enable_clr_reg_sys_0 0F10 2300h
304h 32 PCIE0_enable_clr_reg_sys_1 0F10 2304h
308h 32 PCIE0_enable_clr_reg_sys_2 0F10 2308h
500h 32 PCIE0_status_reg_sys_0 0F10 2500h
504h 32 PCIE0_status_reg_sys_1 0F10 2504h
508h 32 PCIE0_status_reg_sys_2 0F10 2508h
708h 32 PCIE0_status_clr_reg_sys_2 0F10 2708h
A80h 32 PCIE0_intr_vector_reg_sys 0F10 2A80h

Table 12-1472 core__cpts_cfg__CPTS_VBUSP, PCIE0_CORE_CPTS_CFG_CPTS_VBUSP Registers, Base Address=0F10 3000H, Length=1024
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_IDVER_REG idver_reg 0F10 3000h
4h 32 PCIE0_CONTROL_REG control_reg 0F10 3004h
8h 32 PCIE0_RFTCLK_SEL_REG rftclk_sel_reg 0F10 3008h
Ch 32 PCIE0_TS_PUSH_REG ts_push_reg 0F10 300Ch
10h 32 PCIE0_TS_LOAD_VAL_REG ts_load_low_val_reg 0F10 3010h
14h 32 PCIE0_TS_LOAD_EN_REG ts_load_en_reg 0F10 3014h
18h 32 PCIE0_TS_COMP_VAL_REG ts_comp_low_val_reg 0F10 3018h
1Ch 32 PCIE0_TS_COMP_LEN_REG ts_comp_len_reg 0F10 301Ch
20h 32 PCIE0_INTSTAT_RAW_REG intstat_raw_reg 0F10 3020h
24h 32 PCIE0_INTSTAT_MASKED_REG intstat_masked_reg 0F10 3024h
28h 32 PCIE0_INT_ENABLE_REG int_enable_reg 0F10 3028h
2Ch 32 PCIE0_TS_COMP_NUDGE_REG ts_comp_nudge_reg 0F10 302Ch
30h 32 PCIE0_EVENT_POP_REG event_pop_reg 0F10 3030h
34h 32 PCIE0_EVENT_0_REG event_0_reg 0F10 3034h
38h 32 PCIE0_EVENT_1_REG event_1_reg 0F10 3038h
3Ch 32 PCIE0_EVENT_2_REG event_2_reg 0F10 303Ch
40h 32 PCIE0_EVENT_3_REG event_3_reg 0F10 3040h
44h 32 PCIE0_TS_LOAD_HIGH_VAL_REG ts_load_high_val_reg 0F10 3044h
48h 32 PCIE0_TS_COMP_HIGH_VAL_REG ts_comp_high_val_reg 0F10 3048h
4Ch 32 PCIE0_TS_ADD_VAL_REG ts_add_val 0F10 304Ch
50h 32 PCIE0_TS_PPM_LOW_VAL_REG ts_ppm_low_val_reg 0F10 3050h
54h 32 PCIE0_TS_PPM_HIGH_VAL_REG ts_ppm_high_val_reg 0F10 3054h
58h 32 PCIE0_TS_NUDGE_VAL_REG ts_nudge_val_reg 0F10 3058h
D0h 32 PCIE0_TS_CONFIG ts_config 0F10 30D0h
E0h 32 PCIE0_TS_GENF_COMP_LOW_REG comp_low_reg 0F10 30E0h
E4h 32 PCIE0_TS_GENF_COMP_HIGH_REG comp_high_reg 0F10 30E4h
E8h 32 PCIE0_TS_GENF_CONTROL_REG control_reg 0F10 30E8h
ECh 32 PCIE0_TS_GENF_LENGTH_REG length_reg 0F10 30ECh
F0h 32 PCIE0_TS_GENF_PPM_LOW_REG ppm_low_reg 0F10 30F0h
F4h 32 PCIE0_TS_GENF_PPM_HIGH_REG ppm_high_reg 0F10 30F4h
F8h 32 PCIE0_TS_GENF_NUDGE_REG nudge_reg 0F10 30F8h
200h 32 PCIE0_TS_ESTF_COMP_LOW_REG comp_low_reg 0F10 3200h
204h 32 PCIE0_TS_ESTF_COMP_HIGH_REG comp_high_reg 0F10 3204h
208h 32 PCIE0_TS_ESTF_CONTROL_REG control_reg 0F10 3208h
20Ch 32 PCIE0_TS_ESTF_LENGTH_REG length_reg 0F10 320Ch
210h 32 PCIE0_TS_ESTF_PPM_LOW_REG ppm_low_reg 0F10 3210h
214h 32 PCIE0_TS_ESTF_PPM_HIGH_REG ppm_high_reg 0F10 3214h
218h 32 PCIE0_TS_ESTF_NUDGE_REG nudge_reg 0F10 3218h

Table 12-1473 core__core_dat_slv__pcie_dat0, PCIE0_DAT0 Registers, Base Address=6800 0000H, Length=134217728
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_pcie_data_mem PCIe data region0 6800 0000h

Table 12-1474 core__core_dat_slv__pcie_dat1, PCIE0_DAT1 Registers, Base Address=0006 0000 0000H, Length=4294967296
Offset Length Acronym Register Name PCIE0 Physical Address
0h 32 PCIE0_pcie_data_mem PCIe data region1 0006 0000 0000h

2.5.1.1 PCIE0_AGGR_REVISION Register (Offset = 0h) [reset = 1721772545]

Short Description: Aggregator Revision Register

Long Description:

Return to Summary Table

Table 12-1475 Instance Table
Instance Name Base Address
PCIE0 0071 8000h
Figure 12-754 PCIE0_REV Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCHEME BU MODULE_ID
R R R
1 10 11010100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVRTL REVMAJ CUSTOM REVMIN
R R R R
101 10 0 1

Access Types Legend

Table 12-1476 AGGR_REVISION Register Field Descriptions
Bit Field Type Reset Description
31 - 30 SCHEME R 1h Scheme
29 - 28 BU R 2h BU
27 - 16 MODULE_ID R 6A0h Module ID
15 - 11 REVRTL R 5h RTL version
10 - 8 REVMAJ R 2h Major version
7 - 6 CUSTOM R 0h Custom version
5 - 0 REVMIN R 1h Minor version

2.5.1.2 PCIE0_ECC_VECTOR Register (Offset = 8h) [reset = 0]

Short Description: ECC Vector Register

Long Description:

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Table 12-1477 Instance Table
Instance Name Base Address
PCIE0 0071 8008h
Figure 12-755 PCIE0_VECTOR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RD_SVBUS_DONE RD_SVBUS_ADDRESS
NONE R/W1TC R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_SVBUS RESERVED ECC_VECTOR
R/W1TS NONE R/W
0 0

Access Types Legend

Table 12-1478 ECC_VECTOR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
24 RD_SVBUS_DONE R/W1TC 0h Status to indicate if read on serial VBUS is complete, write of any value will clear this bit.
23 - 16 RD_SVBUS_ADDRESS R/W 0h Read address
15 RD_SVBUS R/W1TS 0h Write 1 to trigger a read on the serial VBUS
RESERVED NONE Reserved
10 - 0 ECC_VECTOR R/W 0h Value written to select the corresponding ECC RAM for control or status

2.5.1.3 PCIE0_MISC_STATUS Register (Offset = Ch) [reset = 4]

Short Description: Misc Status

Long Description:

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Table 12-1479 Instance Table
Instance Name Base Address
PCIE0 0071 800Ch
Figure 12-756 PCIE0_STAT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUM_RAMS
NONE R
100

Access Types Legend

Table 12-1480 MISC_STATUS Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
10 - 0 NUM_RAMS R 4h Indicates the number of RAMS serviced by the ECC aggregator

2.5.1.4 PCIE0_RESERVED_SVBUS Register (Offset = 10h) [reset = 0]

Short Description: Reserved Area for Serial VBUS Registers

Long Description:

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Table 12-1481 Instance Table
Instance Name Base Address
PCIE0 0071 8010h
Figure 12-757 PCIE0_RESERVED_SVBUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1482 RESERVED_SVBUS Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Serial VBUS register data

2.5.1.5 PCIE0_SEC_EOI_REG Register (Offset = 3Ch) [reset = 0]

Short Description: EOI Register

Long Description:

Return to Summary Table

Table 12-1483 Instance Table
Instance Name Base Address
PCIE0 0071 803Ch
Figure 12-758 PCIE0_SEC_EOI_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI_WR
NONE R/W1TS
0

Access Types Legend

Table 12-1484 SEC_EOI_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 EOI_WR R/W1TS 0h EOI Register

2.5.1.6 PCIE0_SEC_STATUS_REG0 Register (Offset = 40h) [reset = 0]

Short Description: Interrupt Status Register 0

Long Description:

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Table 12-1485 Instance Table
Instance Name Base Address
PCIE0 0071 8040h
Figure 12-759 PCIE0_SEC_STATUS_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_PEND DIBRAM_RAMECC_PEND AXISFIFO_RAMECC_PEND AXIMFIFO_RAMECC_PEND
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1486 SEC_STATUS_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_PEND R/W1TS 0h Interrupt Pending Status for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for dibram_ramecc_pend
1 AXISFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for aximfifo_ramecc_pend

2.5.1.7 PCIE0_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = 0]

Short Description: Interrupt Enable Set Register 0

Long Description:

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Table 12-1487 Instance Table
Instance Name Base Address
PCIE0 0071 8080h
Figure 12-760 PCIE0_SEC_ENABLE_SET_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_ENABLE_SET DIBRAM_RAMECC_ENABLE_SET AXISFIFO_RAMECC_ENABLE_SET AXIMFIFO_RAMECC_ENABLE_SET
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1488 SEC_ENABLE_SET_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for dibram_ramecc_pend
1 AXISFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for aximfifo_ramecc_pend

2.5.1.8 PCIE0_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = 0]

Short Description: Interrupt Enable Clear Register 0

Long Description:

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Table 12-1489 Instance Table
Instance Name Base Address
PCIE0 0071 80C0h
Figure 12-761 PCIE0_SEC_ENABLE_CLR_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_ENABLE_CLR DIBRAM_RAMECC_ENABLE_CLR AXISFIFO_RAMECC_ENABLE_CLR AXIMFIFO_RAMECC_ENABLE_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0

Access Types Legend

Table 12-1490 SEC_ENABLE_CLR_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for dibram_ramecc_pend
1 AXISFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for aximfifo_ramecc_pend

2.5.1.9 PCIE0_DED_EOI_REG Register (Offset = 13Ch) [reset = 0]

Short Description: EOI Register

Long Description:

Return to Summary Table

Table 12-1491 Instance Table
Instance Name Base Address
PCIE0 0071 813Ch
Figure 12-762 PCIE0_DED_EOI_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI_WR
NONE R/W1TS
0

Access Types Legend

Table 12-1492 DED_EOI_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 EOI_WR R/W1TS 0h EOI Register

2.5.1.10 PCIE0_DED_STATUS_REG0 Register (Offset = 140h) [reset = 0]

Short Description: Interrupt Status Register 0

Long Description:

Return to Summary Table

Table 12-1493 Instance Table
Instance Name Base Address
PCIE0 0071 8140h
Figure 12-763 PCIE0_DED_STATUS_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_PEND DIBRAM_RAMECC_PEND AXISFIFO_RAMECC_PEND AXIMFIFO_RAMECC_PEND
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1494 DED_STATUS_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_PEND R/W1TS 0h Interrupt Pending Status for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for dibram_ramecc_pend
1 AXISFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for aximfifo_ramecc_pend

2.5.1.11 PCIE0_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = 0]

Short Description: Interrupt Enable Set Register 0

Long Description:

Return to Summary Table

Table 12-1495 Instance Table
Instance Name Base Address
PCIE0 0071 8180h
Figure 12-764 PCIE0_DED_ENABLE_SET_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_ENABLE_SET DIBRAM_RAMECC_ENABLE_SET AXISFIFO_RAMECC_ENABLE_SET AXIMFIFO_RAMECC_ENABLE_SET
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1496 DED_ENABLE_SET_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for dibram_ramecc_pend
1 AXISFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for aximfifo_ramecc_pend

2.5.1.12 PCIE0_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = 0]

Short Description: Interrupt Enable Clear Register 0

Long Description:

Return to Summary Table

Table 12-1497 Instance Table
Instance Name Base Address
PCIE0 0071 81C0h
Figure 12-765 PCIE0_DED_ENABLE_CLR_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXI2VBUSM_MST_ENABLE_CLR DIBRAM_RAMECC_ENABLE_CLR AXISFIFO_RAMECC_ENABLE_CLR AXIMFIFO_RAMECC_ENABLE_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0

Access Types Legend

Table 12-1498 DED_ENABLE_CLR_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXI2VBUSM_MST_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axi2vbusm_mst_pend
2 DIBRAM_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for dibram_ramecc_pend
1 AXISFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axisfifo_ramecc_pend
0 AXIMFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for aximfifo_ramecc_pend

2.5.1.13 PCIE0_AGGR_ENABLE_SET Register (Offset = 200h) [reset = 0]

Short Description: AGGR interrupt enable set Register

Long Description:

Return to Summary Table

Table 12-1499 Instance Table
Instance Name Base Address
PCIE0 0071 8200h
Figure 12-766 PCIE0_AGGR_ENABLE_SET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/W1TS R/W1TS
0 0

Access Types Legend

Table 12-1500 AGGR_ENABLE_SET Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 TIMEOUT R/W1TS 0h Interrupt enable set for svbus timeout errors
0 PARITY R/W1TS 0h Interrupt enable set for Parity errors

2.5.1.14 PCIE0_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = 0]

Short Description: AGGR interrupt enable clear Register

Long Description:

Return to Summary Table

Table 12-1501 Instance Table
Instance Name Base Address
PCIE0 0071 8204h
Figure 12-767 PCIE0_AGGR_ENABLE_CLR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/W1TC R/W1TC
0 0

Access Types Legend

Table 12-1502 AGGR_ENABLE_CLR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 TIMEOUT R/W1TC 0h Interrupt enable clear for svbus timeout errors
0 PARITY R/W1TC 0h Interrupt enable clear for Parity errors

2.5.1.15 PCIE0_AGGR_STATUS_SET Register (Offset = 208h) [reset = 0]

Short Description: AGGR interrupt status set Register

Long Description:

Return to Summary Table

Table 12-1503 Instance Table
Instance Name Base Address
PCIE0 0071 8208h
Figure 12-768 PCIE0_AGGR_STATUS_SET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/WI R/WI
0 0

Access Types Legend

Table 12-1504 AGGR_STATUS_SET Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 - 2 TIMEOUT R/WI 0h Interrupt status set for svbus timeout errors
1 - 0 PARITY R/WI 0h Interrupt status set for Parity errors

2.5.1.16 PCIE0_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = 0]

Short Description: AGGR interrupt status clear Register

Long Description:

Return to Summary Table

Table 12-1505 Instance Table
Instance Name Base Address
PCIE0 0071 820Ch
Figure 12-769 PCIE0_AGGR_STATUS_CLR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/WD R/WD
0 0

Access Types Legend

Table 12-1506 AGGR_STATUS_CLR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 - 2 TIMEOUT R/WD 0h Interrupt status clear for svbus timeout errors
1 - 0 PARITY R/WD 0h Interrupt status clear for Parity errors

2.5.1.17 PCIE0_AGGR_REVISION Register (Offset = 0h) [reset = 1721772545]

Short Description: Aggregator Revision Register

Long Description:

Return to Summary Table

Table 12-1507 Instance Table
Instance Name Base Address
PCIE0 0071 9000h
Figure 12-770 PCIE0_REV Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCHEME BU MODULE_ID
R R R
1 10 11010100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVRTL REVMAJ CUSTOM REVMIN
R R R R
101 10 0 1

Access Types Legend

Table 12-1508 AGGR_REVISION Register Field Descriptions
Bit Field Type Reset Description
31 - 30 SCHEME R 1h Scheme
29 - 28 BU R 2h bu
27 - 16 MODULE_ID R 6A0h Module ID
15 - 11 REVRTL R 5h RTL version
10 - 8 REVMAJ R 2h Major version
7 - 6 CUSTOM R 0h Custom version
5 - 0 REVMIN R 1h Minor version

2.5.1.18 PCIE0_ECC_VECTOR Register (Offset = 8h) [reset = 0]

Short Description: ECC Vector Register

Long Description:

Return to Summary Table

Table 12-1509 Instance Table
Instance Name Base Address
PCIE0 0071 9008h
Figure 12-771 PCIE0_VECTOR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED RD_SVBUS_DONE RD_SVBUS_ADDRESS
NONE R/W1TC R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_SVBUS RESERVED ECC_VECTOR
R/W1TS NONE R/W
0 0

Access Types Legend

Table 12-1510 ECC_VECTOR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
24 RD_SVBUS_DONE R/W1TC 0h Status to indicate if read on serial VBUS is complete, write of any value will clear this bit.
23 - 16 RD_SVBUS_ADDRESS R/W 0h Read address
15 RD_SVBUS R/W1TS 0h Write 1 to trigger a read on the serial VBUS
RESERVED NONE Reserved
10 - 0 ECC_VECTOR R/W 0h Value written to select the corresponding ECC RAM for control or status

2.5.1.19 PCIE0_MISC_STATUS Register (Offset = Ch) [reset = 4]

Short Description: Misc Status

Long Description:

Return to Summary Table

Table 12-1511 Instance Table
Instance Name Base Address
PCIE0 0071 900Ch
Figure 12-772 PCIE0_STAT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUM_RAMS
NONE R
100

Access Types Legend

Table 12-1512 MISC_STATUS Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
10 - 0 NUM_RAMS R 4h Indicates the number of RAMS serviced by the ECC aggregator

2.5.1.20 PCIE0_RESERVED_SVBUS Register (Offset = 10h) [reset = 0]

Short Description: Reserved Area for Serial VBUS Registers

Long Description:

Return to Summary Table

Table 12-1513 Instance Table
Instance Name Base Address
PCIE0 0071 9010h
Figure 12-773 PCIE0_RESERVED_SVBUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1514 RESERVED_SVBUS Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Serial VBUS register data

2.5.1.21 PCIE0_SEC_EOI_REG Register (Offset = 3Ch) [reset = 0]

Short Description: EOI Register

Long Description:

Return to Summary Table

Table 12-1515 Instance Table
Instance Name Base Address
PCIE0 0071 903Ch
Figure 12-774 PCIE0_SEC_EOI_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI_WR
NONE R/W1TS
0

Access Types Legend

Table 12-1516 SEC_EOI_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 EOI_WR R/W1TS 0h EOI Register

2.5.1.22 PCIE0_SEC_STATUS_REG0 Register (Offset = 40h) [reset = 0]

Short Description: Interrupt Status Register 0

Long Description:

Return to Summary Table

Table 12-1517 Instance Table
Instance Name Base Address
PCIE0 0071 9040h
Figure 12-775 PCIE0_SEC_STATUS_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_PEND RPLYBUF_RAMECC_PEND RXCPLFIFO_RAMECC_PEND PNPFIFO_RAMECC_PEND
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1518 SEC_STATUS_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for pnpfifo_ramecc_pend

2.5.1.23 PCIE0_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = 0]

Short Description: Interrupt Enable Set Register 0

Long Description:

Return to Summary Table

Table 12-1519 Instance Table
Instance Name Base Address
PCIE0 0071 9080h
Figure 12-776 PCIE0_SEC_ENABLE_SET_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_ENABLE_SET RPLYBUF_RAMECC_ENABLE_SET RXCPLFIFO_RAMECC_ENABLE_SET PNPFIFO_RAMECC_ENABLE_SET
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1520 SEC_ENABLE_SET_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for pnpfifo_ramecc_pend

2.5.1.24 PCIE0_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = 0]

Short Description: Interrupt Enable Clear Register 0

Long Description:

Return to Summary Table

Table 12-1521 Instance Table
Instance Name Base Address
PCIE0 0071 90C0h
Figure 12-777 PCIE0_SEC_ENABLE_CLR_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_ENABLE_CLR RPLYBUF_RAMECC_ENABLE_CLR RXCPLFIFO_RAMECC_ENABLE_CLR PNPFIFO_RAMECC_ENABLE_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0

Access Types Legend

Table 12-1522 SEC_ENABLE_CLR_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for pnpfifo_ramecc_pend

2.5.1.25 PCIE0_DED_EOI_REG Register (Offset = 13Ch) [reset = 0]

Short Description: EOI Register

Long Description:

Return to Summary Table

Table 12-1523 Instance Table
Instance Name Base Address
PCIE0 0071 913Ch
Figure 12-778 PCIE0_DED_EOI_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI_WR
NONE R/W1TS
0

Access Types Legend

Table 12-1524 DED_EOI_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 EOI_WR R/W1TS 0h EOI Register

2.5.1.26 PCIE0_DED_STATUS_REG0 Register (Offset = 140h) [reset = 0]

Short Description: Interrupt Status Register 0

Long Description:

Return to Summary Table

Table 12-1525 Instance Table
Instance Name Base Address
PCIE0 0071 9140h
Figure 12-779 PCIE0_DED_STATUS_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_PEND RPLYBUF_RAMECC_PEND RXCPLFIFO_RAMECC_PEND PNPFIFO_RAMECC_PEND
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1526 DED_STATUS_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_PEND R/W1TS 0h Interrupt Pending Status for pnpfifo_ramecc_pend

2.5.1.27 PCIE0_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = 0]

Short Description: Interrupt Enable Set Register 0

Long Description:

Return to Summary Table

Table 12-1527 Instance Table
Instance Name Base Address
PCIE0 0071 9180h
Figure 12-780 PCIE0_DED_ENABLE_SET_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_ENABLE_SET RPLYBUF_RAMECC_ENABLE_SET RXCPLFIFO_RAMECC_ENABLE_SET PNPFIFO_RAMECC_ENABLE_SET
NONE R/W1TS R/W1TS R/W1TS R/W1TS
0 0 0 0

Access Types Legend

Table 12-1528 DED_ENABLE_SET_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_ENABLE_SET R/W1TS 0h Interrupt Enable Set Register for pnpfifo_ramecc_pend

2.5.1.28 PCIE0_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = 0]

Short Description: Interrupt Enable Clear Register 0

Long Description:

Return to Summary Table

Table 12-1529 Instance Table
Instance Name Base Address
PCIE0 0071 91C0h
Figure 12-781 PCIE0_DED_ENABLE_CLR_REG0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED AXISRODR_RAMECC_ENABLE_CLR RPLYBUF_RAMECC_ENABLE_CLR RXCPLFIFO_RAMECC_ENABLE_CLR PNPFIFO_RAMECC_ENABLE_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0

Access Types Legend

Table 12-1530 DED_ENABLE_CLR_REG0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 AXISRODR_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for axisrodr_ramecc_pend
2 RPLYBUF_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for rplybuf_ramecc_pend
1 RXCPLFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for rxcplfifo_ramecc_pend
0 PNPFIFO_RAMECC_ENABLE_CLR R/W1TC 0h Interrupt Enable Clear Register for pnpfifo_ramecc_pend

2.5.1.29 PCIE0_AGGR_ENABLE_SET Register (Offset = 200h) [reset = 0]

Short Description: AGGR interrupt enable set Register

Long Description:

Return to Summary Table

Table 12-1531 Instance Table
Instance Name Base Address
PCIE0 0071 9200h
Figure 12-782 PCIE0_AGGR_ENABLE_SET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/W1TS R/W1TS
0 0

Access Types Legend

Table 12-1532 AGGR_ENABLE_SET Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 TIMEOUT R/W1TS 0h Interrupt enable set for svbus timeout errors
0 PARITY R/W1TS 0h Interrupt enable set for Parity errors

2.5.1.30 PCIE0_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = 0]

Short Description: AGGR interrupt enable clear Register

Long Description:

Return to Summary Table

Table 12-1533 Instance Table
Instance Name Base Address
PCIE0 0071 9204h
Figure 12-783 PCIE0_AGGR_ENABLE_CLR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/W1TC R/W1TC
0 0

Access Types Legend

Table 12-1534 AGGR_ENABLE_CLR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 TIMEOUT R/W1TC 0h Interrupt enable clear for svbus timeout errors
0 PARITY R/W1TC 0h Interrupt enable clear for Parity errors

2.5.1.31 PCIE0_AGGR_STATUS_SET Register (Offset = 208h) [reset = 0]

Short Description: AGGR interrupt status set Register

Long Description:

Return to Summary Table

Table 12-1535 Instance Table
Instance Name Base Address
PCIE0 0071 9208h
Figure 12-784 PCIE0_AGGR_STATUS_SET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/WI R/WI
0 0

Access Types Legend

Table 12-1536 AGGR_STATUS_SET Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 - 2 TIMEOUT R/WI 0h Interrupt status set for svbus timeout errors
1 - 0 PARITY R/WI 0h Interrupt status set for Parity errors

2.5.1.32 PCIE0_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = 0]

Short Description: AGGR interrupt status clear Register

Long Description:

Return to Summary Table

Table 12-1537 Instance Table
Instance Name Base Address
PCIE0 0071 920Ch
Figure 12-785 PCIE0_AGGR_STATUS_CLR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TIMEOUT PARITY
NONE R/WD R/WD
0 0

Access Types Legend

Table 12-1538 AGGR_STATUS_CLR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
3 - 2 TIMEOUT R/WD 0h Interrupt status clear for svbus timeout errors
1 - 0 PARITY R/WD 0h Interrupt status clear for Parity errors

2.5.1.33 PCIE0_ADDR0 Register (Offset = 400000h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1539 Instance Table
Instance Name Base Address
PCIE0 0D40 0000h
Figure 12-786 PCIE0_ATU_WRAPPER_OB_0_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1540 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.34 PCIE0_ADDR1 Register (Offset = 400004h) [reset = 0]

Short Description:

Long Description:

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Table 12-1541 Instance Table
Instance Name Base Address
PCIE0 0D40 0004h
Figure 12-787 PCIE0_ATU_WRAPPER_OB_0_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1542 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.35 PCIE0_DESC0 Register (Offset = 400008h) [reset = 0]

Short Description:

Long Description:

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Table 12-1543 Instance Table
Instance Name Base Address
PCIE0 0D40 0008h
Figure 12-788 PCIE0_ATU_WRAPPER_OB_0_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1544 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.36 PCIE0_DESC1 Register (Offset = 40000Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1545 Instance Table
Instance Name Base Address
PCIE0 0D40 000Ch
Figure 12-789 PCIE0_ATU_WRAPPER_OB_0_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1546 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.37 PCIE0_DESC3 Register (Offset = 400014h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1547 Instance Table
Instance Name Base Address
PCIE0 0D40 0014h
Figure 12-790 PCIE0_ATU_WRAPPER_OB_0_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1548 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.38 PCIE0_AXI_ADDR0 Register (Offset = 400018h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1549 Instance Table
Instance Name Base Address
PCIE0 0D40 0018h
Figure 12-791 PCIE0_ATU_WRAPPER_OB_0_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1550 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.39 PCIE0_AXI_ADDR1 Register (Offset = 40001Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1551 Instance Table
Instance Name Base Address
PCIE0 0D40 001Ch
Figure 12-792 PCIE0_ATU_WRAPPER_OB_0_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1552 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.40 PCIE0_ADDR0 Register (Offset = 400020h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1553 Instance Table
Instance Name Base Address
PCIE0 0D40 0020h
Figure 12-793 PCIE0_ATU_WRAPPER_OB_1_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1554 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.41 PCIE0_ADDR1 Register (Offset = 400024h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1555 Instance Table
Instance Name Base Address
PCIE0 0D40 0024h
Figure 12-794 PCIE0_ATU_WRAPPER_OB_1_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1556 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.42 PCIE0_DESC0 Register (Offset = 400028h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1557 Instance Table
Instance Name Base Address
PCIE0 0D40 0028h
Figure 12-795 PCIE0_ATU_WRAPPER_OB_1_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1558 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.43 PCIE0_DESC1 Register (Offset = 40002Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1559 Instance Table
Instance Name Base Address
PCIE0 0D40 002Ch
Figure 12-796 PCIE0_ATU_WRAPPER_OB_1_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1560 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.44 PCIE0_DESC3 Register (Offset = 400034h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1561 Instance Table
Instance Name Base Address
PCIE0 0D40 0034h
Figure 12-797 PCIE0_ATU_WRAPPER_OB_1_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1562 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.45 PCIE0_AXI_ADDR0 Register (Offset = 400038h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1563 Instance Table
Instance Name Base Address
PCIE0 0D40 0038h
Figure 12-798 PCIE0_ATU_WRAPPER_OB_1_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1564 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.46 PCIE0_AXI_ADDR1 Register (Offset = 40003Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1565 Instance Table
Instance Name Base Address
PCIE0 0D40 003Ch
Figure 12-799 PCIE0_ATU_WRAPPER_OB_1_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1566 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.47 PCIE0_ADDR0 Register (Offset = 400040h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1567 Instance Table
Instance Name Base Address
PCIE0 0D40 0040h
Figure 12-800 PCIE0_ATU_WRAPPER_OB_2_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1568 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.48 PCIE0_ADDR1 Register (Offset = 400044h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1569 Instance Table
Instance Name Base Address
PCIE0 0D40 0044h
Figure 12-801 PCIE0_ATU_WRAPPER_OB_2_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1570 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.49 PCIE0_DESC0 Register (Offset = 400048h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1571 Instance Table
Instance Name Base Address
PCIE0 0D40 0048h
Figure 12-802 PCIE0_ATU_WRAPPER_OB_2_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1572 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.50 PCIE0_DESC1 Register (Offset = 40004Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1573 Instance Table
Instance Name Base Address
PCIE0 0D40 004Ch
Figure 12-803 PCIE0_ATU_WRAPPER_OB_2_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1574 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.51 PCIE0_DESC3 Register (Offset = 400054h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1575 Instance Table
Instance Name Base Address
PCIE0 0D40 0054h
Figure 12-804 PCIE0_ATU_WRAPPER_OB_2_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1576 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.52 PCIE0_AXI_ADDR0 Register (Offset = 400058h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1577 Instance Table
Instance Name Base Address
PCIE0 0D40 0058h
Figure 12-805 PCIE0_ATU_WRAPPER_OB_2_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1578 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.53 PCIE0_AXI_ADDR1 Register (Offset = 40005Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1579 Instance Table
Instance Name Base Address
PCIE0 0D40 005Ch
Figure 12-806 PCIE0_ATU_WRAPPER_OB_2_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1580 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.54 PCIE0_ADDR0 Register (Offset = 400060h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1581 Instance Table
Instance Name Base Address
PCIE0 0D40 0060h
Figure 12-807 PCIE0_ATU_WRAPPER_OB_3_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1582 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.55 PCIE0_ADDR1 Register (Offset = 400064h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1583 Instance Table
Instance Name Base Address
PCIE0 0D40 0064h
Figure 12-808 PCIE0_ATU_WRAPPER_OB_3_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1584 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.56 PCIE0_DESC0 Register (Offset = 400068h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1585 Instance Table
Instance Name Base Address
PCIE0 0D40 0068h
Figure 12-809 PCIE0_ATU_WRAPPER_OB_3_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1586 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.57 PCIE0_DESC1 Register (Offset = 40006Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1587 Instance Table
Instance Name Base Address
PCIE0 0D40 006Ch
Figure 12-810 PCIE0_ATU_WRAPPER_OB_3_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1588 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.58 PCIE0_DESC3 Register (Offset = 400074h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1589 Instance Table
Instance Name Base Address
PCIE0 0D40 0074h
Figure 12-811 PCIE0_ATU_WRAPPER_OB_3_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1590 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.59 PCIE0_AXI_ADDR0 Register (Offset = 400078h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1591 Instance Table
Instance Name Base Address
PCIE0 0D40 0078h
Figure 12-812 PCIE0_ATU_WRAPPER_OB_3_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1592 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.60 PCIE0_AXI_ADDR1 Register (Offset = 40007Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1593 Instance Table
Instance Name Base Address
PCIE0 0D40 007Ch
Figure 12-813 PCIE0_ATU_WRAPPER_OB_3_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1594 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.61 PCIE0_ADDR0 Register (Offset = 400080h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1595 Instance Table
Instance Name Base Address
PCIE0 0D40 0080h
Figure 12-814 PCIE0_ATU_WRAPPER_OB_4_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1596 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.62 PCIE0_ADDR1 Register (Offset = 400084h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1597 Instance Table
Instance Name Base Address
PCIE0 0D40 0084h
Figure 12-815 PCIE0_ATU_WRAPPER_OB_4_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1598 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.63 PCIE0_DESC0 Register (Offset = 400088h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1599 Instance Table
Instance Name Base Address
PCIE0 0D40 0088h
Figure 12-816 PCIE0_ATU_WRAPPER_OB_4_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1600 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.64 PCIE0_DESC1 Register (Offset = 40008Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1601 Instance Table
Instance Name Base Address
PCIE0 0D40 008Ch
Figure 12-817 PCIE0_ATU_WRAPPER_OB_4_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1602 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.65 PCIE0_DESC3 Register (Offset = 400094h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1603 Instance Table
Instance Name Base Address
PCIE0 0D40 0094h
Figure 12-818 PCIE0_ATU_WRAPPER_OB_4_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1604 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.66 PCIE0_AXI_ADDR0 Register (Offset = 400098h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1605 Instance Table
Instance Name Base Address
PCIE0 0D40 0098h
Figure 12-819 PCIE0_ATU_WRAPPER_OB_4_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1606 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.67 PCIE0_AXI_ADDR1 Register (Offset = 40009Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1607 Instance Table
Instance Name Base Address
PCIE0 0D40 009Ch
Figure 12-820 PCIE0_ATU_WRAPPER_OB_4_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1608 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.68 PCIE0_ADDR0 Register (Offset = 4000A0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1609 Instance Table
Instance Name Base Address
PCIE0 0D40 00A0h
Figure 12-821 PCIE0_ATU_WRAPPER_OB_5_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1610 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.69 PCIE0_ADDR1 Register (Offset = 4000A4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1611 Instance Table
Instance Name Base Address
PCIE0 0D40 00A4h
Figure 12-822 PCIE0_ATU_WRAPPER_OB_5_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1612 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.70 PCIE0_DESC0 Register (Offset = 4000A8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1613 Instance Table
Instance Name Base Address
PCIE0 0D40 00A8h
Figure 12-823 PCIE0_ATU_WRAPPER_OB_5_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1614 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.71 PCIE0_DESC1 Register (Offset = 4000ACh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1615 Instance Table
Instance Name Base Address
PCIE0 0D40 00ACh
Figure 12-824 PCIE0_ATU_WRAPPER_OB_5_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1616 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.72 PCIE0_DESC3 Register (Offset = 4000B4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1617 Instance Table
Instance Name Base Address
PCIE0 0D40 00B4h
Figure 12-825 PCIE0_ATU_WRAPPER_OB_5_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1618 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.73 PCIE0_AXI_ADDR0 Register (Offset = 4000B8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1619 Instance Table
Instance Name Base Address
PCIE0 0D40 00B8h
Figure 12-826 PCIE0_ATU_WRAPPER_OB_5_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1620 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.74 PCIE0_AXI_ADDR1 Register (Offset = 4000BCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1621 Instance Table
Instance Name Base Address
PCIE0 0D40 00BCh
Figure 12-827 PCIE0_ATU_WRAPPER_OB_5_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1622 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.75 PCIE0_ADDR0 Register (Offset = 4000C0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1623 Instance Table
Instance Name Base Address
PCIE0 0D40 00C0h
Figure 12-828 PCIE0_ATU_WRAPPER_OB_6_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1624 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.76 PCIE0_ADDR1 Register (Offset = 4000C4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1625 Instance Table
Instance Name Base Address
PCIE0 0D40 00C4h
Figure 12-829 PCIE0_ATU_WRAPPER_OB_6_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1626 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.77 PCIE0_DESC0 Register (Offset = 4000C8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1627 Instance Table
Instance Name Base Address
PCIE0 0D40 00C8h
Figure 12-830 PCIE0_ATU_WRAPPER_OB_6_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1628 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.78 PCIE0_DESC1 Register (Offset = 4000CCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1629 Instance Table
Instance Name Base Address
PCIE0 0D40 00CCh
Figure 12-831 PCIE0_ATU_WRAPPER_OB_6_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1630 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.79 PCIE0_DESC3 Register (Offset = 4000D4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1631 Instance Table
Instance Name Base Address
PCIE0 0D40 00D4h
Figure 12-832 PCIE0_ATU_WRAPPER_OB_6_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1632 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.80 PCIE0_AXI_ADDR0 Register (Offset = 4000D8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1633 Instance Table
Instance Name Base Address
PCIE0 0D40 00D8h
Figure 12-833 PCIE0_ATU_WRAPPER_OB_6_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1634 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.81 PCIE0_AXI_ADDR1 Register (Offset = 4000DCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1635 Instance Table
Instance Name Base Address
PCIE0 0D40 00DCh
Figure 12-834 PCIE0_ATU_WRAPPER_OB_6_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1636 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.82 PCIE0_ADDR0 Register (Offset = 4000E0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1637 Instance Table
Instance Name Base Address
PCIE0 0D40 00E0h
Figure 12-835 PCIE0_ATU_WRAPPER_OB_7_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1638 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.83 PCIE0_ADDR1 Register (Offset = 4000E4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1639 Instance Table
Instance Name Base Address
PCIE0 0D40 00E4h
Figure 12-836 PCIE0_ATU_WRAPPER_OB_7_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1640 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.84 PCIE0_DESC0 Register (Offset = 4000E8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1641 Instance Table
Instance Name Base Address
PCIE0 0D40 00E8h
Figure 12-837 PCIE0_ATU_WRAPPER_OB_7_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1642 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.85 PCIE0_DESC1 Register (Offset = 4000ECh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1643 Instance Table
Instance Name Base Address
PCIE0 0D40 00ECh
Figure 12-838 PCIE0_ATU_WRAPPER_OB_7_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1644 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.86 PCIE0_DESC3 Register (Offset = 4000F4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1645 Instance Table
Instance Name Base Address
PCIE0 0D40 00F4h
Figure 12-839 PCIE0_ATU_WRAPPER_OB_7_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1646 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.87 PCIE0_AXI_ADDR0 Register (Offset = 4000F8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1647 Instance Table
Instance Name Base Address
PCIE0 0D40 00F8h
Figure 12-840 PCIE0_ATU_WRAPPER_OB_7_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1648 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.88 PCIE0_AXI_ADDR1 Register (Offset = 4000FCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1649 Instance Table
Instance Name Base Address
PCIE0 0D40 00FCh
Figure 12-841 PCIE0_ATU_WRAPPER_OB_7_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1650 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.89 PCIE0_ADDR0 Register (Offset = 400100h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1651 Instance Table
Instance Name Base Address
PCIE0 0D40 0100h
Figure 12-842 PCIE0_ATU_WRAPPER_OB_8_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1652 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.90 PCIE0_ADDR1 Register (Offset = 400104h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1653 Instance Table
Instance Name Base Address
PCIE0 0D40 0104h
Figure 12-843 PCIE0_ATU_WRAPPER_OB_8_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1654 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.91 PCIE0_DESC0 Register (Offset = 400108h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1655 Instance Table
Instance Name Base Address
PCIE0 0D40 0108h
Figure 12-844 PCIE0_ATU_WRAPPER_OB_8_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1656 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.92 PCIE0_DESC1 Register (Offset = 40010Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1657 Instance Table
Instance Name Base Address
PCIE0 0D40 010Ch
Figure 12-845 PCIE0_ATU_WRAPPER_OB_8_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1658 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.93 PCIE0_DESC3 Register (Offset = 400114h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1659 Instance Table
Instance Name Base Address
PCIE0 0D40 0114h
Figure 12-846 PCIE0_ATU_WRAPPER_OB_8_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1660 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.94 PCIE0_AXI_ADDR0 Register (Offset = 400118h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1661 Instance Table
Instance Name Base Address
PCIE0 0D40 0118h
Figure 12-847 PCIE0_ATU_WRAPPER_OB_8_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1662 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.95 PCIE0_AXI_ADDR1 Register (Offset = 40011Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1663 Instance Table
Instance Name Base Address
PCIE0 0D40 011Ch
Figure 12-848 PCIE0_ATU_WRAPPER_OB_8_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1664 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.96 PCIE0_ADDR0 Register (Offset = 400120h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1665 Instance Table
Instance Name Base Address
PCIE0 0D40 0120h
Figure 12-849 PCIE0_ATU_WRAPPER_OB_9_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1666 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.97 PCIE0_ADDR1 Register (Offset = 400124h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1667 Instance Table
Instance Name Base Address
PCIE0 0D40 0124h
Figure 12-850 PCIE0_ATU_WRAPPER_OB_9_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1668 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.98 PCIE0_DESC0 Register (Offset = 400128h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1669 Instance Table
Instance Name Base Address
PCIE0 0D40 0128h
Figure 12-851 PCIE0_ATU_WRAPPER_OB_9_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1670 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.99 PCIE0_DESC1 Register (Offset = 40012Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1671 Instance Table
Instance Name Base Address
PCIE0 0D40 012Ch
Figure 12-852 PCIE0_ATU_WRAPPER_OB_9_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1672 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.100 PCIE0_DESC3 Register (Offset = 400134h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1673 Instance Table
Instance Name Base Address
PCIE0 0D40 0134h
Figure 12-853 PCIE0_ATU_WRAPPER_OB_9_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1674 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.101 PCIE0_AXI_ADDR0 Register (Offset = 400138h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1675 Instance Table
Instance Name Base Address
PCIE0 0D40 0138h
Figure 12-854 PCIE0_ATU_WRAPPER_OB_9_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1676 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0hT The value programmed in this field + 1 gives the region size

2.5.1.102 PCIE0_AXI_ADDR1 Register (Offset = 40013Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1677 Instance Table
Instance Name Base Address
PCIE0 0D40 013Ch
Figure 12-855 PCIE0_ATU_WRAPPER_OB_9_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1678 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.103 PCIE0_ADDR0 Register (Offset = 400140h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1679 Instance Table
Instance Name Base Address
PCIE0 0D40 0140h
Figure 12-856 PCIE0_ATU_WRAPPER_OB_10_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1680 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.104 PCIE0_ADDR1 Register (Offset = 400144h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1681 Instance Table
Instance Name Base Address
PCIE0 0D40 0144h
Figure 12-857 PCIE0_ATU_WRAPPER_OB_10_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1682 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.105 PCIE0_DESC0 Register (Offset = 400148h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1683 Instance Table
Instance Name Base Address
PCIE0 0D40 0148h
Figure 12-858 PCIE0_ATU_WRAPPER_OB_10_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1684 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.106 PCIE0_DESC1 Register (Offset = 40014Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1685 Instance Table
Instance Name Base Address
PCIE0 0D40 014Ch
Figure 12-859 PCIE0_ATU_WRAPPER_OB_10_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1686 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.107 PCIE0_DESC3 Register (Offset = 400154h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1687 Instance Table
Instance Name Base Address
PCIE0 0D40 0154h
Figure 12-860 PCIE0_ATU_WRAPPER_OB_10_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1688 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.108 PCIE0_AXI_ADDR0 Register (Offset = 400158h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1689 Instance Table
Instance Name Base Address
PCIE0 0D40 0158h
Figure 12-861 PCIE0_ATU_WRAPPER_OB_10_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1690 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.109 PCIE0_AXI_ADDR1 Register (Offset = 40015Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1691 Instance Table
Instance Name Base Address
PCIE0 0D40 015Ch
Figure 12-862 PCIE0_ATU_WRAPPER_OB_10_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1692 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.110 PCIE0_ADDR0 Register (Offset = 400160h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1693 Instance Table
Instance Name Base Address
PCIE0 0D40 0160h
Figure 12-863 PCIE0_ATU_WRAPPER_OB_11_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1694 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.111 PCIE0_ADDR1 Register (Offset = 400164h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1695 Instance Table
Instance Name Base Address
PCIE0 0D40 0164h
Figure 12-864 PCIE0_ATU_WRAPPER_OB_11_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1696 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.112 PCIE0_DESC0 Register (Offset = 400168h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1697 Instance Table
Instance Name Base Address
PCIE0 0D40 0168h
Figure 12-865 PCIE0_ATU_WRAPPER_OB_11_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1698 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.113 PCIE0_DESC1 Register (Offset = 40016Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1699 Instance Table
Instance Name Base Address
PCIE0 0D40 016Ch
Figure 12-866 PCIE0_ATU_WRAPPER_OB_11_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1700 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.114 PCIE0_DESC3 Register (Offset = 400174h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1701 Instance Table
Instance Name Base Address
PCIE0 0D40 0174h
Figure 12-867 PCIE0_ATU_WRAPPER_OB_11_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1702 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.115 PCIE0_AXI_ADDR0 Register (Offset = 400178h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1703 Instance Table
Instance Name Base Address
PCIE0 0D40 0178h
Figure 12-868 PCIE0_ATU_WRAPPER_OB_11_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1704 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.116 PCIE0_AXI_ADDR1 Register (Offset = 40017Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1705 Instance Table
Instance Name Base Address
PCIE0 0D40 017Ch
Figure 12-869 PCIE0_ATU_WRAPPER_OB_11_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1706 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.117 PCIE0_ADDR0 Register (Offset = 400180h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1707 Instance Table
Instance Name Base Address
PCIE0 0D40 0180h
Figure 12-870 PCIE0_ATU_WRAPPER_OB_12_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1708 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.118 PCIE0_ADDR1 Register (Offset = 400184h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1709 Instance Table
Instance Name Base Address
PCIE0 0D40 0184h
Figure 12-871 PCIE0_ATU_WRAPPER_OB_12_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1710 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.119 PCIE0_DESC0 Register (Offset = 400188h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1711 Instance Table
Instance Name Base Address
PCIE0 0D40 0188h
Figure 12-872 PCIE0_ATU_WRAPPER_OB_12_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1712 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.120 PCIE0_DESC1 Register (Offset = 40018Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1713 Instance Table
Instance Name Base Address
PCIE0 0D40 018Ch
Figure 12-873 PCIE0_ATU_WRAPPER_OB_12_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1714 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.121 PCIE0_DESC3 Register (Offset = 400194h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1715 Instance Table
Instance Name Base Address
PCIE0 0D40 0194h
Figure 12-874 PCIE0_ATU_WRAPPER_OB_12_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1716 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.122 PCIE0_AXI_ADDR0 Register (Offset = 400198h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1717 Instance Table
Instance Name Base Address
PCIE0 0D40 0198h
Figure 12-875 PCIE0_ATU_WRAPPER_OB_12_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1718 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.123 PCIE0_AXI_ADDR1 Register (Offset = 40019Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1719 Instance Table
Instance Name Base Address
PCIE0 0D40 019Ch
Figure 12-876 PCIE0_ATU_WRAPPER_OB_12_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1720 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.124 PCIE0_ADDR0 Register (Offset = 4001A0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1721 Instance Table
Instance Name Base Address
PCIE0 0D40 01A0h
Figure 12-877 PCIE0_ATU_WRAPPER_OB_13_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1722 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.125 PCIE0_ADDR1 Register (Offset = 4001A4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1723 Instance Table
Instance Name Base Address
PCIE0 0D40 01A4h
Figure 12-878 PCIE0_ATU_WRAPPER_OB_13_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1724 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.126 PCIE0_DESC0 Register (Offset = 4001A8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1725 Instance Table
Instance Name Base Address
PCIE0 0D40 01A8h
Figure 12-879 PCIE0_ATU_WRAPPER_OB_13_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1726 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.127 PCIE0_DESC1 Register (Offset = 4001ACh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1727 Instance Table
Instance Name Base Address
PCIE0 0D40 01ACh
Figure 12-880 PCIE0_ATU_WRAPPER_OB_13_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1728 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.128 PCIE0_DESC3 Register (Offset = 4001B4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1729 Instance Table
Instance Name Base Address
PCIE0 0D40 01B4h
Figure 12-881 PCIE0_ATU_WRAPPER_OB_13_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1730 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.129 PCIE0_AXI_ADDR0 Register (Offset = 4001B8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1731 Instance Table
Instance Name Base Address
PCIE0 0D40 01B8h
Figure 12-882 PCIE0_ATU_WRAPPER_OB_13_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1732 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.130 PCIE0_AXI_ADDR1 Register (Offset = 4001BCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1733 Instance Table
Instance Name Base Address
PCIE0 0D40 01BCh
Figure 12-883 PCIE0_ATU_WRAPPER_OB_13_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1734 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.131 PCIE0_ADDR0 Register (Offset = 4001C0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1735 Instance Table
Instance Name Base Address
PCIE0 0D40 01C0h
Figure 12-884 PCIE0_ATU_WRAPPER_OB_14_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1736 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.132 PCIE0_ADDR1 Register (Offset = 4001C4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1737 Instance Table
Instance Name Base Address
PCIE0 0D40 01C4h
Figure 12-885 PCIE0_ATU_WRAPPER_OB_14_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1738 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.133 PCIE0_DESC0 Register (Offset = 4001C8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1739 Instance Table
Instance Name Base Address
PCIE0 0D40 01C8h
Figure 12-886 PCIE0_ATU_WRAPPER_OB_14_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1740 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.134 PCIE0_DESC1 Register (Offset = 4001CCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1741 Instance Table
Instance Name Base Address
PCIE0 0D40 01CCh
Figure 12-887 PCIE0_ATU_WRAPPER_OB_14_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1742 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.135 PCIE0_DESC3 Register (Offset = 4001D4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1743 Instance Table
Instance Name Base Address
PCIE0 0D40 01D4h
Figure 12-888 PCIE0_ATU_WRAPPER_OB_14_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1744 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.136 PCIE0_AXI_ADDR0 Register (Offset = 4001D8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1745 Instance Table
Instance Name Base Address
PCIE0 0D40 01D8h
Figure 12-889 PCIE0_ATU_WRAPPER_OB_14_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1746 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.137 PCIE0_AXI_ADDR1 Register (Offset = 4001DCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1747 Instance Table
Instance Name Base Address
PCIE0 0D40 01DCh
Figure 12-890 PCIE0_ATU_WRAPPER_OB_14_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1748 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.138 PCIE0_ADDR0 Register (Offset = 4001E0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1749 Instance Table
Instance Name Base Address
PCIE0 0D40 01E0h
Figure 12-891 PCIE0_ATU_WRAPPER_OB_15_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1750 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.139 PCIE0_ADDR1 Register (Offset = 4001E4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1751 Instance Table
Instance Name Base Address
PCIE0 0D40 01E4h
Figure 12-892 PCIE0_ATU_WRAPPER_OB_15_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1752 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.140 PCIE0_DESC0 Register (Offset = 4001E8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1753 Instance Table
Instance Name Base Address
PCIE0 0D40 01E8h
Figure 12-893 PCIE0_ATU_WRAPPER_OB_15_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1754 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.141 PCIE0_DESC1 Register (Offset = 4001ECh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1755 Instance Table
Instance Name Base Address
PCIE0 0D40 01ECh
Figure 12-894 PCIE0_ATU_WRAPPER_OB_15_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1756 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.142 PCIE0_DESC3 Register (Offset = 4001F4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1757 Instance Table
Instance Name Base Address
PCIE0 0D40 01F4h
Figure 12-895 PCIE0_ATU_WRAPPER_OB_15_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1758 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.143 PCIE0_AXI_ADDR0 Register (Offset = 4001F8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1759 Instance Table
Instance Name Base Address
PCIE0 0D40 01F8h
Figure 12-896 PCIE0_ATU_WRAPPER_OB_15_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1760 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.144 PCIE0_AXI_ADDR1 Register (Offset = 4001FCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1761 Instance Table
Instance Name Base Address
PCIE0 0D40 01FCh
Figure 12-897 PCIE0_ATU_WRAPPER_OB_15_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1762 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.145 PCIE0_ADDR0 Register (Offset = 400200h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1763 Instance Table
Instance Name Base Address
PCIE0 0D40 0200h
Figure 12-898 PCIE0_ATU_WRAPPER_OB_16_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1764 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.146 PCIE0_ADDR1 Register (Offset = 400204h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1765 Instance Table
Instance Name Base Address
PCIE0 0D40 0204h
Figure 12-899 PCIE0_ATU_WRAPPER_OB_16_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1766 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.147 PCIE0_DESC0 Register (Offset = 400208h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1767 Instance Table
Instance Name Base Address
PCIE0 0D40 0208h
Figure 12-900 PCIE0_ATU_WRAPPER_OB_16_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1768 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.148 PCIE0_DESC1 Register (Offset = 40020Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1769 Instance Table
Instance Name Base Address
PCIE0 0D40 020Ch
Figure 12-901 PCIE0_ATU_WRAPPER_OB_16_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1770 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.149 PCIE0_DESC3 Register (Offset = 400214h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1771 Instance Table
Instance Name Base Address
PCIE0 0D40 0214h
Figure 12-902 PCIE0_ATU_WRAPPER_OB_16_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1772 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.150 PCIE0_AXI_ADDR0 Register (Offset = 400218h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1773 Instance Table
Instance Name Base Address
PCIE0 0D40 0218h
Figure 12-903 PCIE0_ATU_WRAPPER_OB_16_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1774 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.151 PCIE0_AXI_ADDR1 Register (Offset = 40021Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1775 Instance Table
Instance Name Base Address
PCIE0 0D40 021Ch
Figure 12-904 PCIE0_ATU_WRAPPER_OB_16_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1776 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.152 PCIE0_ADDR0 Register (Offset = 400220h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1777 Instance Table
Instance Name Base Address
PCIE0 0D40 0220h
Figure 12-905 PCIE0_ATU_WRAPPER_OB_17_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1778 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.153 PCIE0_ADDR1 Register (Offset = 400224h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1779 Instance Table
Instance Name Base Address
PCIE0 0D40 0224h
Figure 12-906 PCIE0_ATU_WRAPPER_OB_17_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1780 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.154 PCIE0_DESC0 Register (Offset = 400228h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1781 Instance Table
Instance Name Base Address
PCIE0 0D40 0228h
Figure 12-907 PCIE0_ATU_WRAPPER_OB_17_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1782 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.155 PCIE0_DESC1 Register (Offset = 40022Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1783 Instance Table
Instance Name Base Address
PCIE0 0D40 022Ch
Figure 12-908 PCIE0_ATU_WRAPPER_OB_17_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1784 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.156 PCIE0_DESC3 Register (Offset = 400234h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1785 Instance Table
Instance Name Base Address
PCIE0 0D40 0234h
Figure 12-909 PCIE0_ATU_WRAPPER_OB_17_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1786 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.157 PCIE0_AXI_ADDR0 Register (Offset = 400238h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1787 Instance Table
Instance Name Base Address
PCIE0 0D40 0238h
Figure 12-910 PCIE0_ATU_WRAPPER_OB_17_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1788 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.158 PCIE0_AXI_ADDR1 Register (Offset = 40023Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1789 Instance Table
Instance Name Base Address
PCIE0 0D40 023Ch
Figure 12-911 PCIE0_ATU_WRAPPER_OB_17_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1790 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.159 PCIE0_ADDR0 Register (Offset = 400240h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1791 Instance Table
Instance Name Base Address
PCIE0 0D40 0240h
Figure 12-912 PCIE0_ATU_WRAPPER_OB_18_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1792 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.160 PCIE0_ADDR1 Register (Offset = 400244h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1793 Instance Table
Instance Name Base Address
PCIE0 0D40 0244h
Figure 12-913 PCIE0_ATU_WRAPPER_OB_18_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1794 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.161 PCIE0_DESC0 Register (Offset = 400248h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1795 Instance Table
Instance Name Base Address
PCIE0 0D40 0248h
Figure 12-914 PCIE0_ATU_WRAPPER_OB_18_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1796 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.162 PCIE0_DESC1 Register (Offset = 40024Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1797 Instance Table
Instance Name Base Address
PCIE0 0D40 024Ch
Figure 12-915 PCIE0_ATU_WRAPPER_OB_18_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1798 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.163 PCIE0_DESC3 Register (Offset = 400254h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1799 Instance Table
Instance Name Base Address
PCIE0 0D40 0254h
Figure 12-916 PCIE0_ATU_WRAPPER_OB_18_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1800 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.164 PCIE0_AXI_ADDR0 Register (Offset = 400258h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1801 Instance Table
Instance Name Base Address
PCIE0 0D40 0258h
Figure 12-917 PCIE0_ATU_WRAPPER_OB_18_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1802 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.165 PCIE0_AXI_ADDR1 Register (Offset = 40025Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1803 Instance Table
Instance Name Base Address
PCIE0 0D40 025Ch
Figure 12-918 PCIE0_ATU_WRAPPER_OB_18_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1804 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.166 PCIE0_ADDR0 Register (Offset = 400260h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1805 Instance Table
Instance Name Base Address
PCIE0 0D40 0260h
Figure 12-919 PCIE0_ATU_WRAPPER_OB_19_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1806 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.167 PCIE0_ADDR1 Register (Offset = 400264h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1807 Instance Table
Instance Name Base Address
PCIE0 0D40 0264h
Figure 12-920 PCIE0_ATU_WRAPPER_OB_19_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1808 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.168 PCIE0_DESC0 Register (Offset = 400268h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1809 Instance Table
Instance Name Base Address
PCIE0 0D40 0268h
Figure 12-921 PCIE0_ATU_WRAPPER_OB_19_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1810 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.169 PCIE0_DESC1 Register (Offset = 40026Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1811 Instance Table
Instance Name Base Address
PCIE0 0D40 026Ch
Figure 12-922 PCIE0_ATU_WRAPPER_OB_19_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1812 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.170 PCIE0_DESC3 Register (Offset = 400274h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1813 Instance Table
Instance Name Base Address
PCIE0 0D40 0274h
Figure 12-923 PCIE0_ATU_WRAPPER_OB_19_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1814 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.171 PCIE0_AXI_ADDR0 Register (Offset = 400278h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1815 Instance Table
Instance Name Base Address
PCIE0 0D40 0278h
Figure 12-924 PCIE0_ATU_WRAPPER_OB_19_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1816 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.172 PCIE0_AXI_ADDR1 Register (Offset = 40027Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1817 Instance Table
Instance Name Base Address
PCIE0 0D40 027Ch
Figure 12-925 PCIE0_ATU_WRAPPER_OB_19_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1818 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.173 PCIE0_ADDR0 Register (Offset = 400280h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1819 Instance Table
Instance Name Base Address
PCIE0 0D40 0280h
Figure 12-926 PCIE0_ATU_WRAPPER_OB_20_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1820 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.174 PCIE0_ADDR1 Register (Offset = 400284h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1821 Instance Table
Instance Name Base Address
PCIE0 0D40 0284h
Figure 12-927 PCIE0_ATU_WRAPPER_OB_20_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1822 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.175 PCIE0_DESC0 Register (Offset = 400288h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1823 Instance Table
Instance Name Base Address
PCIE0 0D40 0288h
Figure 12-928 PCIE0_ATU_WRAPPER_OB_20_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1824 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.176 PCIE0_DESC1 Register (Offset = 40028Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1825 Instance Table
Instance Name Base Address
PCIE0 0D40 028Ch
Figure 12-929 PCIE0_ATU_WRAPPER_OB_20_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1826 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.177 PCIE0_DESC3 Register (Offset = 400294h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1827 Instance Table
Instance Name Base Address
PCIE0 0D40 0294h
Figure 12-930 PCIE0_ATU_WRAPPER_OB_20_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1828 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.178 PCIE0_AXI_ADDR0 Register (Offset = 400298h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1829 Instance Table
Instance Name Base Address
PCIE0 0D40 0298h
Figure 12-931 PCIE0_ATU_WRAPPER_OB_20_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1830 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.179 PCIE0_AXI_ADDR1 Register (Offset = 40029Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1831 Instance Table
Instance Name Base Address
PCIE0 0D40 029Ch
Figure 12-932 PCIE0_ATU_WRAPPER_OB_20_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1832 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.180 PCIE0_ADDR0 Register (Offset = 4002A0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1833 Instance Table
Instance Name Base Address
PCIE0 0D40 02A0h
Figure 12-933 PCIE0_ATU_WRAPPER_OB_21_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1834 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.181 PCIE0_ADDR1 Register (Offset = 4002A4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1835 Instance Table
Instance Name Base Address
PCIE0 0D40 02A4h
Figure 12-934 PCIE0_ATU_WRAPPER_OB_21_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1836 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.182 PCIE0_DESC0 Register (Offset = 4002A8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1837 Instance Table
Instance Name Base Address
PCIE0 0D40 02A8h
Figure 12-935 PCIE0_ATU_WRAPPER_OB_21_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1838 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.183 PCIE0_DESC1 Register (Offset = 4002ACh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1839 Instance Table
Instance Name Base Address
PCIE0 0D40 02ACh
Figure 12-936 PCIE0_ATU_WRAPPER_OB_21_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1840 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.184 PCIE0_DESC3 Register (Offset = 4002B4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1841 Instance Table
Instance Name Base Address
PCIE0 0D40 02B4h
Figure 12-937 PCIE0_ATU_WRAPPER_OB_21_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1842 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.185 PCIE0_AXI_ADDR0 Register (Offset = 4002B8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1843 Instance Table
Instance Name Base Address
PCIE0 0D40 02B8h
Figure 12-938 PCIE0_ATU_WRAPPER_OB_21_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1844 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.186 PCIE0_AXI_ADDR1 Register (Offset = 4002BCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1845 Instance Table
Instance Name Base Address
PCIE0 0D40 02BCh
Figure 12-939 PCIE0_ATU_WRAPPER_OB_21_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1846 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.187 PCIE0_ADDR0 Register (Offset = 4002C0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1847 Instance Table
Instance Name Base Address
PCIE0 0D40 02C0h
Figure 12-940 PCIE0_ATU_WRAPPER_OB_22_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1848 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.188 PCIE0_ADDR1 Register (Offset = 4002C4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1849 Instance Table
Instance Name Base Address
PCIE0 0D40 02C4h
Figure 12-941 PCIE0_ATU_WRAPPER_OB_22_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1850 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.189 PCIE0_DESC0 Register (Offset = 4002C8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1851 Instance Table
Instance Name Base Address
PCIE0 0D40 02C8h
Figure 12-942 PCIE0_ATU_WRAPPER_OB_22_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1852 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.190 PCIE0_DESC1 Register (Offset = 4002CCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1853 Instance Table
Instance Name Base Address
PCIE0 0D40 02CCh
Figure 12-943 PCIE0_ATU_WRAPPER_OB_22_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1854 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.191 PCIE0_DESC3 Register (Offset = 4002D4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1855 Instance Table
Instance Name Base Address
PCIE0 0D40 02D4h
Figure 12-944 PCIE0_ATU_WRAPPER_OB_22_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1856 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.192 PCIE0_AXI_ADDR0 Register (Offset = 4002D8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1857 Instance Table
Instance Name Base Address
PCIE0 0D40 02D8h
Figure 12-945 PCIE0_ATU_WRAPPER_OB_22_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1858 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.193 PCIE0_AXI_ADDR1 Register (Offset = 4002DCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1859 Instance Table
Instance Name Base Address
PCIE0 0D40 02DCh
Figure 12-946 PCIE0_ATU_WRAPPER_OB_22_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1860 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.194 PCIE0_ADDR0 Register (Offset = 4002E0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1861 Instance Table
Instance Name Base Address
PCIE0 0D40 02E0h
Figure 12-947 PCIE0_ATU_WRAPPER_OB_23_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1862 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.195 PCIE0_ADDR1 Register (Offset = 4002E4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1863 Instance Table
Instance Name Base Address
PCIE0 0D40 02E4h
Figure 12-948 PCIE0_ATU_WRAPPER_OB_23_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1864 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.196 PCIE0_DESC0 Register (Offset = 4002E8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1865 Instance Table
Instance Name Base Address
PCIE0 0D40 02E8h
Figure 12-949 PCIE0_ATU_WRAPPER_OB_23_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1866 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.197 PCIE0_DESC1 Register (Offset = 4002ECh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1867 Instance Table
Instance Name Base Address
PCIE0 0D40 02ECh
Figure 12-950 PCIE0_ATU_WRAPPER_OB_23_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1868 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.198 PCIE0_DESC3 Register (Offset = 4002F4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1869 Instance Table
Instance Name Base Address
PCIE0 0D40 02F4h
Figure 12-951 PCIE0_ATU_WRAPPER_OB_23_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1870 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.199 PCIE0_AXI_ADDR0 Register (Offset = 4002F8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1871 Instance Table
Instance Name Base Address
PCIE0 0D40 02F8h
Figure 12-952 PCIE0_ATU_WRAPPER_OB_23_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1872 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.200 PCIE0_AXI_ADDR1 Register (Offset = 4002FCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1873 Instance Table
Instance Name Base Address
PCIE0 0D40 02FCh
Figure 12-953 PCIE0_ATU_WRAPPER_OB_23_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1874 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.201 PCIE0_ADDR0 Register (Offset = 400300h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1875 Instance Table
Instance Name Base Address
PCIE0 0D40 0300h
Figure 12-954 PCIE0_ATU_WRAPPER_OB_24_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1876 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.202 PCIE0_ADDR1 Register (Offset = 400304h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1877 Instance Table
Instance Name Base Address
PCIE0 0D40 0304h
Figure 12-955 PCIE0_ATU_WRAPPER_OB_24_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1878 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.203 PCIE0_DESC0 Register (Offset = 400308h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1879 Instance Table
Instance Name Base Address
PCIE0 0D40 0308h
Figure 12-956 PCIE0_ATU_WRAPPER_OB_24_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1880 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.204 PCIE0_DESC1 Register (Offset = 40030Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1881 Instance Table
Instance Name Base Address
PCIE0 0D40 030Ch
Figure 12-957 PCIE0_ATU_WRAPPER_OB_24_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1882 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.205 PCIE0_DESC3 Register (Offset = 400314h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1883 Instance Table
Instance Name Base Address
PCIE0 0D40 0314h
Figure 12-958 PCIE0_ATU_WRAPPER_OB_24_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1884 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.206 PCIE0_AXI_ADDR0 Register (Offset = 400318h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1885 Instance Table
Instance Name Base Address
PCIE0 0D40 0318h
Figure 12-959 PCIE0_ATU_WRAPPER_OB_24_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1886 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.207 PCIE0_AXI_ADDR1 Register (Offset = 40031Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1887 Instance Table
Instance Name Base Address
PCIE0 0D40 031Ch
Figure 12-960 PCIE0_ATU_WRAPPER_OB_24_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1888 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.208 PCIE0_ADDR0 Register (Offset = 400320h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1889 Instance Table
Instance Name Base Address
PCIE0 0D40 0320h
Figure 12-961 PCIE0_ATU_WRAPPER_OB_25_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1890 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.209 PCIE0_ADDR1 Register (Offset = 400324h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1891 Instance Table
Instance Name Base Address
PCIE0 0D40 0324h
Figure 12-962 PCIE0_ATU_WRAPPER_OB_25_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1892 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.210 PCIE0_DESC0 Register (Offset = 400328h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1893 Instance Table
Instance Name Base Address
PCIE0 0D40 0328h
Figure 12-963 PCIE0_ATU_WRAPPER_OB_25_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1894 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.211 PCIE0_DESC1 Register (Offset = 40032Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1895 Instance Table
Instance Name Base Address
PCIE0 0D40 032Ch
Figure 12-964 PCIE0_ATU_WRAPPER_OB_25_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1896 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.212 PCIE0_DESC3 Register (Offset = 400334h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1897 Instance Table
Instance Name Base Address
PCIE0 0D40 0334h
Figure 12-965 PCIE0_ATU_WRAPPER_OB_25_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1898 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.213 PCIE0_AXI_ADDR0 Register (Offset = 400338h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1899 Instance Table
Instance Name Base Address
PCIE0 0D40 0338h
Figure 12-966 PCIE0_ATU_WRAPPER_OB_25_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1900 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.214 PCIE0_AXI_ADDR1 Register (Offset = 40033Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1901 Instance Table
Instance Name Base Address
PCIE0 0D40 033Ch
Figure 12-967 PCIE0_ATU_WRAPPER_OB_25_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1902 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.215 PCIE0_ADDR0 Register (Offset = 400340h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1903 Instance Table
Instance Name Base Address
PCIE0 0D40 0340h
Figure 12-968 PCIE0_ATU_WRAPPER_OB_26_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1904 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.216 PCIE0_ADDR1 Register (Offset = 400344h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1905 Instance Table
Instance Name Base Address
PCIE0 0D40 0344h
Figure 12-969 PCIE0_ATU_WRAPPER_OB_26_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1906 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.217 PCIE0_DESC0 Register (Offset = 400348h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1907 Instance Table
Instance Name Base Address
PCIE0 0D40 0348h
Figure 12-970 PCIE0_ATU_WRAPPER_OB_26_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1908 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.218 PCIE0_DESC1 Register (Offset = 40034Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1909 Instance Table
Instance Name Base Address
PCIE0 0D40 034Ch
Figure 12-971 PCIE0_ATU_WRAPPER_OB_26_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1910 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.219 PCIE0_DESC3 Register (Offset = 400354h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1911 Instance Table
Instance Name Base Address
PCIE0 0D40 0354h
Figure 12-972 PCIE0_ATU_WRAPPER_OB_26_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1912 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.220 PCIE0_AXI_ADDR0 Register (Offset = 400358h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1913 Instance Table
Instance Name Base Address
PCIE0 0D40 0358h
Figure 12-973 PCIE0_ATU_WRAPPER_OB_26_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1914 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.221 PCIE0_AXI_ADDR1 Register (Offset = 40035Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1915 Instance Table
Instance Name Base Address
PCIE0 0D40 035Ch
Figure 12-974 PCIE0_ATU_WRAPPER_OB_26_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1916 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.222 PCIE0_ADDR0 Register (Offset = 400360h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1917 Instance Table
Instance Name Base Address
PCIE0 0D40 0360h
Figure 12-975 PCIE0_ATU_WRAPPER_OB_27_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1918 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.223 PCIE0_ADDR1 Register (Offset = 400364h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1919 Instance Table
Instance Name Base Address
PCIE0 0D40 0364h
Figure 12-976 PCIE0_ATU_WRAPPER_OB_27_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1920 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.224 PCIE0_DESC0 Register (Offset = 400368h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1921 Instance Table
Instance Name Base Address
PCIE0 0D40 0368h
Figure 12-977 PCIE0_ATU_WRAPPER_OB_27_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1922 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.225 PCIE0_DESC1 Register (Offset = 40036Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1923 Instance Table
Instance Name Base Address
PCIE0 0D40 036Ch
Figure 12-978 PCIE0_ATU_WRAPPER_OB_27_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1924 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.226 PCIE0_DESC3 Register (Offset = 400374h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1925 Instance Table
Instance Name Base Address
PCIE0 0D40 0374h
Figure 12-979 PCIE0_ATU_WRAPPER_OB_27_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1926 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.227 PCIE0_AXI_ADDR0 Register (Offset = 400378h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1927 Instance Table
Instance Name Base Address
PCIE0 0D40 0378h
Figure 12-980 PCIE0_ATU_WRAPPER_OB_27_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1928 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.228 PCIE0_AXI_ADDR1 Register (Offset = 40037Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1929 Instance Table
Instance Name Base Address
PCIE0 0D40 037Ch
Figure 12-981 PCIE0_ATU_WRAPPER_OB_27_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1930 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.229 PCIE0_ADDR0 Register (Offset = 400380h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1931 Instance Table
Instance Name Base Address
PCIE0 0D40 0380h
Figure 12-982 PCIE0_ATU_WRAPPER_OB_28_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1932 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.230 PCIE0_ADDR1 Register (Offset = 400384h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1933 Instance Table
Instance Name Base Address
PCIE0 0D40 0384h
Figure 12-983 PCIE0_ATU_WRAPPER_OB_28_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1934 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.231 PCIE0_DESC0 Register (Offset = 400388h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1935 Instance Table
Instance Name Base Address
PCIE0 0D40 0388h
Figure 12-984 PCIE0_ATU_WRAPPER_OB_28_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1936 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.232 PCIE0_DESC1 Register (Offset = 40038Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1937 Instance Table
Instance Name Base Address
PCIE0 0D40 038Ch
Figure 12-985 PCIE0_ATU_WRAPPER_OB_28_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1938 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.233 PCIE0_DESC3 Register (Offset = 400394h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1939 Instance Table
Instance Name Base Address
PCIE0 0D40 0394h
Figure 12-986 PCIE0_ATU_WRAPPER_OB_28_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1940 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.234 PCIE0_AXI_ADDR0 Register (Offset = 400398h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1941 Instance Table
Instance Name Base Address
PCIE0 0D40 0398h
Figure 12-987 PCIE0_ATU_WRAPPER_OB_28_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1942 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.235 PCIE0_AXI_ADDR1 Register (Offset = 40039Ch) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1943 Instance Table
Instance Name Base Address
PCIE0 0D40 039Ch
Figure 12-988 PCIE0_ATU_WRAPPER_OB_28_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1944 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.236 PCIE0_ADDR0 Register (Offset = 4003A0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1945 Instance Table
Instance Name Base Address
PCIE0 0D40 03A0h
Figure 12-989 PCIE0_ATU_WRAPPER_OB_29_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1946 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.237 PCIE0_ADDR1 Register (Offset = 4003A4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1947 Instance Table
Instance Name Base Address
PCIE0 0D40 03A4h
Figure 12-990 PCIE0_ATU_WRAPPER_OB_29_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1948 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.238 PCIE0_DESC0 Register (Offset = 4003A8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1949 Instance Table
Instance Name Base Address
PCIE0 0D40 03A8h
Figure 12-991 PCIE0_ATU_WRAPPER_OB_29_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1950 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.239 PCIE0_DESC1 Register (Offset = 4003ACh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1951 Instance Table
Instance Name Base Address
PCIE0 0D40 03ACh
Figure 12-992 PCIE0_ATU_WRAPPER_OB_29_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1952 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.240 PCIE0_DESC3 Register (Offset = 4003B4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1953 Instance Table
Instance Name Base Address
PCIE0 0D40 03B4h
Figure 12-993 PCIE0_ATU_WRAPPER_OB_29_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1954 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.241 PCIE0_AXI_ADDR0 Register (Offset = 4003B8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1955 Instance Table
Instance Name Base Address
PCIE0 0D40 03B8h
Figure 12-994 PCIE0_ATU_WRAPPER_OB_29_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1956 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.242 PCIE0_AXI_ADDR1 Register (Offset = 4003BCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1957 Instance Table
Instance Name Base Address
PCIE0 0D40 03BCh
Figure 12-995 PCIE0_ATU_WRAPPER_OB_29_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1958 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.243 PCIE0_ADDR0 Register (Offset = 4003C0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1959 Instance Table
Instance Name Base Address
PCIE0 0D40 03C0h
Figure 12-996 PCIE0_ATU_WRAPPER_OB_31_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1960 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.244 PCIE0_ADDR1 Register (Offset = 4003C4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1961 Instance Table
Instance Name Base Address
PCIE0 0D40 03C4h
Figure 12-997 PCIE0_ATU_WRAPPER_OB_31_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1962 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.245 PCIE0_DESC0 Register (Offset = 4003C8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1963 Instance Table
Instance Name Base Address
PCIE0 0D40 03C8h
Figure 12-998 PCIE0_ATU_WRAPPER_OB_31_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1964 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.246 PCIE0_DESC1 Register (Offset = 4003CCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1965 Instance Table
Instance Name Base Address
PCIE0 0D40 03CCh
Figure 12-999 PCIE0_ATU_WRAPPER_OB_31_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1966 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.247 PCIE0_DESC3 Register (Offset = 4003D4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1967 Instance Table
Instance Name Base Address
PCIE0 0D40 03D4h
Figure 12-1000 PCIE0_ATU_WRAPPER_OB_31_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1968 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.248 PCIE0_AXI_ADDR0 Register (Offset = 4003D8h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1969 Instance Table
Instance Name Base Address
PCIE0 0D40 03D8h
Figure 12-1001 PCIE0_ATU_WRAPPER_OB_31_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1970 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.249 PCIE0_AXI_ADDR1 Register (Offset = 4003DCh) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1971 Instance Table
Instance Name Base Address
PCIE0 0D40 03DCh
Figure 12-1002 PCIE0_ATU_WRAPPER_OB_31_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1972 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.250 PCIE0_ADDR0 Register (Offset = 4003E0h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-1973 Instance Table
Instance Name Base Address
PCIE0 0D40 03E0h
Figure 12-1003 PCIE0_ATU_WRAPPER_OB_32_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1974 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of PCIe Address Register for region N
7 - 6 RSVD R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h Number_bits + 1 bits are passed through from AXI address to the PCIe address

2.5.1.251 PCIE0_ADDR1 Register (Offset = 4003E4h) [reset = 0]

Short Description:

Long Description:

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Table 12-1975 Instance Table
Instance Name Base Address
PCIE0 0D40 03E4h
Figure 12-1004 PCIE0_ATU_WRAPPER_OB_32_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1976 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of PCIe Address Register for region N

2.5.1.252 PCIE0_DESC0 Register (Offset = 4003E8h) [reset = 0]

Short Description:

Long Description:

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Table 12-1977 Instance Table
Instance Name Base Address
PCIE0 0D40 03E8h
Figure 12-1005 PCIE0_ATU_WRAPPER_OB_32_DESC0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1978 DESC0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lowest 32-bits of PCIe Descriptor Register for region N

2.5.1.253 PCIE0_DESC1 Register (Offset = 4003ECh) [reset = 0]

Short Description:

Long Description:

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Table 12-1979 Instance Table
Instance Name Base Address
PCIE0 0D40 03ECh
Figure 12-1006 PCIE0_ATU_WRAPPER_OB_32_DESC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1980 DESC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Lower middle 32-bits of PCIe Descriptor Register for region N

2.5.1.254 PCIE0_DESC3 Register (Offset = 4003F4h) [reset = 0]

Short Description:

Long Description:

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Table 12-1981 Instance Table
Instance Name Base Address
PCIE0 0D40 03F4h
Figure 12-1007 PCIE0_ATU_WRAPPER_OB_32_DESC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD DATA
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1982 DESC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 23 RSVD R 0h reserved
22 - 0 DATA R/W 0h {Execute Permission Supported, Privileged Mode Supported, PASID Value, PASID present bit}

2.5.1.255 PCIE0_AXI_ADDR0 Register (Offset = 4003F8h) [reset = 0]

Short Description:

Long Description:

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Table 12-1983 Instance Table
Instance Name Base Address
PCIE0 0D40 03F8h
Figure 12-1008 PCIE0_ATU_WRAPPER_OB_32_AXI_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD REGION_SIZE
R/W R/W R/W
0 0 0

Access Types Legend

Table 12-1984 AXI_ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of Outbound AXI Region Base Address Register used to decode the region
7 - 6 RSVD R/W 0h These needs to be forced to 0
5 - 0 REGION_SIZE R/W 0h The value programmed in this field + 1 gives the region size

2.5.1.256 PCIE0_AXI_ADDR1 Register (Offset = 4003FCh) [reset = 0]

Short Description:

Long Description:

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Table 12-1985 Instance Table
Instance Name Base Address
PCIE0 0D40 03FCh
Figure 12-1009 PCIE0_ATU_WRAPPER_OB_32_AXI_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1986 AXI_ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI outbound Base Address Register used to decode the region

2.5.1.257 PCIE0_ADDR0 Register (Offset = 400800h) [reset = 0]

Short Description:

Long Description:

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Table 12-1987 Instance Table
Instance Name Base Address
PCIE0 0D40 0800h
Figure 12-1010 PCIE0_ATU_WRAPPER_IB_0_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD0 NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1988 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of AXI Address Register for BAR N
7 - 6 RSVD0 R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h The value programmed in this register +1 bits are passed through from PCIe to AXI

2.5.1.258 PCIE0_ADDR1 Register (Offset = 400804h) [reset = 0]

Short Description:

Long Description:

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Table 12-1989 Instance Table
Instance Name Base Address
PCIE0 0D40 0804h
Figure 12-1011 PCIE0_ATU_WRAPPER_IB_0_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1990 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI Address Register for BAR N

2.5.1.259 PCIE0_ADDR0 Register (Offset = 400808h) [reset = 0]

Short Description:

Long Description:

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Table 12-1991 Instance Table
Instance Name Base Address
PCIE0 0D40 0808h
Figure 12-1012 PCIE0_ATU_WRAPPER_IB_1_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD0 NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1992 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of AXI Address Register for BAR N
7 - 6 RSVD0 R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h The value programmed in this register +1 bits are passed through from PCIe to AXI

2.5.1.260 PCIE0_ADDR1 Register (Offset = 40080Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-1993 Instance Table
Instance Name Base Address
PCIE0 0D40 080Ch
Figure 12-1013 PCIE0_ATU_WRAPPER_IB_1_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1994 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI Address Register for BAR N

2.5.1.261 PCIE0_ADDR0 Register (Offset = 400810h) [reset = 0]

Short Description:

Long Description:

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Table 12-1995 Instance Table
Instance Name Base Address
PCIE0 0D40 0810h
Figure 12-1014 PCIE0_ATU_WRAPPER_IB_7_ADDR0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA RSVD0 NUM_BITS
R/W R R/W
0 0 0

Access Types Legend

Table 12-1996 ADDR0 Register Field Descriptions
Bit Field Type Reset Description
31 - 8 DATA R/W 0h Bits [31:8] of AXI Address Register for BAR N
7 - 6 RSVD0 R 0h Bits 7 and 6 are reserved
5 - 0 NUM_BITS R/W 0h The value programmed in this register +1 bits are passed through from PCIe to AXI

2.5.1.262 PCIE0_ADDR1 Register (Offset = 400814h) [reset = 0]

Short Description:

Long Description:

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Table 12-1997 Instance Table
Instance Name Base Address
PCIE0 0D40 0814h
Figure 12-1015 PCIE0_ATU_WRAPPER_IB_7_ADDR1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W
0

Access Types Legend

Table 12-1998 ADDR1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DATA R/W 0h Bits [63:32] of AXI Address Register for BAR N

2.5.1.263 PCIE0_C0 Register (Offset = 400820h) [reset = 4104]

Short Description:

Long Description:

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Table 12-1999 Instance Table
Instance Name Base Address
PCIE0 0D40 0820h
Figure 12-1016 PCIE0_ATU_CREDIT_THRESHOLD_C0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED HEADER
NONE R/W
1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEADER DATA
R/W R/W
1 1000

Access Types Legend

Table 12-2000 C0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
19 - 12 HEADER R/W 1h This is the threshold value of the header credits required which is used to flag credit availability in AXI wrapper
11 - 0 DATA R/W 8h This is the threshold value of the payload credits required which is used to flag credit availability in AXI wrapper

2.5.1.264 PCIE0_L0 Register (Offset = 400824h) [reset = 0]

Short Description:

Long Description:

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Table 12-2001 Instance Table
Instance Name Base Address
PCIE0 0D40 0824h
Figure 12-1017 PCIE0_ATU_LINK_DOWN_INDICATOR_BIT_L0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLEAR_LINK_DOWN_BIT_TO_PROCEED
NONE R/W
0

Access Types Legend

Table 12-2002 L0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 CLEAR_LINK_DOWN_BIT_TO_PROCEED R/W 0h This bit will be set when link down reset comes. client should clear this bit before issueing new traffic to the core

2.5.1.265 PCIE0_I_VENDOR_ID_DEVICE_ID Register (Offset = 0h) [reset = 16783309]

Short Description:

Long Description:

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Table 12-2003 Instance Table
Instance Name Base Address
PCIE0 0D00 0000h
Figure 12-1018 PCIE0_RC_I_RC_PCIE_BASE_I_VENDOR_ID_DEVICE_ID Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DID
R
100000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VID
R
1011111001101

Access Types Legend

Table 12-2004 I_VENDOR_ID_DEVICE_ID Register Field Descriptions
Bit Field Type Reset Description
31 - 16 DID R 100h Device ID assigned by the manufacturer of the device. On power-up, the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15 - 0 VID R 17CDh This is the Vendor ID assigned by PCI SIG to the manufacturer of the device. The Vendor ID is set in the Vendor ID Register within the local management register block.

2.5.1.266 PCIE0_I_COMMAND_STATUS Register (Offset = 4h) [reset = 1048576]

Short Description:

Long Description:

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Table 12-2005 Instance Table
Instance Name Base Address
PCIE0 0D00 0004h
Figure 12-1019 PCIE0_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPE SSE RMA RTA STA R6 MDPE R5 CL IS R4
R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R R/W1TC R R R R
0 0 0 0 0 0 0 0 1 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R3 IMD R2 SE R1 PERE R0 BE MSE ISE
R R/W R R/W R R/W R R/W R/W R/W
0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2006 I_COMMAND_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 DPE R/W1TC 0h This bit is set when the Controller has received a poisoned TLP. The Parity Error Response enable bit [bit 6] has no effect on the setting of this bit. This field can also be cleared from the local management bus APB by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30 SSE R/W1TC 0h The Controller sets this bit [i]On receiving an error message from the link, if SERR-Enable in PCI Command Register is 1 and SERR-Enable in the Bridge Control Register is also 1. [ii]On any internal Fatal/Non-Fatal error detected, if SERR-Enable in PCI Command Register is 1. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29 RMA R/W1TC 0h This bit is set when the Controller has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
28 RTA R/W1TC 0h This bit is set when the Controller has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
27 STA R/W1TC 0h This bit is set when the Controller has sent a completion to the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26 - 25 R6 R 0h Reserved
24 MDPE R/W1TC 0h When the Parity Error Response enable bit is 1, the Controller sets this bit when it detects the following error conditions: [i] The Controller receives a poisoned request from the link. [ii] The Controller has sent a Poisoned Completion downstream to the link This bit remains 0 when the Parity Error Response enable bit is 0. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23 - 21 R5 R 0h Reserved
20 CL R 1h Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1.
19 IS R 0h This bit is valid only when the Controller is configured to support legacy interrupts. Indicates that the Controller has a pending interrupt, that is, the Controller has sent an Assert_INTx message but has not transmitted a corresponding Deassert_INTx message.
18 - 16 R4 R 0h Reserved
15 - 11 R3 R 0h Reserved
10 IMD R/W 0h Enables or disables the transmission of INTx Assert and De-assert messages from the Controller. The setting of this bit has no effect on the operation of the Controller in the RC mode.
9 R2 R 0h Reserved
8 SE R/W 0h Enables the reporting of fatal and non-fatal errors detected by the Controller to the Root Complex.
7 R1 R 0h Reserved
6 PERE R/W 0h When this bit is 1, the Controller sets the Master Data Parity Error status bit when it detects the following error conditions: [i] The Controller receives a poisoned completion from the link in response to a request. [ii] The Controller sends out a poisoned write request on the link [this may be because an underflow occurred during the packet transfer at the host interface of the Controller.]. When this bit is 0, the Master Data Parity Error status bit is never set.
5 - 3 R0 R 0h Reserved
2 BE R/W 0h For a Function with a Type 1 Configurations Space header[Controller in RP Mode], this bit controls forwarding of Memory or I/O Requests by a Port in the Upstream direction. Note: The Controller does not generate any response based on this bit. Client application logic must use this bit and respond to requests appropriately: - When this bit is '1', Client logic can process the Memory and IO Requests received from PCIe Link normally. - When this bit is '0', Client logic must handle Memory and IO Requests received from PCIe Link as Unsupported Requests.
1 MSE R/W 0h For a Function with a Type 1 Configuration Space header[Controller in RP Mode], this bit controls the response to Memory Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit. - Client must check for this bit to be '1' before initiating any Memory requests on the pcie_master_AXI interface.
0 ISE R/W 0h For a Function with a Type 1 Configuration Space header [Controller in RP Mode] , this bit controls the response to I/O Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit. - Client must check for this bit to be '1' before initiating any IO requests on the pcie_master_AXI interface.

2.5.1.267 PCIE0_I_REVISION_ID_CLASS_CODE Register (Offset = 8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2007 Instance Table
Instance Name Base Address
PCIE0 0D00 0008h
Figure 12-1020 PCIE0_RC_I_RC_PCIE_BASE_I_REVISION_ID_CLASS_CODE Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC SCC
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIB RID
R R
0 0

Access Types Legend

Table 12-2008 I_REVISION_ID_CLASS_CODE Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CC R 0h Identifies the function of the device. On power-up, the Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23 - 16 SCC R 0h Identifies a sub-category within the selected function. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15 - 8 PIB R 0h Identifies the register set layout of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
7 - 0 RID R 0h Assigned by the manufacturer of the device to identify the revision number of the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.268 PCIE0_I_BIST_HEADER_LATENCY_CACHE_LINE Register (Offset = Ch) [reset = 65536]

Short Description:

Long Description:

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Table 12-2009 Instance Table
Instance Name Base Address
PCIE0 0D00 000Ch
Figure 12-1021 PCIE0_RC_I_RC_PCIE_BASE_I_BIST_HEADER_LATENCY_CACHE_LINE Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR DT HT
R R R
0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT CLS
R R/W
0 0

Access Types Legend

Table 12-2010 I_BIST_HEADER_LATENCY_CACHE_LINE Register Field Descriptions
Bit Field Type Reset Description
31 - 24 BR R 0h BIST control register. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
23 DT R 0h Identifies whether the device supports a single Function or multiple Functions. Hardwired to zero
22 - 16 HT R 1h Identifies format of header. This field is hardwired to 1.
15 - 8 LT R 0h This is an unused field and is hardwired to 0.
7 - 0 CLS R/W 0h Cache Line Size Register defined in PCI Specifications 3.0. This field can be read or written, both from the link and from the local management bus, but its value is not used.

2.5.1.269 PCIE0_I_RC_BAR_0 Register (Offset = 10h) [reset = 0]

Short Description:

Long Description:

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Table 12-2011 Instance Table
Instance Name Base Address
PCIE0 0D00 0010h
Figure 12-1022 PCIE0_RC_I_RC_PCIE_BASE_I_RC_BAR_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAMRW BAMR0
R/W R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAMR0 P0 S0 R7 MSI0
R R R R R
0 0 0 0 0

Access Types Legend

Table 12-2012 I_RC_BAR_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 22 BAMRW R/W 0h This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writable, and are read as 0's.
21 - 4 BAMR0 R 0h This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in Root Complex BAR Configuration Register. All other bits are not writable, and are read as 0's.
3 P0 R 0h For memory BAR: This bit reads as 1 when BAR 0 is configured as a prefetchable BAR, and as 0 when configured as a non-prefetchable BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.
2 S0 R 0h For memory BAR:This bit reads as 0 when BAR 0 is configured as a 32-bit BAR, and as 1 when configured as a 64-bit BAR. For IO BAR: This is bit 3 of the base address. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.
1 R7 R 0h This bit is hardwired to 0 for both memory and I/O BARs.
0 MSI0 R 0h Specifies whether this BAR defines a memory address range or an I/O address range [0 = memory, 1 = I/O]. The value read in this field is determined by the setting of Root Complex BAR Configuration Register.

2.5.1.270 PCIE0_I_RC_BAR_1 Register (Offset = 14h) [reset = 0]

Short Description:

Long Description:

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Table 12-2013 Instance Table
Instance Name Base Address
PCIE0 0D00 0014h
Figure 12-1023 PCIE0_RC_I_RC_PCIE_BASE_I_RC_BAR_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R7
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R7
R
0

Access Types Legend

Table 12-2014 I_RC_BAR_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 R7 R 0h This field is reserved at power-on. This can be changed using BAR configuration register in LM space.

2.5.1.271 PCIE0_I_PCIE_BUS_NUMBERS Register (Offset = 18h) [reset = 0]

Short Description:

Long Description:

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Table 12-2015 Instance Table
Instance Name Base Address
PCIE0 0D00 0018h
Figure 12-1024 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_BUS_NUMBERS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLTN SUBN
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBN PBN
R/W R/W
0 0

Access Types Legend

Table 12-2016 I_PCIE_BUS_NUMBERS Register Field Descriptions
Bit Field Type Reset Description
31 - 24 SLTN R 0h This field is not implemented.
23 - 16 SUBN R/W 0h This field can be read and written from the local management bus, but its value is not used within the Controller.
15 - 8 SBN R/W 0h This field can be read and written from the local management bus, but its value is not used within the Controller.
7 - 0 PBN R/W 0h This field can be read and written from the local management bus, but its value is not used within the Controller.

2.5.1.272 PCIE0_I_PCIE_IO_BASE_LIMIT Register (Offset = 1Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2017 Instance Table
Instance Name Base Address
PCIE0 0D00 001Ch
Figure 12-1025 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_IO_BASE_LIMIT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPE RSE RMA RTA STA R4 MPE R3
R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R R/W1TC R
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILR R2 IOBS2 IBR R1 IOBS1
R R R R R R
0 0 0 0 0 0

Access Types Legend

Table 12-2018 I_PCIE_IO_BASE_LIMIT Register Field Descriptions
Bit Field Type Reset Description
31 DPE R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30 RSE R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29 RMA R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
28 RTA R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
27 STA R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26 - 25 R4 R 0h Reserved
24 MPE R/W1TC 0h The Controller does not set this bit by itself. This bit can be cleared by writing a 1 into this bit position from the local management APB bus. This field can be forced to 1 or 0 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. Note that this bit can be set only when the Parity Error Response Enable bit is set in the Bridge Control Register
23 - 16 R3 R 0h Reserved
15 - 12 ILR R 0h This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
11 - 9 R2 R 0h Reserved
8 IOBS2 R 0h value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register].If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set, then this field will be hard coded to 0.
7 - 4 IBR R 0h This field can be read and written from the local management bus if IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
3 - 1 R1 R 0h Reserved
0 IOBS1 R 0h value set in Type1 cfg IO bar size[bit 20 of RC BAR CONFIG register]. If type1 cfg IObar enable bit[bit 19 in RC BAR CONFIG register] is not set, then this field will be hard coded to 0.

2.5.1.273 PCIE0_I_PCIE_MEM_BASE_LIMIT Register (Offset = 20h) [reset = 0]

Short Description:

Long Description:

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Table 12-2019 Instance Table
Instance Name Base Address
PCIE0 0D00 0020h
Figure 12-1026 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_MEM_BASE_LIMIT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLR R2
R/W R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBR R1
R/W R
0 0

Access Types Legend

Table 12-2020 I_PCIE_MEM_BASE_LIMIT Register Field Descriptions
Bit Field Type Reset Description
31 - 20 MLR R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
19 - 16 R2 R 0h Reserved
15 - 4 MBR R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
3 - 0 R1 R 0h Reserved

2.5.1.274 PCIE0_I_PCIE_PREFETCH_BASE_LIMIT Register (Offset = 24h) [reset = 0]

Short Description:

Long Description:

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Table 12-2021 Instance Table
Instance Name Base Address
PCIE0 0D00 0024h
Figure 12-1027 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_BASE_LIMIT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PMLR
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMBR
R
0

Access Types Legend

Table 12-2022 I_PCIE_PREFETCH_BASE_LIMIT Register Field Descriptions
Bit Field Type Reset Description
31 - 16 PMLR R 0h This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
15 - 0 PMBR R 0h This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

2.5.1.275 PCIE0_I_PCIE_PREFETCH_BASE_UPPER Register (Offset = 28h) [reset = 0]

Short Description:

Long Description:

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Table 12-2023 Instance Table
Instance Name Base Address
PCIE0 0D00 0028h
Figure 12-1028 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_BASE_UPPER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBRU
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBRU
R
0

Access Types Legend

Table 12-2024 I_PCIE_PREFETCH_BASE_UPPER Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PBRU R 0h This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

2.5.1.276 PCIE0_I_PCIE_PREFETCH_LIMIT_UPPER Register (Offset = 2Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2025 Instance Table
Instance Name Base Address
PCIE0 0D00 002Ch
Figure 12-1029 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_LIMIT_UPPER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLRU
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLRU
R
0

Access Types Legend

Table 12-2026 I_PCIE_PREFETCH_LIMIT_UPPER Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PLRU R 0h This field can be read and written from the local management APB bus if 64bit prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

2.5.1.277 PCIE0_I_PCIE_IO_BASE_LIMIT_UPPER Register (Offset = 30h) [reset = 0]

Short Description:

Long Description:

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Table 12-2027 Instance Table
Instance Name Base Address
PCIE0 0D00 0030h
Figure 12-1030 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_IO_BASE_LIMIT_UPPER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ILR
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IBRU
R
0

Access Types Legend

Table 12-2028 I_PCIE_IO_BASE_LIMIT_UPPER Register Field Descriptions
Bit Field Type Reset Description
31 - 16 ILR R 0h This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.
15 - 0 IBRU R 0h This field can be read and written from the local management bus if 32bit IO BAR is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.

2.5.1.278 PCIE0_I_CAPABILITIES_POINTER Register (Offset = 34h) [reset = 128]

Short Description:

Long Description:

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Table 12-2029 Instance Table
Instance Name Base Address
PCIE0 0D00 0034h
Figure 12-1031 PCIE0_RC_I_RC_PCIE_BASE_I_CAPABILITIES_POINTER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R15
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R15 CP
R R
0 10000000

Access Types Legend

Table 12-2030 I_CAPABILITIES_POINTER Register Field Descriptions
Bit Field Type Reset Description
31 - 8 R15 R 0h Reserved
7 - 0 CP R 80h Contains pointer to the first PCI Capability Structure. This field is set by default to the value defined in the RTL file reg_defaults.h. It can be re-written independently for every Function from the local management APB bus.

2.5.1.279 PCIE0_RSVD_0E Register (Offset = 38h) [reset = 0]

Short Description:

Long Description:

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Table 12-2031 Instance Table
Instance Name Base Address
PCIE0 0D00 0038h
Figure 12-1032 PCIE0_RC_I_RC_PCIE_BASE_RSVD_0E Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
R
0

Access Types Legend

Table 12-2032 RSVD_0E Register Field Descriptions
Bit Field Type Reset Description
31 - 0 RSVD R 0h Reserved

2.5.1.280 PCIE0_I_INTRPT_LINE_INTRPT_PIN Register (Offset = 3Ch) [reset = 511]

Short Description:

Long Description:

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Table 12-2033 Instance Table
Instance Name Base Address
PCIE0 0D00 003Ch
Figure 12-1033 PCIE0_RC_I_RC_PCIE_BASE_I_INTRPT_LINE_INTRPT_PIN Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R23 BCRSBR R21 VGA16D VGAE ISAE BCSE PERE
R R/W R R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R5 IPR ILR
R R R/W
0 1 11111111

Access Types Legend

Table 12-2034 I_INTRPT_LINE_INTRPT_PIN Register Field Descriptions
Bit Field Type Reset Description
31 - 23 R23 R 0h Reserved
22 BCRSBR R/W 0h This field can be read and written from the local management APB bus. When set, it initiates a hot reset on the link.
21 R21 R 0h Reserved
20 VGA16D R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
19 VGAE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
18 ISAE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
17 BCSE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
16 PERE R/W 0h This field can be read and written from the local management APB bus. It is used only to enable the Master Data Parity Error bit in the Secondary Status Register.
15 - 11 R5 R 0h Reserved
10 - 8 IPR R 1h Identifies the interrupt input [A, B, C, D] to which this Functions interrupt output is connected to [01 = INTA, 02 = INTB, 03 = INTC, 04 = INTD]. The assignment of interrupt inputs to Functions is fixed when the Controller is configured. This field can be re-written independently for each Function from the local management bus. Default values - PF0: 01 [INTA], PF1: 02 [INTB].
7 - 0 ILR R/W FFh This field can be read and written from the local management bus, but its value is not used within the Controller. The given reset value is for PF0.

2.5.1.281 PCIE0_I_PWR_MGMT_CAP Register (Offset = 80h) [reset = 1510182913]

Short Description:

Long Description:

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Table 12-2035 Instance Table
Instance Name Base Address
PCIE0 0D00 0080h
Figure 12-1034 PCIE0_RC_I_RC_PCIE_BASE_I_PWR_MGMT_CAP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSDCS PSDHS PSD2S PSD1S PSD0S D2S D1S MCRAPS DSI R0 PC VID
R R R R R R R R R R R R
0 1 0 1 1 0 1 0 0 0 0 11
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP CID
R R
10010000 1

Access Types Legend

Table 12-2036 I_PWR_MGMT_CAP Register Field Descriptions
Bit Field Type Reset Description
31 PSDCS R 0h Indicates whether the Function is capable of sending PME messages when in the D3cold state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
30 PSDHS R 1h Indicates whether the Function is capable of sending PME messages when in the D3hot state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
29 PSD2S R 0h Indicates whether the Function is capable of sending PME messages when in the D2 state. This bit is hardwired to 0 because D2 state is not supported.
28 PSD1S R 1h Indicates whether the Function is capable of sending PME messages when in the D1 state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register.
27 PSD0S R 1h Indicates whether the Function is capable of sending PME messages when in the D0 state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
26 D2S R 0h Set if the Function supports the D2 power state. Currently hardwired to 0.
25 D1S R 1h Set if the Function supports the D1 power state. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
24 - 22 MCRAPS R 0h Specifies the maximum current drawn by the device from the aux power source in the D3cold state. This field is not implemented in devices not supporting PME notification when in the D3cold state, and is therefore hardwired to 0.
21 DSI R 0h This bit, when set, indicates that the device requires additional configuration steps beyond setting up its PCI configuration space, to bring it to the D0 active state from the D0 uninitialized state. This bit is hardwired to 0.
20 R0 R 0h Reserved
19 PC R 0h Not applicable to PCI Express. This bit is hardwired to 0.
18 - 16 VID R 3h Indicates the version of the PCI Bus Power Management Specifications that the Function implements. This field is set by default to 011 [Version 1.2]. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15 - 8 CP R 90h Contains pointer to the next PCI Capability Structure. The Controller sets it to the value defined in the RTL file reg_defaults.h. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
7 - 0 CID R 1h Identifies that the capability structure is for Power Management. This field is set by default to 01 hex. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.282 PCIE0_I_PWR_MGMT_CTRL_STAT_REP Register (Offset = 84h) [reset = 8]

Short Description:

Long Description:

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Table 12-2037 Instance Table
Instance Name Base Address
PCIE0 0D00 0084h
Figure 12-1035 PCIE0_RC_I_RC_PCIE_BASE_I_PWR_MGMT_CTRL_STAT_REP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR R1
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMES R2 PE R3 NSR R4 PS
R/W1TC R R/W R R R R/W
0 0 0 0 1 0 0

Access Types Legend

Table 12-2038 I_PWR_MGMT_CTRL_STAT_REP Register Field Descriptions
Bit Field Type Reset Description
31 - 24 DR R 0h This optional register is not implemented in the Cadence PCIe Controller. This field is hardwired to 0.
23 - 16 R1 R 0h Reserved
15 PMES R/W1TC 0h This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write..
14 - 9 R2 R 0h Reserved
8 PE R/W 0h This bit can be set or cleared from the local management APB bus, by writing a 1 or 0, respectively.
7 - 4 R3 R 0h Reserved
3 NSR R 1h This bit is set to 1 by default. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
2 R4 R 0h Reserved
1 - 0 PS R/W 0h This field can also be read or written from the local management APBbus.

2.5.1.283 PCIE0_I_MSI_CTRL_REG Register (Offset = 90h) [reset = 25210885]

Short Description:

Long Description:

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Table 12-2039 Instance Table
Instance Name Base Address
PCIE0 0D00 0090h
Figure 12-1036 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_CTRL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 MC BAC64 MME MMC ME
R R R R/W R R/W
0 1 1 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1 CID1
R R
10110000 101

Access Types Legend

Table 12-2040 I_MSI_CTRL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 25 R0 R 0h Reserved
24 MC R 1h can be modified using localmanagement interface
23 BAC64 R 1h Set to 1 to indicate that the device is capable of generating 64-bit addresses for MSI messages.Can be modified using local management interface
22 - 20 MME R/W 0h Encodes the number of distinct messages that the Controller is programmed to generate for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. This setting must be based on the number of interrupt inputs of the Controller that are actually used by this Function. This field can be written from the local management bus.
19 - 17 MMC R 0h Encodes the number of distinct messages that the Controller is capable of generating for this Function [000 = 1, 001 = 2, 010 = 4, 011 = 8, 100 = 16, 101 = 32]. Thus, this field defines the number of the interrupt vectors for this Function. The Controller allows up to 32 distinct messages, but the setting of this field must be based on the number of interrupt inputs of the Controller that are actually used by the client. For example, if the client logic uses 8 of the 32 distinct MSI interrupt inputs of the Controller for this Function, then the value of this field must be set to 011. This field can be written from the local management bus. Please see the define den_db_Fx_MSI_MULTIPLE_MSG_CAPABLE values [where x is the function number] for default values of each function in the reg_defaults.v files.
16 ME R/W 0h Set by the configuration program to enable the MSI feature. This field can also be written from the local management bus.
15 - 8 CP1 R B0h Pointer to the next PCI Capability Structure. This can be modified from the local management bus. This field can be written from the local management bus.
7 - 0 CID1 R 5h Specifies that the capability structure is for MSI. Hardwired to 05 hex.

2.5.1.284 PCIE0_I_MSI_MSG_LOW_ADDR Register (Offset = 94h) [reset = 0]

Short Description:

Long Description:

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Table 12-2041 Instance Table
Instance Name Base Address
PCIE0 0D00 0094h
Figure 12-1037 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_MSG_LOW_ADDR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAL R1
R/W R
0 0

Access Types Legend

Table 12-2042 I_MSI_MSG_LOW_ADDR Register Field Descriptions
Bit Field Type Reset Description
31 - 2 MAL R/W 0h Lower bits of the address to be used in MSI messages. This field can also be written from the local management bus.
1 - 0 R1 R 0h The two lower bits of the address are hardwired to 0 to align the address on a double-word boundary.

2.5.1.285 PCIE0_I_MSI_MSG_HI_ADDR Register (Offset = 98h) [reset = 0]

Short Description:

Long Description:

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Table 12-2043 Instance Table
Instance Name Base Address
PCIE0 0D00 0098h
Figure 12-1038 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_MSG_HI_ADDR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAH
R/W
0

Access Types Legend

Table 12-2044 I_MSI_MSG_HI_ADDR Register Field Descriptions
Bit Field Type Reset Description
31 - 0 MAH R/W 0h Contains bits 63:32 of the 64-bit address to be used in MSI Messages. A value of 0 specifies that 32-bit addresses are to be used in the messages. This field can also be written from the local management bus.

2.5.1.286 PCIE0_I_MSI_MSG_DATA Register (Offset = 9Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2045 Instance Table
Instance Name Base Address
PCIE0 0D00 009Ch
Figure 12-1039 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_MSG_DATA Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MD
R/W
0

Access Types Legend

Table 12-2046 I_MSI_MSG_DATA Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R2 R 0h Hardwired to 0
15 - 0 MD R/W 0h Message data to be used for this Function. This field can also be written from the local management bus.

2.5.1.287 PCIE0_I_MSI_MASK Register (Offset = A0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2047 Instance Table
Instance Name Base Address
PCIE0 0D00 00A0h
Figure 12-1040 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_MASK Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MM
NONE R/W
0

Access Types Legend

Table 12-2048 I_MSI_MASK Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 MM R/W 0h Mask bits for MSI interrupts. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid mask bits.

2.5.1.288 PCIE0_I_MSI_PENDING_BITS Register (Offset = A4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2049 Instance Table
Instance Name Base Address
PCIE0 0D00 00A4h
Figure 12-1041 PCIE0_RC_I_RC_PCIE_BASE_I_MSI_PENDING_BITS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MP
NONE R
0

Access Types Legend

Table 12-2050 I_MSI_PENDING_BITS Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 MP R 0h Pending bits for MSI interrupts. This field can be written from the APB interface to reflect the current pending status.

2.5.1.289 PCIE0_I_MSIX_CTRL Register (Offset = B0h) [reset = 49169]

Short Description:

Long Description:

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Table 12-2051 Instance Table
Instance Name Base Address
PCIE0 0D00 00B0h
Figure 12-1042 PCIE0_RC_I_RC_PCIE_BASE_I_MSIX_CTRL Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSIXE FM R0 MSIXTS
R/W R/W R R
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP CID
R R
11000000 10001

Access Types Legend

Table 12-2052 I_MSIX_CTRL Register Field Descriptions
Bit Field Type Reset Description
31 MSIXE R/W 0h Set by the configuration program to enable the MSI-X feature. This field can also be written from the local management bus.
30 FM R/W 0h This bit serves as a global mask to all the interrupt conditions associated with this Function. When this bit is set, the Controller will not send out MSI-X messages from this Function. This field can also be written from the local management bus.
29 - 27 R0 R 0h Reserved
26 - 16 MSIXTS R 0h Specifies the size of the MSI-X Table, that is, the number of interrupt vectors defined for the Function. The programmed value is 1 minus the size of the table [that is, this field is set to 0 if the table size is 1.]. It can be re-written independently for each Function from the local management bus. Please see the define den_db_Fx_MSIX_TABLE_SIZE values [where x is the function number] for default values of each function in the reg_defaults.v files.
15 - 8 CP R C0h Contains pointer to the next PCI Capability Structure. This is set to point to the PCI Express Capability Structure at 30 hex. This can be rewritten independently for each Function from the local management bus.
7 - 0 CID R 11h Identifies that the capability structure is for MSI-X. This field is set by default to 11 hex. It can be rewritten independently for each Function from the local management bus.

2.5.1.290 PCIE0_I_MSIX_TBL_OFFSET Register (Offset = B4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2053 Instance Table
Instance Name Base Address
PCIE0 0D00 00B4h
Figure 12-1043 PCIE0_RC_I_RC_PCIE_BASE_I_MSIX_TBL_OFFSET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO BARI
R R
0 0

Access Types Legend

Table 12-2054 I_MSIX_TBL_OFFSET Register Field Descriptions
Bit Field Type Reset Description
31 - 3 TO R 0h Offset of the memory address where the MSI-X Table is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. Please see the define den_db_Fx_MSIX_TABLE_OFFSET values [where x is the function number] for default values of each function in the reg_defaults.v files.
2 - 0 BARI R 0h Identifies the BAR corresponding to the memory address range where the MSI-X Table is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. Please see the define den_db_Fx_MSIX_TABLE_BIR values [where x is the function number] for default values of each function in the reg_defaults.v files.

2.5.1.291 PCIE0_I_MSIX_PENDING_INTRPT Register (Offset = B8h) [reset = 8]

Short Description:

Long Description:

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Table 12-2055 Instance Table
Instance Name Base Address
PCIE0 0D00 00B8h
Figure 12-1044 PCIE0_RC_I_RC_PCIE_BASE_I_MSIX_PENDING_INTRPT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBAO
R
1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PBAO BARI1
R R
1 0

Access Types Legend

Table 12-2056 I_MSIX_PENDING_INTRPT Register Field Descriptions
Bit Field Type Reset Description
31 - 3 PBAO R 1h Offset of the memory address where the PBA is located, relative to the selected BAR. The three least significant bits of the address are omitted, as the addresses are QWORD aligned. Please see the define den_db_Fx_MSIX_PBA_OFFSET values [where x is the function number] for default values of each function in the reg_defaults.v files.
2 - 0 BARI1 R 0h Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register.Identifies the BAR corresponding to the memory address range where the PBA Structure is located [000 = BAR 0, 001 = BAR 1, ... , 101 = BAR 5]. The value programmed must be the same as the BAR Indicator configured in the MSI-X Table Offset Register. Please see the define den_db_Fx_MSIX_PBA_BIR values [where x is the function number] for default values of each function in the reg_defaults.v files.

2.5.1.292 PCIE0_I_PCIE_CAP_LIST Register (Offset = C0h) [reset = 21102608]

Short Description:

Long Description:

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Table 12-2057 Instance Table
Instance Name Base Address
PCIE0 0D00 00C0h
Figure 12-1045 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_CAP_LIST Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0 TRS IMN SI DT PCV
R R R R R R
0 0 0 1 100 10
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCP CID
R R
0 10000

Access Types Legend

Table 12-2058 I_PCIE_CAP_LIST Register Field Descriptions
Bit Field Type Reset Description
31 R0 R 0h Reserved
30 TRS R 0h When set to 1, this bit indicates that the device supports routing of Trusted Configuration Requests. Not valid for Endpoints. Hardwired to 0.
29 - 25 IMN R 0h Identifies the MSI or MSI-X interrupt vector for the interrupt message generated corresponding to the status bits in the Slot Status Register, Root Status Register, or this capability structure. This field must be defined based on the chosen interrupt mode - MSI or MSI-X. This field is hardwired to 0.
24 SI R 1h When Set, this bit indicates that the Link associated with this Port is connected to a slot
23 - 20 DT R 4h Indicates the type of device implementing this Function. This field is hardwired to 4 in the RP mode.
19 - 16 PCV R 2h Identifies the version number of the capability structure. This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0. Can be modified using local management interface after asserting input signal MGMT_TYPE1_CONFIG_REG_ACCESS high.
15 - 8 NCP R 0h Points to the next PCI capability structure. Set to 0 because this is the last capability structure.
7 - 0 CID R 10h Specifies Capability ID assigned by PCI SIG for this structure. This field is hardwired to 10 hex.

2.5.1.293 PCIE0_I_PCIE_CAP Register (Offset = C4h) [reset = 32768]

Short Description:

Long Description:

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Table 12-2059 Instance Table
Instance Name Base Address
PCIE0 0D00 00C4h
Figure 12-1046 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_CAP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R5 FLRC CPLS CSP R4
R R R R R
0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RER R3 AL1L AL0L ETFS PFS MP
R R R R R R R
1 0 0 0 0 0 0

Access Types Legend

Table 12-2060 I_PCIE_CAP Register Field Descriptions
Bit Field Type Reset Description
31 - 29 R5 R 0h Reserved
28 FLRC R 0h A value of 1b indicates the Function supports the optional Function Level Reset mechanism
27 - 26 CPLS R 0h Specifies the scale used by Slot Power Limit Value. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. .
25 - 18 CSP R 0h Specifies upper limit on power supplied by slot. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. .
17 - 16 R4 R 0h Reserved
15 RER R 1h Enables role-based errer reporting. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
14 - 12 R3 R 0h Reserved
11 - 9 AL1L R 0h Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
8 - 6 AL0L R 0h Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
5 ETFS R 0h hard coded to zero .
4 - 3 PFS R 0h This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature.
2 - 0 MP R 0h Specifies maximum payload size supported by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.294 PCIE0_I_PCIE_DEV_CTRL_STATUS Register (Offset = C8h) [reset = 10256]

Short Description:

Long Description:

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Table 12-2061 Instance Table
Instance Name Base Address
PCIE0 0D00 00C8h
Figure 12-1047 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R8 TP APD URD FED NFED CED
R R R R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R7 MRR ENS APPME PFE ETE MP ERO EURR EFER ENFER ECER
R R/W R/W R R R R/W R/W R/W R/W R/W R/W
0 10 1 0 0 0 0 1 0 0 0 0

Access Types Legend

Table 12-2062 I_PCIE_DEV_CTRL_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 22 R8 R 0h N/A
21 TP R 0h Indicates if any of the Non-Posted requests issued by the RC are still pending.
20 APD R 0h Set when auxiliary power is detected by the device. This is an unused field.
19 URD R/W1TC 0h Set to 1 by the Controller when it receives an unsupported request.
18 FED R/W1TC 0h Set to 1 by the Controller when it detects a fatal error, regardless of whether the error is masked.
17 NFED R/W1TC 0h Set to 1 by the Controller when it detects a non-fatal error, regardless of whether the error is masked.
16 CED R/W1TC 0h Set to 1 by the Controller when it detects a correctable error, regardless of whether the error is masked.
15 R7 R 0h Hardwired to 0.
14 - 12 MRR R/W 2h Specifies the maximum size allowed in read requests generated by the device.
11 ENS R/W 1h If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency.
10 APPME R 0h Hardwired to 0
9 PFE R 0h Hardwired to 0
8 ETE R 0h extended tag not enabled. Hence hard coded to zero .
7 - 5 MP R/W 0h Specifies the maximum TLP payload size configured. The device must be able to receive a TLP of this maximum size, and should not generate TLP's larger than this value. Software must set this field based on the maximum payload size in the Device Capabilities Register, and the capability of the other side.
4 ERO R/W 1h When set, this bit indicates that the device is allowed to set the Relaxed Ordering bit in the Attributes field of transactions initiated from it., when the transactions do not require Strong Ordering.
3 EURR R/W 0h This bit is used to gate the CORRECTABLE_ERROR_OUT, NON_FATAL_ERROR_OUT, FATAL_ERROR_OUT output in Root Port mode on receiving unsupported requests. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT on receiving uncorrectable unsupported requests.
2 EFER R/W 0h This bit is used to gate the FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 1 is detected Internally or when a ERR_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT.
1 ENFER R/W 0h This bit is used to gate the NON_FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 0 is detected Internally or when a ERR_NON_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of NON_FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of NON_FATAL_ERROR_OUT.
0 ECER R/W 0h This bit is used to gate the CORRECTABLE_ERROR_OUT output of the Controller in Root Port mode. When a Correctable and Unmasked Error is detected Internally or when a ERR_CORR message is received by the Controller, in Root Port mode, this bit gates the assertion of CORRECTABLE_ERROR_OUT output.

Short Description:

Long Description:

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Table 12-2063 Instance Table
Figure 12-1048 PCIE0_RC_I_RC_PCIE_BASE_I_LINK_CAP Name Register

Access Types Legend

Table 12-2064 I_LINK_CAP Register Field Descriptions

Short Description:

Long Description:

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Table 12-2065 Instance Table
Figure 12-1049 PCIE0_RC_I_RC_PCIE_BASE_I_LINK_CTRL_STATUS Name Register

Access Types Legend

Table 12-2066 I_LINK_CTRL_STATUS Register Field Descriptions

2.5.1.297 PCIE0_I_SLOT_CAPABILITY Register (Offset = D4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2067 Instance Table
Instance Name Base Address
PCIE0 0D00 00D4h
Figure 12-1050 PCIE0_RC_I_RC_PCIE_BASE_I_SLOT_CAPABILITY Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSN NCCS EIP SPLS
R R R R
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPLS SPLV HPC HPS PIP AIP MRLSP PCP ABPRSNT
R R R R R R R R R
0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2068 I_SLOT_CAPABILITY Register Field Descriptions
Bit Field Type Reset Description
31 - 19 PSN R 0h This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis, regardless of the form factor associated with the slot. This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port.
18 NCCS R 0h When Set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be Set if the hot-plug capable Port is able to accept writes to all fields of the Slot Control register without delay between successive writes.
17 EIP R 0h When Set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot.
16 - 15 SPLS R 0h Specifies the scale used for the Slot Power Limit Value . Range of Values: 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/firmware initialization is 00b.
14 - 7 SPLV R 0h In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot [see Section 6.9] or by other means to the adapter. Power limit [in Watts] is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field except when the Slot Power Limit Scale field equals 00b [1.0x] and Slot Power Limit Value exceeds EFh, the following alternative encodings are used: F0h = 250 W Slot Power Limit F1h = 275 W Slot Power Limit F2h = 300 W Slot Power Limit F3h to FFh = Reserved for Slot Power Limit values above 300 W This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/firmware initialization is 0000 0000b.
6 HPC R 0h When Set, this bit indicates that this slot is capable of supporting hot-plug operations.
5 HPS R 0h When Set, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation.
4 PIP R 0h When Set, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot.
3 AIP R 0h When Set, this bit indicates that an Attention Indicator is electrically controlled by the chassis.
2 MRLSP R 0h When Set, this bit indicates that an MRL Sensor is implemented on the chassis for this slot.
1 PCP R 0h When Set, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter [depending on form factor].
0 ABPRSNT R 0h When Set, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis.

2.5.1.298 PCIE0_I_SLOT_CTRL_STATUS Register (Offset = D8h) [reset = 2099136]

Short Description:

Long Description:

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Table 12-2069 Instance Table
Instance Name Base Address
PCIE0 0D00 00D8h
Figure 12-1051 PCIE0_RC_I_RC_PCIE_BASE_I_SLOT_CTRL_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSCS2 DLLSC EMIS PDS MRLSS CMDCMPL PDC MRLSC PFD ABPRSD
R R/W1TC R R R R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 1 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSCS1 DLLSCE EMIC PCC PIC AIC HPIE CCIE PDCE MSCE PFDE ABPE
R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 1 11 11 0 0 0 0 0 0

Access Types Legend

Table 12-2070 I_SLOT_CTRL_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 25 RSCS2 R 0h N/A
24 DLLSC R/W1TC 0h This bit is Set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event, software must read the Data Link Layer Link Active bit of the Link Status register to determine if the Link is active before initiating configuration cycles to the hot plugged device.
23 EMIS R 0h If an Electromechanical Interlock is implemented, this bit indicates the status of the Electromechanical Interlock. Defined encodings are: 0b Electromechanical Interlock Disengaged 1b Electromechanical Interlock Engaged
22 PDS R 0h This bit indicates the presence of an adapter in the slot, reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and, if present, any out-of-band presence detect mechanism defined for the slot's corresponding form factor. Note that the in-band presence detect mechanism requires that power be applied to an adapter for its presence to be detected. Consequently, form factors that require a power controller for hot-plug must implement a physical pin presence detect mechanism. Defined encodings are: 0b Slot Empty 1b Card Present in slot.
21 MRLSS R 1h This bit reports the status of the MRL sensor if implemented. Defined encodings are: 0b MRL Closed 1b MRL Open
20 CMDCMPL R/W1TC 0h If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b], this bit is Set when a hot-plug command has completed and the Hot-Plug Controller is ready to accept a subsequent command. The Command Completed status bit is Set as an indication to host software that the Hot- Plug Controller has processed the previous command and is ready to receive the next command; it provides no guarantee that the action corresponding to the command is complete. If Command Completed notification is not supported, this bit must be hardwired to 0b.
19 PDC R/W1TC 0h This bit is set when the value reported in the Presence Detect State bit is changed.
18 MRLSC R/W1TC 0h If an MRL sensor is implemented, this bit is Set when a MRL Sensor state change is detected. If an MRL sensor is not implemented, this bit must not be Set.
17 PFD R/W1TC 0h If a Power Controller that supports power fault detection is implemented, this bit is Set when the Power Controller detects a power fault at this slot. Note that, depending on hardware capability, it is possible that a power fault can be detected at any time, independent of the Power Controller Control setting or the occupancy of the slot. If power fault detection is not supported, this bit must not be Set.
16 ABPRSD R/W1TC 0h If an Attention Button is implemented, this bit is Set when the attention button is pressed. If an Attention Button is not supported, this bit must not be Set.
15 - 13 RSCS1 R 0h Reserved
12 DLLSCE R/W 0h If the Data Link Layer Link Active Reporting capability is 1b, this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active Reporting Capable bit is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
11 EMIC R 0h If an Electromechanical Interlock is implemented, a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit always returns a 0b.
10 PCC R/W 1h If a Power Controller is implemented, this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write, even if the corresponding hot-plug command is not complete, unless software issues a write, if required to, without waiting for the previous command to complete in which case the read value is undefined. The defined encodings are: 0b Power On 1b Power Off
9 - 8 PIC R/W 3h If a Power Indicator is implemented, writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write,Defined encodings are: 00b Reserved 01b On 10b Blink 11b Off
7 - 6 AIC R/W 3h If an Attention Indicator is implemented, writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write,Defined encodings are: 00b Reserved 01b On 10b Blink 11b Off
5 HPIE R/W 0h When Set, this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
4 CCIE R/W 0h If Command Completed notification is supported [if the No Command Completed Support bit in the Slot Capabilities register is 0b], when Set, this bit enables software notification when a hot-plug command is completed by the Hot-Plug Controller. If Command Completed notification is not supported, this bit must be hardwired to 0b. Default value of this bit is 0b.
3 PDCE R/W 0h When Set, this bit enables software notification on a presence detect changed event. If the Hot-Plug Capable bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
2 MSCE R/W 0h When Set, this bit enables software notification on a MRL sensor changed event If the MRL Sensor Present bit in the Slot Capabilities register is Clear, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
1 PFDE R/W 0h When Set, this bit enables software notification on a power fault event If a Power Controller that supports power fault detection is not implemented, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.
0 ABPE R/W 0h When Set to 1b, this bit enables software notification on an attention button pressed event. If the Attention Button Present bit in the Slot Capabilities register is 0b, this bit is permitted to be read-only with a value of 0b. Default value of this bit is 0b.

2.5.1.299 PCIE0_I_ROOT_CTRL_CAP Register (Offset = DCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2071 Instance Table
Instance Name Base Address
PCIE0 0D00 00DCh
Figure 12-1052 PCIE0_RC_I_RC_PCIE_BASE_I_ROOT_CTRL_CAP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R27
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R27 CRSSVE PMEIE SEFEE SENFEE SECEE
R R R/W R/W R/W R/W
0 0 0 0 0 0

Access Types Legend

Table 12-2072 I_ROOT_CTRL_CAP Register Field Descriptions
Bit Field Type Reset Description
31 - 5 R27 R 0h Reserved
4 CRSSVE R 0h This capability is not implemented and this bit is hardwired to 0b.
3 PMEIE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
2 SEFEE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
1 SENFEE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.
0 SECEE R/W 0h This field can be read and written from the local management APB bus, but its value is not used within the Controller.

2.5.1.300 PCIE0_I_ROOT_STATUS Register (Offset = E0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2073 Instance Table
Instance Name Base Address
PCIE0 0D00 00E0h
Figure 12-1053 PCIE0_RC_I_RC_PCIE_BASE_I_ROOT_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R18 PMEP PMES
R R R/W1TC
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PMERID
R
0

Access Types Legend

Table 12-2074 I_ROOT_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 18 R18 R 0h Reserved
17 PMEP R 0h This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
16 PMES R/W1TC 0h This field is not set by the Controller but can be cleared by writing a 1 from the local management APB bus. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
15 - 0 PMERID R 0h This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.301 PCIE0_I_PCIE_CAP_2 Register (Offset = E4h) [reset = 7604242]

Short Description:

Long Description:

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Table 12-2075 Instance Table
Instance Name Base Address
PCIE0 0D00 00E4h
Figure 12-1054 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_CAP_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R16 MEEP EEPS EXFS OBFF RESERVED
R R R R R NONE
0 1 1 1 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R15 RESERVED TPHC LMS R14 ACS128 ACS64 ACS32 AOPRS AFS CTDS CTR
R NONE R R R R R R R R R R
0 0 1 0 0 0 0 0 0 1 10

Access Types Legend

Table 12-2076 I_PCIE_CAP_2 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 R16 R 0h Reserved
23 - 22 MEEP R 1h Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are: 01b 1 End-End TLP Prefix 10b 2 End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write
21 EEPS R 1h Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write
20 EXFS R 1h Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all Physical Functions.
19 - 18 OBFF R 1h A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill [OBFF] capability using message signaling. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write
RESERVED NONE Reserved
15 - 14 R15 R 0h Reserved
RESERVED NONE Reserved
12 TPHC R 0h Hardwired to 0.
11 LMS R 1h A value of 1b indicates support for the optional Latency Tolerance Reporting [LTR] mechanism. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
10 R14 R 0h Reserved
9 ACS128 R 0h Hardwired to 0.
8 ACS64 R 0h Hardwired to 0.
7 ACS32 R 0h Hardwired to 0.
6 AOPRS R 0h Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
5 AFS R 0h hard coded to zero
4 CTDS R 1h A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.
3 - 0 CTR R 2h Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 [10 ms - 250 ms], but can be modified from the local management APB bus. The actual timeout values are in two programmable local management registers, which allow the timeout settings of the two sub-ranges within Range B to be programmed independently. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.302 PCIE0_I_PCIE_DEV_CTRL_STATUS_2 Register (Offset = E8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2077 Instance Table
Instance Name Base Address
PCIE0 0D00 00E8h
Figure 12-1055 PCIE0_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R20
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R20 OBFFE RESERVED R19 LTRME ICE IRE R18 AORE AFE CTD CTV
R R/W NONE R R/W R/W R/W R R R R/W R/W
0 0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2078 I_PCIE_DEV_CTRL_STATUS_2 Register Field Descriptions
Bit Field Type Reset Description
31 - 15 R20 R 0h N/A
14 - 13 OBFFE R/W 0h Enables the Optimized Buffer Flush/Fill [OBFF] capability in the device. Valid settings are 00 [disabled], 01 [Variation A], and 10 [Variation B].
RESERVED NONE Reserved
11 R19 R 0h Reserved
10 LTRME R/W 0h This must be set to 1 to enable the Latency Tolerance Reporting Mechanism. This bit is implemented only in PF 0. Its default value is 1, but can be modified from the local management bus. This bit is read-only in PF 1.
9 ICE R/W 0h When this bit is 1, the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the Completions it generates.
8 IRE R/W 0h When this bit is 1, the RC is allowed to set the ID-based Ordering [IDO] Attribute bit in the requests it generates.
7 R18 R 0h Reserved
6 AORE R 0h This bit must be set to enable the generation of Atomic Op Requests. If the client logic attempts to send an Atomic Op when this bit is not set, logic in the Controller will nullify the TLP on its way to the link.
5 AFE R 0h A 1 in this filed indicates that the port treats fields 7:0 of the ID as function number while converting a Type 1 config packet to type 0 config packet.
4 CTD R/W 0h Setting this bit disables the Completion Timeout in the device.
3 - 0 CTV R/W 0h Specifies the Completion Timeout value for the device. Allowable values are 0101 [sub-range 1] and 0110 [sub-range 2]. The corresponding timeout values are stored in the local management register's Completion Timeout Interval Registers 0 and 1, respectively. Value of 0 selects completion timeout from Completion-Timeout-Interval-Registers-0 in local management register.

Short Description:

Long Description:

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Table 12-2079 Instance Table
Figure 12-1056 PCIE0_RC_I_RC_PCIE_BASE_I_LINK_CAP_2 Name Register

Access Types Legend

Table 12-2080 I_LINK_CAP_2 Register Field Descriptions

Short Description:

Long Description:

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Table 12-2081 Instance Table
Figure 12-1057 PCIE0_RC_I_RC_PCIE_BASE_I_LINK_CTRL_STATUS_2 Name Register

Access Types Legend

Table 12-2082 I_LINK_CTRL_STATUS_2 Register Field Descriptions

2.5.1.305 PCIE0_I_AER_ENHNCD_CAP Register (Offset = 100h) [reset = 352452609]

Short Description:

Long Description:

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Table 12-2083 Instance Table
Instance Name Base Address
PCIE0 0D00 0100h
Figure 12-1058 PCIE0_RC_I_RC_PCIE_BASE_I_AER_ENHNCD_CAP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCO CV
R R
101010000 10
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECID
R
1

Access Types Legend

Table 12-2084 I_AER_ENHNCD_CAP Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NCO R 150h Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19 - 16 CV R 2h Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 4'h2.
15 - 0 PECID R 1h This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express AER Extended Capability Structure [0001 hex].

2.5.1.306 PCIE0_I_UNCORR_ERR_STATUS Register (Offset = 104h) [reset = 0]

Short Description:

Long Description:

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Table 12-2085 Instance Table
Instance Name Base Address
PCIE0 0D00 0104h
Figure 12-1059 PCIE0_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R28 UIE R27 URE EE MT RO UC
R R/W1TC R R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CA CT FCPE PT R26 SDES DLPE R25 LTE
R/W1TC R/W1TC R/W1TC R/W1TC R R/W1TC R/W1TC R R/W1TC
0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2086 I_UNCORR_ERR_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 23 R28 R 0h Reserved
22 UIE R/W1TC 0h This bit is set when the Controller has detected an internal uncorrectable error [HAL Parity error or an uncorrectable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal error through the input UNCORRECTABLE_ERROR_IN. This error is considered fatal by default.
21 R27 R 0h Reserved
20 URE R/W1TC 0h This bit is set when the Controller has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default, except for the special case outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers.
19 EE R/W1TC 0h This bit is set when the Controller has detected an ECRC error in a received TLP.
18 MT R/W1TC 0h This bit is set when the Controller receives a malformed TLP from the link. This error is considered fatal by default. The header of the received TLP with error is logged in the Header Log Registers.
17 RO R/W1TC 0h This bit is set when the Controller receives a TLP in violation of the receive credit currently available.
16 UC R/W1TC 0h This bit is set when the Controller has received an unexpected Completion packet from the link.
15 CA R/W1TC 0h This bit is set when the Controller has returned the Completer Abort [CA] status to a request received from the link. This error is considered non-fatal by default, except for the special cases outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers.
14 CT R/W1TC 0h This bit is set when the completion timer associated with an outstanding request times out. This error is considered non-fatal by default.
13 FCPE R/W1TC 0h This bit is set when certain violations of the flow control protocol are detected by the Controller.
12 PT R/W1TC 0h This bit is set when the Controller receives a poisoned TLP from the link. This error is considered non-fatal by default. The header of the received TLP with error is logged in the Header Log Registers.
11 - 6 R26 R 0h Reserved
5 SDES R/W1TC 0h This error status indicates Link up to Link down event. So Status bit is set upon LINK_DOWN_RESET_OUT event. This field is applicable to RC only and not for EP as per PCIE-spec.
4 DLPE R/W1TC 0h This bit is set when the Controller receives an Ack or Nak DLLP whose sequence does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP [for details, refer to the PCI Express Base Specifications].
3 - 1 R25 R 0h N/A
0 LTE R/W1TC 0h This error indicates that link training is not successful and transition back to detect state. This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect. This field is applicable to RC only and not for EP as per PCIE-spec.

2.5.1.307 PCIE0_I_UNCORR_ERR_MASK Register (Offset = 108h) [reset = 4194304]

Short Description:

Long Description:

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Table 12-2087 Instance Table
Instance Name Base Address
PCIE0 0D00 0108h
Figure 12-1060 PCIE0_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_MASK Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R32 UIEM R31 UREM EEM MTM ROM UCM
R R/W R R/W R/W R/W R/W R/W
0 1 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAM CTM FCPER PTM R30 SDESM DLPER R29 LTEM
R/W R/W R/W R/W R R/W R/W R R/W
0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2088 I_UNCORR_ERR_MASK Register Field Descriptions
Bit Field Type Reset Description
31 - 23 R32 R 0h Reserved
22 UIEM R/W 1h This bit is set to mask the reporting of internal errors. STICKY.
21 R31 R 0h Reserved
20 UREM R/W 0h This bit is set to mask the reporting of unexpected requests received from the link. STICKY.
19 EEM R/W 0h This bit is set to mask the reporting of ECRC errors. STICKY.
18 MTM R/W 0h This bit is set to mask the reporting of malformed TLPs received from the link. STICKY.
17 ROM R/W 0h This bit is set to mask the reporting of violations of receive credit. STICKY.
16 UCM R/W 0h This bit is set to mask the reporting of unexpected Completions received by the Controller. STICKY.
15 CAM R/W 0h This bit is set to mask the reporting of the Controller sending a Completer Abort. STICKY.
14 CTM R/W 0h This bit is set to mask the reporting of Completion Timeouts. STICKY.
13 FCPER R/W 0h This bit is set to mask the reporting of Flow Control Protocol Errors. STICKY.
12 PTM R/W 0h This bit is set to mask the reporting of a Poisoned TLP. STICKY.
11 - 6 R30 R 0h Reserved
5 SDESM R/W 0h This bit is set to mask the reporting of Surprise Down Error Status Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.
4 DLPER R/W 0h This bit is set to mask the reporting of Data Link Protocol Errors. STICKY.
3 - 1 R29 R 0h Reserved
0 LTEM R/W 0h This bit is set to mask the reporting of Link Training Error Mask. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.

2.5.1.308 PCIE0_I_UNCORR_ERR_SEVERITY Register (Offset = 10Ch) [reset = 4595760]

Short Description:

Long Description:

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Table 12-2089 Instance Table
Instance Name Base Address
PCIE0 0D00 010Ch
Figure 12-1061 PCIE0_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_SEVERITY Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R37 UNCORR_INTRNL_ERR_SVRTY R36 URES EES MTS ROS UCS
R R/W R R/W R/W R/W R/W R/W
0 1 0 0 0 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAS CTS FCPES PTS R35 SDES DLPES R33 LTES
R/W R/W R/W R/W R R/W R/W R R/W
0 0 1 0 0 1 1 0 0

Access Types Legend

Table 12-2090 I_UNCORR_ERR_SEVERITY Register Field Descriptions
Bit Field Type Reset Description
31 - 23 R37 R 0h N/A
22 UNCORR_INTRNL_ERR_SVRTY R/W 1h Severity of internal errors [0 = Non-Fatal, 1 = Fatal].
21 R36 R 0h Reserved
20 URES R/W 0h Severity of unexpected requests received from the link [0 = Non-Fatal, 1 = Fatal]. STICKY.
19 EES R/W 0h Severity of ECRC errors [0 = Non-Fatal, 1 = Fatal]. STICKY.
18 MTS R/W 1h Severity of malformed TLPs received from the link [0 = Non-Fatal, 1 = Fatal]. STICKY.
17 ROS R/W 1h Severity of receive credit violations [0 = Non-Fatal, 1 = Fatal]. STICKY.
16 UCS R/W 0h Severity of unexpected Completions received by the Controller [0 = Non-Fatal, 1 = Fatal]. STICKY.
15 CAS R/W 0h Severity of sending a Completer Abort [0 = Non-Fatal, 1 = Fatal]. STICKY.
14 CTS R/W 0h Severity of Completion Timeouts [0 = Non-Fatal, 1 = Fatal]. STICKY.
13 FCPES R/W 1h Severity of a Flow Control Protocol Error [0 = Non-Fatal, 1 = Fatal]. STICKY.
12 PTS R/W 0h Severity of a Poisoned TLP error [0 = Non-Fatal, 1 = Fatal]. STICKY.
11 - 6 R35 R 0h N/A
5 SDES R/W 1h surprise down error severity [0 = Non-Fatal, 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.
4 DLPES R/W 1h Severity of Data Link Protocol Errors [0 = Non-Fatal, 1 = Fatal]. STICKY.
3 - 1 R33 R 0h Reserved
0 LTES R/W 0h Severity of Link Training Error [0 = Non-Fatal, 1 = Fatal]. STICKY. This field is applicable to RC only and not for EP as per PCIE-spec.

2.5.1.309 PCIE0_I_CORR_ERR_STATUS Register (Offset = 110h) [reset = 0]

Short Description:

Long Description:

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Table 12-2091 Instance Table
Instance Name Base Address
PCIE0 0D00 0110h
Figure 12-1062 PCIE0_RC_I_RC_PCIE_BASE_I_CORR_ERR_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R39
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLOS CIES ANES RTTS R38 RNRS BDS BTS R37 RES
R/W1TC R/W1TC R/W1TC R/W1TC R R/W1TC R/W1TC R/W1TC R R/W1TC
0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2092 I_CORR_ERR_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R39 R 0h Reserved
15 HLOS R/W1TC 0h This bit is set on a Header Log Register overflow, that is, when the header could not be logged in the Header Log Register because it is occupied by a previous header.
14 CIES R/W1TC 0h This bit is set when the Controller has detected an internal correctable error condition [a correctable ECC error while reading from any of the RAMs]. This bit is also set in response to the client signaling an internal error through the input CORRECTABLE_ERROR_IN.
13 ANES R/W1TC 0h This bit is set when an uncorrectable error occurs, which is determined to belong to one of the special cases described in the PCI Express Base Specification 2.0. This causes the Controller to assert the CORRECTABLE_ERROR_OUT output in place of NON_FATAL_ERROR_OUT.
12 RTTS R/W1TC 0h This bit is set when the replay timer in the Data Link Layer of the Controller times out, causing the Controller to re-transmit a TLP.
11 - 9 R38 R 0h Reserved
8 RNRS R/W1TC 0h This bit is set when the replay count rolls over after three re-transmissions of a TLP at the Data Link Layer of the Controller.
7 BDS R/W1TC 0h This bit is set when an LCRC error is detected in a received DLLP, and no errors were detected by the Physical Layer.
6 BTS R/W1TC 0h This bit is set when an error is detected in a received TLP by the Data Link Layer of the Controller the conditions causing this error are [1] an LCRC error, [2] the packet terminates with EDB symbol, but its LCRC field does not equal the inverted value of the calculated CRC.
5 - 1 R37 R 0h Reserved
0 RES R/W1TC 0h This bit is set when an error is detected in the receive side of the Physical Layer of the Controller [e.g. an 8b10b decode error].

2.5.1.310 PCIE0_I_CORR_ERR_MASK Register (Offset = 114h) [reset = 57344]

Short Description:

Long Description:

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Table 12-2093 Instance Table
Instance Name Base Address
PCIE0 0D00 0114h
Figure 12-1063 PCIE0_RC_I_RC_PCIE_BASE_I_CORR_ERR_MASK Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R42
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLOM CIEM ANEM RTTM R41 RNRM BDM BTM R40 REM
R/W R/W R/W R/W R R/W R/W R/W R R/W
1 1 1 0 0 0 0 0 0 0

Access Types Legend

Table 12-2094 I_CORR_ERR_MASK Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R42 R 0h Reserved
15 HLOM R/W 1h This bit, when set, masks the reporting of an error in response to a Header Log register overflow. STICKY.
14 CIEM R/W 1h This bit, when set, masks the reporting of an error in response to a corrected internal error condition. STICKY.
13 ANEM R/W 1h This bit, when set, masks the reporting of an error in response to an uncorrectable error occurence, which is determined to belong to one of the special cases in the PCI Express Base Specification 2.0. STICKY.
12 RTTM R/W 0h This bit, when set, masks the reporting of an error in response to a Replay Timer timeout event. STICKY.
11 - 9 R41 R 0h Reserved
8 RNRM R/W 0h This bit, when set, masks the reporting of an error in response to a Replay Number Rollover event. STICKY.
7 BDM R/W 0h This bit, when set, masks the reporting of an error in response to a 'Bad DLLP' received. STICKY.
6 BTM R/W 0h This bit,when set, masks the reporting of an error in response to a 'Bad TLP' received. STICKY.
5 - 1 R40 R 0h Reserved
0 REM R/W 0h This bit, when set, masks the reporting of Physical Layer errors. STICKY.

2.5.1.311 PCIE0_I_ADV_ERR_CAP_CTL Register (Offset = 118h) [reset = 160]

Short Description:

Long Description:

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Table 12-2095 Instance Table
Instance Name Base Address
PCIE0 0D00 0118h
Figure 12-1064 PCIE0_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R43
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R43 TPLP MHRE MHRC EEC ECC EEG EGC FEP
R R R R R/W R R/W R R
0 0 0 0 0 1 0 1 0

Access Types Legend

Table 12-2096 I_ADV_ERR_CAP_CTL Register Field Descriptions
Bit Field Type Reset Description
31 - 12 R43 R 0h Reserved
11 TPLP R 0h If Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined. Default value of this bit is 0. This bit is RsvdP if the End-End TLP Prefix Supported bit is CIf Set and the First Error Pointer is valid, indicates that the TLP Prefix Log register contains valid information. If Clear or if First Error Pointer is invalid, the TLP Prefix Log register is undefined.
10 MHRE R 0h Setting this bit enables the RC to log multiple error headers in its Header Log Registers. It is hardwired to 0.
9 MHRC R 0h This bit is set when the RC has the capability to log more than one error header in its Header Log Registers. It is hardwired to 0.
8 EEC R/W 0h Setting this bit enables ECRC checking on the receive side of the Controller. This bit is writable from the local management bus. STICKY.
7 ECC R 1h This read-only bit indicates to the software that the device is capable of checking ECRC in packets received from the link.
6 EEG R/W 0h Setting this bit enables the ECRC generation on the transmit side of the Controller. This bit is writable from the local management bus. STICKY.
5 EGC R 1h This read-only bit indicates to the software that the device is capable of generating ECRC in packets transmitted on the link.
4 - 0 FEP R 0h This is a 5-bit pointer to the bit position in the Uncorrectable Error Status Register corresponding to the error that was detected first. When there are multiple bits set in the Uncorrectable Error Status Register, this field informs the software which error was observed first. To prevent the field from being overwritten before the software is able to read it, this field is not updated while the status bit it points to in the Uncorrectable Error Status Register remains set. After the software clears this status bit, a subsequent error condition that sets any bit in the Uncorrectable Error Status Register will update the First Error Pointer. Any uncorrectable error type, including the special cases where the error is reported using an ERR_COR message, will set the First Error Pointer [assuming the software has reset the error pointed by it in the Uncorrectable Error Status Register]. STICKY.

2.5.1.312 PCIE0_I_HDR_LOG_0 Register (Offset = 11Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2097 Instance Table
Instance Name Base Address
PCIE0 0D00 011Ch
Figure 12-1065 PCIE0_RC_I_RC_PCIE_BASE_I_HDR_LOG_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HD0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HD0
R
0

Access Types Legend

Table 12-2098 I_HDR_LOG_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 HD0 R 0h First Dword of captured TLP header. STICKY.

2.5.1.313 PCIE0_I_HDR_LOG_1 Register (Offset = 120h) [reset = 0]

Short Description:

Long Description:

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Table 12-2099 Instance Table
Instance Name Base Address
PCIE0 0D00 0120h
Figure 12-1066 PCIE0_RC_I_RC_PCIE_BASE_I_HDR_LOG_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HD1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HD1
R
0

Access Types Legend

Table 12-2100 I_HDR_LOG_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 HD1 R 0h Second Dword of captured TLP header. STICKY.

2.5.1.314 PCIE0_I_HDR_LOG_2 Register (Offset = 124h) [reset = 0]

Short Description:

Long Description:

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Table 12-2101 Instance Table
Instance Name Base Address
PCIE0 0D00 0124h
Figure 12-1067 PCIE0_RC_I_RC_PCIE_BASE_I_HDR_LOG_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HD2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HD2
R
0

Access Types Legend

Table 12-2102 I_HDR_LOG_2 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 HD2 R 0h Third Dword of captured TLP header. STICKY.

2.5.1.315 PCIE0_I_HDR_LOG_3 Register (Offset = 128h) [reset = 0]

Short Description:

Long Description:

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Table 12-2103 Instance Table
Instance Name Base Address
PCIE0 0D00 0128h
Figure 12-1068 PCIE0_RC_I_RC_PCIE_BASE_I_HDR_LOG_3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HD3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HD3
R
0

Access Types Legend

Table 12-2104 I_HDR_LOG_3 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 HD3 R 0h Fourth Dword of captured TLP header. STICKY.

2.5.1.316 PCIE0_I_ROOT_ERR_CMD Register (Offset = 12Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2105 Instance Table
Instance Name Base Address
PCIE0 0D00 012Ch
Figure 12-1069 PCIE0_RC_I_RC_PCIE_BASE_I_ROOT_ERR_CMD Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R44
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R44 FERE NFERE CERE
R R/W R/W R/W
0 0 0 0

Access Types Legend

Table 12-2106 I_ROOT_ERR_CMD Register Field Descriptions
Bit Field Type Reset Description
31 - 3 R44 R 0h Reserved
2 FERE R/W 0h If this bit is set, the Controller will active its FATAL_ERROR_OUT output in response to an error message received from the link.
1 NFERE R/W 0h If this bit is set, the Controller will active its NON_FATAL_ERROR_OUT output in response to an error message received from the link.
0 CERE R/W 0h If this bit is set, the Controller will active its CORRECTABLE_ERROR_OUT output in response to an error message received from the link.

2.5.1.317 PCIE0_I_ROOT_ERR_STAT Register (Offset = 130h) [reset = 0]

Short Description:

Long Description:

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Table 12-2107 Instance Table
Instance Name Base Address
PCIE0 0D00 0130h
Figure 12-1070 PCIE0_RC_I_RC_PCIE_BASE_I_ROOT_ERR_STAT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R45
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R45 FEMR NEMR FUF MEFNR EFNR MECR ECR
R R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2108 I_ROOT_ERR_STAT Register Field Descriptions
Bit Field Type Reset Description
31 - 7 R45 R 0h Reserved
6 FEMR R/W1TC 0h This bit, when set, indicates that the RC has received one or more Fatal error messages from the link. STICKY
5 NEMR R/W1TC 0h This bit, when set, indicates that the RC has received one or more Non-Fatal error messages from the link. STICKY
4 FUF R/W1TC 0h This bit, when set, indicates that the first Uncorrectable error message received was for a Fatal error. STICKY
3 MEFNR R/W1TC 0h This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link, and the ERR_FATAL/NONFATAL Received bit is already set. STICKY
2 EFNR R/W1TC 0h This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link. STICKY
1 MECR R/W1TC 0h This bit is set when the RC receives a Correctable error message from the link, if the ERR_COR received bit is already set. STICKY
0 ECR R/W1TC 0h This bit is set when the RC receives a Correctable error message from the link. STICKY

2.5.1.318 PCIE0_I_ERR_SRC_ID Register (Offset = 134h) [reset = 0]

Short Description:

Long Description:

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Table 12-2109 Instance Table
Instance Name Base Address
PCIE0 0D00 0134h
Figure 12-1071 PCIE0_RC_I_RC_PCIE_BASE_I_ERR_SRC_ID Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFNSI
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECSI
R
0

Access Types Legend

Table 12-2110 I_ERR_SRC_ID Register Field Descriptions
Bit Field Type Reset Description
31 - 16 EFNSI R 0h This field captures and stores the Requester ID from an ERR_FATAL or ERROR_NONFATAL message received by the RC, if the ERR_FATAL or NONFATAL Received bit was not set at the time the message was received. STICKY
15 - 0 ECSI R 0h This field captures and stores the Requester ID from an ERR_COR message received by the RC, if the ERR_COR bit was not set at the time the message was received. STICKY

2.5.1.319 PCIE0_I_TLP_PRE_LOG_0 Register (Offset = 138h) [reset = 0]

Short Description:

Long Description:

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Table 12-2111 Instance Table
Instance Name Base Address
PCIE0 0D00 0138h
Figure 12-1072 PCIE0_RC_I_RC_PCIE_BASE_I_TLP_PRE_LOG_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HD1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HD1
R
0

Access Types Legend

Table 12-2112 I_TLP_PRE_LOG_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 HD1 R 0h First TLP Prefix of captured TLP STICKY.

2.5.1.320 PCIE0_I_DEV_SER_NUM_CAP_HDR Register (Offset = 150h) [reset = 805371907]

Short Description:

Long Description:

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Table 12-2113 Instance Table
Instance Name Base Address
PCIE0 0D00 0150h
Figure 12-1073 PCIE0_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_CAP_HDR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SNNCO DSNCV
R R
1100000000 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECID
R
11

Access Types Legend

Table 12-2114 I_DEV_SER_NUM_CAP_HDR Register Field Descriptions
Bit Field Type Reset Description
31 - 20 SNNCO R 300h Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19 - 16 DSNCV R 1h Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified from the local management bus by writing into Function 0 from the local management bus.
15 - 0 PECID R 3h This field is hardwired to the Capability ID assigned by PCI SIG to the PCI Express Device Serial Number Capability [0001 hex].

2.5.1.321 PCIE0_I_DEV_SER_NUM_0 Register (Offset = 154h) [reset = 0]

Short Description:

Long Description:

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Table 12-2115 Instance Table
Instance Name Base Address
PCIE0 0D00 0154h
Figure 12-1074 PCIE0_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSND0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSND0
R
0

Access Types Legend

Table 12-2116 I_DEV_SER_NUM_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DSND0 R 0h This field contains the first 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.322 PCIE0_I_DEV_SER_NUM_1 Register (Offset = 158h) [reset = 0]

Short Description:

Long Description:

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Table 12-2117 Instance Table
Instance Name Base Address
PCIE0 0D00 0158h
Figure 12-1075 PCIE0_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSND1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSND1
R
0

Access Types Legend

Table 12-2118 I_DEV_SER_NUM_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DSND1 R 0h This field contains the last 32 bits of the device's serial number. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.

2.5.1.323 PCIE0_I_SEC_PCIE_CAP_HDR_REG Register (Offset = 300h) [reset = 1275133977]

Short Description:

Long Description:

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Table 12-2119 Instance Table
Instance Name Base Address
PCIE0 0D00 0300h
Figure 12-1076 PCIE0_RC_I_RC_PCIE_BASE_I_SEC_PCIE_CAP_HDR_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCO CV
R R
10011000000 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECI
R
11001

Access Types Legend

Table 12-2120 I_SEC_PCIE_CAP_HDR_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NCO R 4C0h Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19 - 16 CV R 1h Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1 , but can be modified independently for each PF from [ the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write] .
15 - 0 PECI R 19h This field is hardwired to the Capability ID assigned by PCI SIG to the Secondary PCI Express Capability

Short Description:

Long Description:

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Table 12-2121 Instance Table
Figure 12-1077 PCIE0_RC_I_RC_PCIE_BASE_I_LINK_CONTROL3 Name Register

Access Types Legend

Table 12-2122 I_LINK_CONTROL3 Register Field Descriptions

2.5.1.325 PCIE0_I_LANE_ERROR_STATUS Register (Offset = 308h) [reset = 0]

Short Description:

Long Description:

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Table 12-2123 Instance Table
Instance Name Base Address
PCIE0 0D00 0308h
Figure 12-1078 PCIE0_RC_I_RC_PCIE_BASE_I_LANE_ERROR_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 LES
R R/W1TC
0 0

Access Types Legend

Table 12-2124 I_LANE_ERROR_STATUS Register Field Descriptions
Bit Field Type Reset Description
31 - 1 R0 R 0h N/A
0 LES R/W1TC 0h Each of these bits indicates the error status for the corresponding lane. STICKY.

2.5.1.326 PCIE0_I_LANE_EQUALIZATION_CONTROL_0 Register (Offset = 30Ch) [reset = 32639]

Short Description:

Long Description:

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Table 12-2125 Instance Table
Instance Name Base Address
PCIE0 0D00 030Ch
Figure 12-1079 PCIE0_RC_I_RC_PCIE_BASE_I_LANE_EQUALIZATION_CONTROL_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R2_11
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1 UPRPH0 UPTP0 R0_1 DNRPH0 DNTP0
R R R R R R
0 111 1111 0 111 1111

Access Types Legend

Table 12-2126 I_LANE_EQUALIZATION_CONTROL_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R2_11 R 0h Reserved
15 R1 R 0h Reserved
14 - 12 UPRPH0 R 7h 8.0GT/s Value sent by the Controller as the Receiver Preset Hint for the remote receiver associated with Lane 0. The remote node may use this value to adapt its receiver at the start of the link equalization procedure.
11 - 8 UPTP0 R Fh 8.0GT/s Value sent by the Controller as the Transmitter Preset for the remote transmitter associated with Lane 0. The remote node uses this value to set up its transmitter at the start of the link equalization procedure.
7 R0_1 R 0h Reserved
6 - 4 DNRPH0 R 7h 8.0GT/s Receiver Preset Hint value to be used for the local receiver associated with Lane 0. The Controller uses this value to set up the receiver attached to Lane 0
3 - 0 DNTP0 R Fh 8.0GT/s Transmitter Preset value to be used for the local transmitter associated with Lane 0. The Controller uses this value to set up the Lane 0 transmitter during link equalization.

2.5.1.327 PCIE0_I_VC_ENH_CAP_HEADER_REG Register (Offset = 4C0h) [reset = 2415984642]

Short Description:

Long Description:

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Table 12-2127 Instance Table
Instance Name Base Address
PCIE0 0D00 04C0h
Figure 12-1080 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_ENH_CAP_HEADER_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCO CV
R R
100100000000 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECID
R
10

Access Types Legend

Table 12-2128 I_VC_ENH_CAP_HEADER_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NCO R 900h Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19 - 16 CV R 1h Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified independently for each PF from the local management bus.
15 - 0 PECID R 2h This field is hardwired to the Capability ID assigned by PCI SIG to the VC Capability.

2.5.1.328 PCIE0_I_PORT_VC_CAP_REG_1 Register (Offset = 4C4h) [reset = 3]

Short Description:

Long Description:

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Table 12-2129 Instance Table
Instance Name Base Address
PCIE0 0D00 04C4h
Figure 12-1081 PCIE0_RC_I_VC_CAP_STRUCT_I_PORT_VC_CAP_REG_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 RESERVED EVC
R NONE R
0 11

Access Types Legend

Table 12-2130 I_PORT_VC_CAP_REG_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 4 R0 R 0h N/A
RESERVED NONE Reserved
2 - 0 EVC R 3h N/A

2.5.1.329 PCIE0_I_PORT_VC_CAP_REG_2 Register (Offset = 4C8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2131 Instance Table
Instance Name Base Address
PCIE0 0D00 04C8h
Figure 12-1082 PCIE0_RC_I_VC_CAP_STRUCT_I_PORT_VC_CAP_REG_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1
R
0

Access Types Legend

Table 12-2132 I_PORT_VC_CAP_REG_2 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 R1 R 0h N/A

2.5.1.330 PCIE0_I_PORT_VC_CTRL_STS_REG Register (Offset = 4CCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2133 Instance Table
Instance Name Base Address
PCIE0 0D00 04CCh
Figure 12-1083 PCIE0_RC_I_VC_CAP_STRUCT_I_PORT_VC_CTRL_STS_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R2
R
0

Access Types Legend

Table 12-2134 I_PORT_VC_CTRL_STS_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 R2 R 0h N/A

2.5.1.331 PCIE0_I_VC_RES_CAP_REG_0 Register (Offset = 4D0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2135 Instance Table
Instance Name Base Address
PCIE0 0D00 04D0h
Figure 12-1084 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST R1
R R
0 0

Access Types Legend

Table 12-2136 I_VC_RES_CAP_REG_0 Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R3 R 0h N/A
15 RST R 0h N/A
14 - 0 R1 R 0h N/A

2.5.1.332 PCIE0_I_VC_RES_CTRL_REG_0 Register (Offset = 4D4h) [reset = 2147483903]

Short Description:

Long Description:

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Table 12-2137 Instance Table
Instance Name Base Address
PCIE0 0D00 04D4h
Figure 12-1085 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCEN R6 VCI R5 PARS LPAT
R R R R R R
1 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TVM TVM0
NONE R/W R
1111111 1

Access Types Legend

Table 12-2138 I_VC_RES_CTRL_REG_0 Register Field Descriptions
Bit Field Type Reset Description
31 VCEN R 1h Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30 - 27 R6 R 0h N/A
26 - 24 VCI R 0h VC ID assigned to VC0. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23 - 20 R5 R 0h N/A
19 - 17 PARS R 0h Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16 LPAT R 0h Updates the port arbitration logic from the Port Arbitration Table for VC 0. This bit is not implemented, and hardwired to 0.
RESERVED NONE Reserved
7 - 1 TVM R/W 7Fh Indicates the TCs that are mapped to this VC. When bit 0 of this field is set, it indicates that TC 0 is mapped to VC 0.By default, all TCs are mapped to VC 0.
0 TVM0 R 1h Indicates the TC0 always mapped to VC0.

2.5.1.333 PCIE0_I_VC_RES_STS_REG_0 Register (Offset = 4D8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2139 Instance Table
Instance Name Base Address
PCIE0 0D00 04D8h
Figure 12-1086 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VCNP PATS
NONE R R
0 0

Access Types Legend

Table 12-2140 I_VC_RES_STS_REG_0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 VCNP R 0h This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0 PATS R 0h This is not implemented and hardwired to 0.

2.5.1.334 PCIE0_I_VC_RES_CAP_REG_1 Register (Offset = 4DCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2141 Instance Table
Instance Name Base Address
PCIE0 0D00 04DCh
Figure 12-1087 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST R1
R R
0 0

Access Types Legend

Table 12-2142 I_VC_RES_CAP_REG_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R3 R 0h N/A
15 RST R 0h N/A
14 - 0 R1 R 0h N/A

2.5.1.335 PCIE0_I_VC_RES_CTRL_REG_1 Register (Offset = 4E0h) [reset = 16777216]

Short Description:

Long Description:

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Table 12-2143 Instance Table
Instance Name Base Address
PCIE0 0D00 04E0h
Figure 12-1088 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCEN R6 VCI R5 PARS LPAT
R/W R R/W R R R
0 0 1 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TVM TVM0
NONE R/W R
0 0

Access Types Legend

Table 12-2144 I_VC_RES_CTRL_REG_1 Register Field Descriptions
Bit Field Type Reset Description
31 VCEN R/W 0h Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30 - 27 R6 R 0h N/A
26 - 24 VCI R/W 1h VC ID assigned to VC1. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23 - 20 R5 R 0h N/A
19 - 17 PARS R 0h Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16 LPAT R 0h Updates the port arbitration logic from the Port Arbitration Table for VC 1. This bit is not implemented, and hardwired to 0.
RESERVED NONE Reserved
7 - 1 TVM R/W 0h Indicates the TCs that are mapped to this VC. When bit 1 of this field is set, it indicates that TC 1 is mapped to VC 1.By default, all TCs are mapped to VC 0.
0 TVM0 R 0h Indicates the TC0 always mapped to VC0.

2.5.1.336 PCIE0_I_VC_RES_STS_REG_1 Register (Offset = 4E4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2145 Instance Table
Instance Name Base Address
PCIE0 0D00 04E4h
Figure 12-1089 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VCNP PATS
NONE R R
0 0

Access Types Legend

Table 12-2146 I_VC_RES_STS_REG_1 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 VCNP R 0h This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0 PATS R 0h This is not implemented and hardwired to 0.

2.5.1.337 PCIE0_I_VC_RES_CAP_REG_2 Register (Offset = 4E8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2147 Instance Table
Instance Name Base Address
PCIE0 0D00 04E8h
Figure 12-1090 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST R1
R R
0 0

Access Types Legend

Table 12-2148 I_VC_RES_CAP_REG_2 Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R3 R 0h N/A
15 RST R 0h N/A
14 - 0 R1 R 0h N/A

2.5.1.338 PCIE0_I_VC_RES_CTRL_REG_2 Register (Offset = 4ECh) [reset = 33554432]

Short Description:

Long Description:

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Table 12-2149 Instance Table
Instance Name Base Address
PCIE0 0D00 04ECh
Figure 12-1091 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCEN R6 VCI R5 PARS LPAT
R/W R R/W R R R
0 0 10 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TVM TVM0
NONE R/W R
0 0

Access Types Legend

Table 12-2150 I_VC_RES_CTRL_REG_2 Register Field Descriptions
Bit Field Type Reset Description
31 VCEN R/W 0h Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30 - 27 R6 R 0h N/A
26 - 24 VCI R/W 2h VC ID assigned to VC2. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23 - 20 R5 R 0h N/A
19 - 17 PARS R 0h Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16 LPAT R 0h Updates the port arbitration logic from the Port Arbitration Table for VC 2. This bit is not implemented, and hardwired to 0.
RESERVED NONE Reserved
7 - 1 TVM R/W 0h Indicates the TCs that are mapped to this VC. When bit 2 of this field is set, it indicates that TC 2 is mapped to VC 2.By default, all TCs are mapped to VC 0.
0 TVM0 R 0h Indicates the TC0 always mapped to VC0.

2.5.1.339 PCIE0_I_VC_RES_STS_REG_2 Register (Offset = 4F0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2151 Instance Table
Instance Name Base Address
PCIE0 0D00 04F0h
Figure 12-1092 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VCNP PATS
NONE R R
0 0

Access Types Legend

Table 12-2152 I_VC_RES_STS_REG_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 VCNP R 0h This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0 PATS R 0h This is not implemented and hardwired to 0.

2.5.1.340 PCIE0_I_VC_RES_CAP_REG_3 Register (Offset = 4F4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2153 Instance Table
Instance Name Base Address
PCIE0 0D00 04F4h
Figure 12-1093 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST R1
R R
0 0

Access Types Legend

Table 12-2154 I_VC_RES_CAP_REG_3 Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R3 R 0h N/A
15 RST R 0h N/A
14 - 0 R1 R 0h N/A

2.5.1.341 PCIE0_I_VC_RES_CTRL_REG_3 Register (Offset = 4F8h) [reset = 50331648]

Short Description:

Long Description:

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Table 12-2155 Instance Table
Instance Name Base Address
PCIE0 0D00 04F8h
Figure 12-1094 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VCEN R6 VCI R5 PARS LPAT
R/W R R/W R R R
0 0 11 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TVM TVM0
NONE R/W R
0 0

Access Types Legend

Table 12-2156 I_VC_RES_CTRL_REG_3 Register Field Descriptions
Bit Field Type Reset Description
31 VCEN R/W 0h Software uses this bit to enable the VC. For VC0 this bit is hardwired to 1.
30 - 27 R6 R 0h N/A
26 - 24 VCI R/W 3h VC ID assigned to VC3. For the VC0, this field is read-only and it is hardwired to 00b. For non VC0 case, it is allowed to use any VC-ID. This VC-ID has to be unique across all VCs. This must not be same as VC0's ID[VC0 ID=0].
23 - 20 R5 R 0h N/A
19 - 17 PARS R 0h Configures the VC to use a specific port arbitration scheme. This field is not implemented, and hardwired to 0.
16 LPAT R 0h Updates the port arbitration logic from the Port Arbitration Table for VC 3. This bit is not implemented, and hardwired to 0.
RESERVED NONE Reserved
7 - 1 TVM R/W 0h Indicates the TCs that are mapped to this VC. When bit 3 of this field is set, it indicates that TC 3 is mapped to VC 3.By default, all TCs are mapped to VC 0.
0 TVM0 R 0h Indicates the TC0 always mapped to VC0.

2.5.1.342 PCIE0_I_VC_RES_STS_REG_3 Register (Offset = 4FCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2157 Instance Table
Instance Name Base Address
PCIE0 0D00 04FCh
Figure 12-1095 PCIE0_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VCNP PATS
NONE R R
0 0

Access Types Legend

Table 12-2158 I_VC_RES_STS_REG_3 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 VCNP R 0h This indicates whether the Virtual Channel negotiation is in pending state. The value of this bit is defined only when the link is in the DL_Active state and Virtual Channel is enabled. When this bit is set by hardware, it indicates that the VC resource has not completed the process of negotiation. This bit is cleared by hardware after the VC negotiation is complete.
0 PATS R 0h This is not implemented and hardwired to 0.

2.5.1.343 PCIE0_I_L1_PM_EXT_CAP_HDR Register (Offset = 900h) [reset = 2717974558]

Short Description:

Long Description:

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Table 12-2159 Instance Table
Instance Name Base Address
PCIE0 0D00 0900h
Figure 12-1096 PCIE0_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_EXT_CAP_HDR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NCO CV
R R
101000100000 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECID
R
11110

Access Types Legend

Table 12-2160 I_L1_PM_EXT_CAP_HDR Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NCO R A20h Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set.
19 - 16 CV R 1h Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified from the local management bus.
15 - 0 PECID R 1Eh This field is hardwired to the Capability ID assigned by PCI SIG to the L1 PM Substates Extended Capability Structure [001E hex].

2.5.1.344 PCIE0_I_L1_PM_CAP Register (Offset = 904h) [reset = 6881055]

Short Description:

Long Description:

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Table 12-2161 Instance Table
Instance Name Base Address
PCIE0 0D00 0904h
Figure 12-1097 PCIE0_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CAP Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED R0 RESERVED L1PRTPVRONSCALE
NONE R NONE R
1101 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1PRTCMMDRESTRTIME RESERVED L1PMSUPP L1ASPML11SUPP L1ASPML12SUPP L1PML11SUPP L1PML12SUPP
R NONE R R R R R
11111111 1 1 1 1 1

Access Types Legend

Table 12-2162 I_L1_PM_CAP Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
23 - 19 R0 R Dh Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time [in us] that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. The value of Port T_POWER_ON is calculated by multiplying the value in this field by the scale value in the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register. T Power On is the minimum amount of time that each component must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. This is to ensure no device is ever actively driving into an un-powered component.
RESERVED NONE Reserved
17 - 16 L1PRTPVRONSCALE R 0h Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of Values
00b = 2 us
01b = 10 us
10b = 100 us
11b = Reserved
Default value is 00.
15 - 8 L1PRTCMMDRESTRTIME R FFh Time [in us] required for this Port to re-establish common mode during exit from PM or ASPM L1.2 substate
RESERVED NONE Reserved
4 L1PMSUPP R 1h When Set this bit indicates that this Port supports L1 PM Substates.
3 L1ASPML11SUPP R 1h When Set this bit indicates that ASPM L1.1 is supported.
2 L1ASPML12SUPP R 1h When Set this bit indicates that ASPM L1.2 is supported.
1 L1PML11SUPP R 1h When Set this bit indicates that PCI-PM L1.1 is supported.
0 L1PML12SUPP R 1h When Set this bit indicates that PCI-PM L1.2 is supported.

2.5.1.345 PCIE0_I_L1_PM_CTRL_1 Register (Offset = 908h) [reset = 0]

Short Description:

Long Description:

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Table 12-2163 Instance Table
Instance Name Base Address
PCIE0 0D00 0908h
Figure 12-1098 PCIE0_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CTRL_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L1THRSHLDSC RESERVED L1THRSHLDVAL
R/W NONE R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1CMMDRESTRTIME RESERVED L1ASPML11EN L1ASPML12EN L1PML11EN L1PML12EN
R/W NONE R/W R/W R/W R/W
0 0 0 0 0

Access Types Legend

Table 12-2164 I_L1_PM_CTRL_1 Register Field Descriptions
Bit Field Type Reset Description
31 - 29 L1THRSHLDSC R/W 0h This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.
000 - Value times 1 ns
001 - Value times 32 ns
010 - Value times 1024 ns
011 - Value times 32,768 ns
100 - Value times 1,048,576 ns
101 - Value times 33,554,422ns
110-111 - Not permitted
RESERVED NONE Reserved
25 - 16 L1THRSHLDVAL R/W 0h Along with the LTR_L1.2_THRESHOLD_Scale, this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 [if enabled] or L1.2 [if enabled].
15 - 8 L1CMMDRESTRTIME R/W 0h Sets value of TCOMMONMODE [in us], which must be used by the Downstream Port for timing the re-establishment of common mode. This field must only be modified when the ASPM L1.2 Enable and PCI-PM L1.2 Enable bits are both Clear. This field is reserved since both PCI-PM L1.2 and ASPM L1.2 are Not Supported in this configuration of the Controller.
RESERVED NONE Reserved
3 L1ASPML11EN R/W 0h When Set this bit enables ASPM L1.1.
2 L1ASPML12EN R/W 0h When Set this bit enables ASPM L1.2.
1 L1PML11EN R/W 0h When Set this bit enables PCI-PM L1.1.
0 L1PML12EN R/W 0h When Set this bit enables PCI-PM L1.2.

2.5.1.346 PCIE0_I_L1_PM_CTRL_2 Register (Offset = 90Ch) [reset = 40]

Short Description:

Long Description:

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Table 12-2165 Instance Table
Instance Name Base Address
PCIE0 0D00 090Ch
Figure 12-1099 PCIE0_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CTRL_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED L1PWRONVAL RESERVED L1PWRONSC
NONE R/W NONE R/W
101 0

Access Types Legend

Table 12-2166 I_L1_PM_CTRL_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 3 L1PWRONVAL R/W 5h Along with the T_POWER_ON Scale sets the minimum amount of time [in us] that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface. T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.
RESERVED NONE Reserved
1 - 0 L1PWRONSC R/W 0h Specifies the scale used for T_POWER_ON Value. Range of Values 00b = 2 us 01b = 10 us 10b = 100 us 11b = Reserved

2.5.1.347 PCIE0_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register (Offset = A20h) [reset = 65567]

Short Description:

Long Description:

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Table 12-2167 Instance Table
Instance Name Base Address
PCIE0 0D00 0A20h
Figure 12-1100 PCIE0_RC_I_REGF_PTM_CAP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMNXCAP PTMCAPVER
R R
0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMCAPID
R
11111

Access Types Legend

Table 12-2168 I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 20 PTMNXCAP R 0h The offset to the next PCIe Extended Capability structure.
19 - 16 PTMCAPVER R 1h This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.
15 - 0 PTMCAPID R 1Fh Indicates that the associated extended capability structure is for Precision Time Measurement capability. This field returns a Capability ID of 001Fh.

2.5.1.348 PCIE0_I_PTM_CAPABILITIES_REG Register (Offset = A24h) [reset = 1030]

Short Description:

Long Description:

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Table 12-2169 Instance Table
Instance Name Base Address
PCIE0 0D00 0A24h
Figure 12-1101 PCIE0_RC_I_REGF_PTM_CAP_I_PTM_CAPABILITIES_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R16
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCCLKGR R3 PTMRTCAP PTMRSCAP PTMRQCAP
R R R R R
100 0 1 1 0

Access Types Legend

Table 12-2170 I_PTM_CAPABILITIES_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R16 R 0h Reserved
15 - 8 LOCCLKGR R 4h In RC Mode: The Controller uses the CORE_CLK as the Local Clock for PTM. This field is used to indicate the Time Period of the CORE_CLK. If the PTM Root Select is 1, then CORE_CLK is used to provide PTM Master Time. If the PTM Root Select is 0, then CORE_CLK is used to locally track the PTM Master Time received on the PTM_LOCAL_TIMER_IN[63:0] input. By default, this field is set to 8'd4. This bit can be programmed through the local management APB interface if required.
7 - 3 R3 R 0h Reserved
2 PTMRTCAP R 1h This bit is used to indicate that the Controller implements PTM Time Source Role and is capable of serving as PTM Root. By default, this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required. Note: If this bit is programmed to 1, then the PTM Responder Capable bit must also be programmed to 1 by FW.
1 PTMRSCAP R 1h This bit is used to indicate support for PTM Responder Role. By default, this bit is set to 1 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required. Note: If the PTM Root Capable is programmed to 1, then this bit must also be programmed to 1 by FW.
0 PTMRQCAP R 0h This bit is used to indicate support for PTM Requester Role. By default, this bit is set to 0 when the Controller is in RC Mode. This bit can be programmed through the local management APB interface if required.

2.5.1.349 PCIE0_I_PTM_CONTROL_REG Register (Offset = A28h) [reset = 0]

Short Description:

Long Description:

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Table 12-2171 Instance Table
Instance Name Base Address
PCIE0 0D00 0A28h
Figure 12-1102 PCIE0_RC_I_REGF_PTM_CAP_I_PTM_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R16
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFFGRN R2 RTSEL PTMEN
R R R/W R/W
0 0 0 0

Access Types Legend

Table 12-2172 I_PTM_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R16 R 0h Reserved
15 - 8 EFFGRN R 0h This field is used only in PTM Requester Mode and is not used in RC Mode. This field is set to 00 by default in RC Mode.
7 - 2 R2 R 0h Reserved
1 RTSEL R/W 0h This field is configured by System SW. When set to 1 and when PTM Enable bit is aslo set to 1, this PTM Source is the PTM Root. Default value of this bit is 0.
0 PTMEN R/W 0h When Set, this function is permitted to participate in the PTM mechanism as PTM Requester. By default, this bit is set to 0.

2.5.1.350 PCIE0_I_PL_CONFIG_0_REG Register (Offset = 100000h) [reset = 32]

Short Description:

Long Description:

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Table 12-2173 Instance Table
Instance Name Base Address
PCIE0 0D10 0000h
Figure 12-1103 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLE R0 LTSSM RLID
R/W R R R
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFC TSS APER LTD NS NLC LS
R R/W R/W R R R R
0 0 0 1 0 0 0

Access Types Legend

Table 12-2174 I_PL_CONFIG_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 MLE R/W 0h When the Controller is operating as a Root Port, setting this to 1 causes the LTSSM to initiate a loopback and become the loopback master. This bit is not used in the EndPoint Mode.
30 R0 R 0h A 1 in this field indicates that the remote node advertised Linkwidth Upconfigure Capability in the training sequences in the Configuration.Complete state when the link came up. A 0 indicates that the remote node did not set the Link Upconfigure bit.
29 - 24 LTSSM R 0h Current state of the LTSSM. The encoding of the states is given in Appendix C.
23 - 16 RLID R 0h Link ID received from other side during link training.
15 - 8 RFC R 0h FTS count received from the other side during link training for use at the 2.5 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state, when operating at the 2.5 GT/s speed.
7 TSS R/W 0h This bit drives the PIPE_TX_SWING output of the Controller.
6 APER R/W 0h This bit controls the reporting of Errors Detected by the PHY. The Errors Detected by the PHY include:- - Received errors indicated on PIPE RxStatus interface, - 8.0 GT/s Invalid Sync Header received error, If PHY Error Reporting bit is set to 0, the Controller will only report those errors that caused a TLP or DLLP to be dropped because of a Detected PHY Error. If PHY Error Reporting bit is set to 1, the Controller will report all Detected PHY Errors regardless of whether a TLP or DLLP was dropped. The following registers report PHY error in conjunction with this bit: - Correctable Error Status Register, i_corr_err_status, bit-0, Receiver Error Status - Local Error and Status Register, i_local_error_status_register, bit-7, Phy Error In addition to the Errors Detected by the PHY[PCS], the Controller detects the following Physical Layer Protocol Framing Errors: - Framing Errors in the received DLLP and TLP - Ordered Set Block Received Without EDS - Data Block Received After EDS - Illegal Ordered Set Block Received After EDS - Ordered Set Block Received After Skip OS Note: These Errors are always reported independent of the setting of this bit.
5 LTD R 1h The state of this bit indicates whether the Controller completed link training as an upstream port[EndPoint][=0] or a downstream port[Root Port][=1]. Default value depends on CORE_TYPE strap pin.
4 - 3 NS R 0h Current operating speed of link [00 = 2.5G, 01 = 5G, 10 = 8G, 11 = 16G].
2 - 1 NLC R 0h N/A
0 LS R 0h Current state of link [1 = link training complete, 0 = link training not complete].

2.5.1.351 PCIE0_I_PL_CONFIG_1_REG Register (Offset = 100004h) [reset = 2155905024]

Short Description:

Long Description:

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Table 12-2175 Instance Table
Instance Name Base Address
PCIE0 0D10 0004h
Figure 12-1104 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFC3 TFC2
R/W R/W
10000000 10000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFC1 TLI
R/W R/W
10000000 0

Access Types Legend

Table 12-2176 I_PL_CONFIG_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 TFC3 R/W 80h FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state.
23 - 16 TFC2 R/W 80h FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state.
15 - 8 TFC1 R/W 80h FTS count transmitted by the Controller in TS1/TS2 sequences during link training. This value must be set based on the time needed by the receiver to acquire sync while exiting from L0S state.
7 - 0 TLI R/W 0h Link ID transmitted by the device in training sequences in the Root Port mode.

2.5.1.352 PCIE0_I_DLL_TMR_CONFIG_REG Register (Offset = 100008h) [reset = 0]

Short Description:

Long Description:

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Table 12-2177 Instance Table
Instance Name Base Address
PCIE0 0D10 0008h
Figure 12-1105 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DLL_TMR_CONFIG_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R25 RSART
R R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R9 TSRT
R R/W
0 0

Access Types Legend

Table 12-2178 I_DLL_TMR_CONFIG_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 25 R25 R 0h Reserved
24 - 16 RSART R/W 0h Additional receive side ACK-NAK timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal ACK-NAK timer timeout value computed by the Controller based on the PCI Express Specifications. This enables the user to make minor adjustments to the spec-defined replay timer settings.Its value is in multiples of [2 Symbol Times] At Gen1 adjustment range = [+2040 ns to -2048 ns]. At Gen2 adjustment range = [+1020 ns to -1024 ns]. At Gen3 adjustment range = [+510 ns to -512 ns].
15 - 9 R9 R 0h Reserved
8 - 0 TSRT R/W 0h Additional transmit-side replay timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal replay timer timeout value computed by the Controller based on the PCI Express Specifications. This enables the user to make minor adjustments to the spec-defined replay timer settings. Its value is in multiples of [2 Symbol Times] At Gen1 adjustment range = [+2040 ns to -2048 ns]. At Gen2 adjustment range = [+1020 ns to -1024 ns]. At Gen3 adjustment range = [+510 ns to -512 ns].

2.5.1.353 PCIE0_I_RCV_CRED_LIM_0_REG Register (Offset = 10000Ch) [reset = 33685568]

Short Description:

Long Description:

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Table 12-2179 Instance Table
Instance Name Base Address
PCIE0 0D10 000Ch
Figure 12-1106 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R/W R/W
100000 100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R/W R/W
100000 1000000

Access Types Legend

Table 12-2180 I_RCV_CRED_LIM_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R/W 20h Non-Posted payload credit limit advertised by the Controller for VC 0 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19 - 12 PHC R/W 20h Posted header credit limit advertised by the Controller for VC 0. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11 - 0 PPC R/W 40h Posted payload credit limit advertised by the Controller for VC 0. [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.354 PCIE0_I_RCV_CRED_LIM_1_REG Register (Offset = 100010h) [reset = 32]

Short Description:

Long Description:

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Table 12-2181 Instance Table
Instance Name Base Address
PCIE0 0D10 0010h
Figure 12-1107 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R2 CPC
R/W R R/W
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHCL
R/W R/W
0 100000

Access Types Legend

Table 12-2182 I_RCV_CRED_LIM_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R/W 0h Completion header credit limit advertised by the Controller for VC 0 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23 - 20 R2 R 0h Reserved
19 - 8 CPC R/W 0h Completion payload credit limit advertised by the Controller for VC 0 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7 - 0 NPHCL R/W 20h Non-Posted header credit limit advertised by the Controller for VC 0 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.355 PCIE0_I_TRANSM_CRED_LIM_0_REG Register (Offset = 100014h) [reset = 0]

Short Description:

Long Description:

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Table 12-2183 Instance Table
Instance Name Base Address
PCIE0 0D10 0014h
Figure 12-1108 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R R
0 0

Access Types Legend

Table 12-2184 I_TRANSM_CRED_LIM_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R 0h Non-Posted payload credit limit received by the Controller for Link 0 . [in units of 4 Dwords]
19 - 12 PHC R 0h Posted header credit limit received by the Controller for this link . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
11 - 0 PPC R 0h Posted payload credit limit received by the Controller for this link . [in units of 4 Dwords]

2.5.1.356 PCIE0_I_TRANSM_CRED_LIM_1_REG Register (Offset = 100018h) [reset = 0]

Short Description:

Long Description:

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Table 12-2185 Instance Table
Instance Name Base Address
PCIE0 0D10 0018h
Figure 12-1109 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R3 CPC
R R R
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHC
R R
0 0

Access Types Legend

Table 12-2186 I_TRANSM_CRED_LIM_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R 0h Completion header credit limit received by the Controller for VC 0 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
23 - 20 R3 R 0h Reserved
19 - 8 CPC R 0h Completion payload credit limit received by the Controller for VC 0 . [in units of 4 Dwords]
7 - 0 NPHC R 0h Non-Posted header credit limit received by the Controller for VC 0 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.

2.5.1.357 PCIE0_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register (Offset = 10001Ch) [reset = 262148]

Short Description:

Long Description:

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Table 12-2187 Instance Table
Instance Name Base Address
PCIE0 0D10 001Ch
Figure 12-1110 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MNUI
R/W
100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUI
R/W
100

Access Types Legend

Table 12-2188 I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 MNUI R/W 4h Minimum credit update interval for non-posted transactions. The Controller follows this minimum interval between issuing posted credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes available in the receive FIFO since the last update was sent, the Controller will issue a new update only after this interval has elapsed since the last update. The value is in units of 16 ns. This field is re-written by the internal logic when the negotiated link width or link speed changes, to correspond to the default values defined in defines.h. The user may override this default value by writing into this register field. The value written will be lost on a change in the negotiated link width/speed.
15 - 0 MPUI R/W 4h Minimum credit update interval for posted transactions. The Controller follows this minimum interval between issuing posted credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes available in the receive FIFO since the last update was sent, the Controller will issue a new update only after this interval has elapsed since the last update. The value is in units of 16 ns. This field is re-written by the internal logic when the negotiated link width or link speed changes, to correspond to the default values defined in defines.h. The user may override this default value by writing into this register field. The value written will be lost on a change in the negotiated link width/speed.

2.5.1.358 PCIE0_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register (Offset = 100020h) [reset = 61472772]

Short Description:

Long Description:

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Table 12-2189 Instance Table
Instance Name Base Address
PCIE0 0D10 0020h
Figure 12-1111 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUI
R/W
1110101010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CUI
R/W
100

Access Types Legend

Table 12-2190 I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 MUI R/W 3AAh Maximum credit update interval for all transactions. If no new credit has become available since the last update, the Controller will repeat the last update after this interval. This is to recover from any losses of credit update packets. The value is in units of 16 ns. This field could be re-written by the internal logic when the negotiated link width or link speed changes, to correspond to the default values defined in defines.h. The user may override this default value by writing into this register field. The value written will be lost on a change in the negotiated link width/speed.
15 - 0 CUI R/W 4h Minimum credit update interval for Completion packets. The Controller follows this minimum interval between issuing completion credit updates on the link. This is to limit the bandwidth use of credit updates. If new credit becomes available in the receive FIFO since the last update was sent, the Controller will issue a new update only after this interval has elapsed since the last update. The value is in units of 16 ns. This parameter is not used when the Completion credit is infinity.

2.5.1.359 PCIE0_I_L0S_TIMEOUT_LIMIT_REG Register (Offset = 100024h) [reset = 375]

Short Description:

Long Description:

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Table 12-2191 Instance Table
Instance Name Base Address
PCIE0 0D10 0024h
Figure 12-1112 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_L0S_TIMEOUT_LIMIT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R4
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
R/W
101110111

Access Types Legend

Table 12-2192 I_L0S_TIMEOUT_LIMIT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R4 R 0h Reserved
15 - 0 LT R/W 177h Contains the timeout value [in units of 16 ns] for transitioning to the L0S power state. Setting this parameter to 0 permanently disables the transition to the L0S power state.

2.5.1.360 PCIE0_I_TRANSMIT_TLP_COUNT_REG Register (Offset = 100028h) [reset = 0]

Short Description:

Long Description:

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Table 12-2193 Instance Table
Instance Name Base Address
PCIE0 0D10 0028h
Figure 12-1113 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSMIT_TLP_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTC
R/W1TC
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
R/W1TC
0

Access Types Legend

Table 12-2194 I_TRANSMIT_TLP_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TTC R/W1TC 0h Count of TLPs transmitted

2.5.1.361 PCIE0_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register (Offset = 10002Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2195 Instance Table
Instance Name Base Address
PCIE0 0D10 002Ch
Figure 12-1114 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TTPBC
R/W1TC
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTPBC
R/W1TC
0

Access Types Legend

Table 12-2196 I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TTPBC R/W1TC 0h Count of TLPs payload Dwords transmitted

2.5.1.362 PCIE0_I_RECEIVE_TLP_COUNT_REG Register (Offset = 100030h) [reset = 0]

Short Description:

Long Description:

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Table 12-2197 Instance Table
Instance Name Base Address
PCIE0 0D10 0030h
Figure 12-1115 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_TLP_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTC
R/W1TC
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC
R/W1TC
0

Access Types Legend

Table 12-2198 I_RECEIVE_TLP_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 RTC R/W1TC 0h Count of TLPs received

2.5.1.363 PCIE0_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register (Offset = 100034h) [reset = 0]

Short Description:

Long Description:

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Table 12-2199 Instance Table
Instance Name Base Address
PCIE0 0D10 0034h
Figure 12-1116 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTPDC
R/W1TC
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPDC
R/W1TC
0

Access Types Legend

Table 12-2200 I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 RTPDC R/W1TC 0h Count of TLP payload Dwords received

2.5.1.364 PCIE0_I_COMPLN_TMOUT_LIM_0_REG Register (Offset = 100038h) [reset = 12500000]

Short Description:

Long Description:

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Table 12-2201 Instance Table
Instance Name Base Address
PCIE0 0D10 0038h
Figure 12-1117 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_COMPLN_TMOUT_LIM_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R5 CTL
R R/W
0 101111101011110000100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL
R/W
101111101011110000100000

Access Types Legend

Table 12-2202 I_COMPLN_TMOUT_LIM_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 R5 R 0h Reserved
23 - 0 CTL R/W BEBC20h Timeout limit for completion timers [in 4 ns cycles]. Default value is 50 ms in 4 ns cycles. Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout.

2.5.1.365 PCIE0_I_COMPLN_TMOUT_LIM_1_REG Register (Offset = 10003Ch) [reset = 50000000]

Short Description:

Long Description:

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Table 12-2203 Instance Table
Instance Name Base Address
PCIE0 0D10 003Ch
Figure 12-1118 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_COMPLN_TMOUT_LIM_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R6 CTL
R R/W
0 10111110101111000010000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL
R/W
10111110101111000010000000

Access Types Legend

Table 12-2204 I_COMPLN_TMOUT_LIM_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 28 R6 R 0h Reserved
27 - 0 CTL R/W 2FAF080h Timeout limit for completion timers [in 4 ns cycles]. Default value is 200ms in 4ns cycles. Please note that there could be a variation of 0 to +8us on the programmed Completion Timeout.

2.5.1.366 PCIE0_I_L1_ST_REENTRY_DELAY_REG Register (Offset = 100040h) [reset = 0]

Short Description:

Long Description:

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Table 12-2205 Instance Table
Instance Name Base Address
PCIE0 0D10 0040h
Figure 12-1119 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_L1_ST_REENTRY_DELAY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L1RD
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1RD
R/W
0

Access Types Legend

Table 12-2206 I_L1_ST_REENTRY_DELAY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 L1RD R/W 0h Delay to re-enter L1 after no activity [in units of 16 ns].

2.5.1.367 PCIE0_I_VENDOR_ID_REG Register (Offset = 100044h) [reset = 399316941]

Short Description:

Long Description:

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Table 12-2207 Instance Table
Instance Name Base Address
PCIE0 0D10 0044h
Figure 12-1120 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_VENDOR_ID_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SVID
R/W
1011111001101
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VID
R/W
1011111001101

Access Types Legend

Table 12-2208 I_VENDOR_ID_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 SVID R/W 17CDh Subsystem Vendor ID
15 - 0 VID R/W 17CDh Vendor ID

2.5.1.368 PCIE0_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register (Offset = 100048h) [reset = 750]

Short Description:

Long Description:

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Table 12-2209 Instance Table
Instance Name Base Address
PCIE0 0D10 0048h
Figure 12-1121 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DISLNRXCHK R7 L1T
R/W R R/W
0 0 1011101110
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1T
R/W
1011101110

Access Types Legend

Table 12-2210 I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register Field Descriptions
Bit Field Type Reset Description
31 DISLNRXCHK R/W 0h This bit is used to configure the ASPM L1 Entry mechanism:
1: Link is checked for IDLE only on the TX to determine ASPM L1 Entry. ASPM L1 entry is initiated if no TLP is transmitted for the L1 timeout period.
0: Link is checked for IDLE both on the TX and RX to determine ASPM L1 Entry. ASPM L1 entry is initiated if no TLP is transmitted/received for the L1 timeout period.
30 - 20 R7 R 0h Reserved
19 - 0 L1T R/W 2EEh Contains the timeout value[in units of 16 ns] for transitioning to the L1 power state. Setting it to 0 permanently disables the transition to the L1 power state.

2.5.1.369 PCIE0_I_PME_TURNOFF_ACK_DELAY_REG Register (Offset = 10004Ch) [reset = 100]

Short Description:

Long Description:

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Table 12-2211 Instance Table
Instance Name Base Address
PCIE0 0D10 004Ch
Figure 12-1122 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PME_TURNOFF_ACK_DELAY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R7
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTOAD
R/W
1100100

Access Types Legend

Table 12-2212 I_PME_TURNOFF_ACK_DELAY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R7 R 0h Reserved
15 - 0 PTOAD R/W 64h Time in microseconds between the Controller receiving a PME_TurnOff message TLP and the Controller sending a PME_TO_Ack response to it. This field must be set to a non-zero value in order for the Controller to send a response. Setting this field to 0 suppresses the Controller's response to PME_TurnOff message, so that the client may transmit the PME_TO_Ack message through the master interface.

2.5.1.370 PCIE0_I_LINKWIDTH_CONTROL_REG Register (Offset = 100050h) [reset = 0]

Short Description:

Long Description:

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Table 12-2213 Instance Table
Instance Name Base Address
PCIE0 0D10 0050h
Figure 12-1123 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LINKWIDTH_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPLSCRL R2 EPTLS R20 DSAG4SC DSAG3SC DSAG2SC R1
R/W R R/W R R/W R/W R/W R
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1
R
0

Access Types Legend

Table 12-2214 I_LINKWIDTH_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 EPLSCRL R/W 0h Writing a 1 into this field results in the Controller re-training the link to change its speed. When setting this bit to 1, the software must also set the EP Target Link Speed field to indicate the speed that the EP desires to change on the link. The EP Controller will attempt to change the link to this speed. This bit is cleared by the internal logic of the Controller after the re-training has been completed and link has reached the L0 state. Software must wait for the bit to be clear before setting it again to change the link speed.
30 - 26 R2 R 0h Reserved
25 - 24 EPTLS R/W 0h This field contains the Link Speed that the EP intends to change to during the re-training. Client needs to ensure that this field is programmed to a speed which is lesser than or equal to the Target Link Speed field of PF0 Configuration Link Control 2 Register. Client also needs to ensure that this does not exceed PCIE_GENERATION_SEL strap input. Defined encodings of this field are: 00 - GEN1 01 - GEN2 10 - GEN3 11 - Reserved
23 - 20 R20 R 0h Reserved
19 DSAG4SC R/W 0h This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen4 capability and if Gen3 speed change, equalization was successful, the Controller [RP] autonomously initiates Gen3 to Gen4 speed change, equalization. If Gen4 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen3 L0. Software can re-initiate Gen4 speed change. Autonomous Speed Change to Gen4 can be disabled by programming this bit to 1. Note: If Disable Auto Gen3 Speed Change is disabled, then Auto Gen4 Speed Change must also be disabled by setting this bit to 1.
18 DSAG3SC R/W 0h This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen3 capability, the Controller [RP] autonomously initiates Gen1 to Gen3 speed change, equalization. If Gen3 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen1 L0. Software can re-initiate Gen3 speed change. Autonomous Speed Change to Gen3 can be disabled by programming this bit to 1.
17 DSAG2SC R/W 0h This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen2 capability and if Gen2 is the highest common supported speed the Controller [RP] autonomously initiates Gen1 to Gen2 speed change. If Gen2 autonomous speed change was unsuccessful, then the Link transitions back to Gen1 L0. Software can re-initiate Gen2 speed change. Autonomous Speed Change to Gen2 can be disabled by programming this bit to 1.
16 - 0 R1 R 0h Reserved

2.5.1.371 PCIE0_I_PL_CONFIG_2_REG Register (Offset = 100054h) [reset = 1]

Short Description:

Long Description:

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Table 12-2215 Instance Table
Instance Name Base Address
PCIE0 0D10 0054h
Figure 12-1124 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R3 DQMDC LK_TRN
R R/W R/W
0 0 1

Access Types Legend

Table 12-2216 I_PL_CONFIG_2_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 3 R3 R 0h Reserved
2 - 1 DQMDC R/W 0h As per PCIe specification, All Receivers must meet the Z-RX-DC specification for 2.5 GT/s within 1ms of entering Detect.Quiet LTSSM substate. The LTSSM must stay in this substate until the ZRX-DC specification for 2.5 GT/s is met. This register field can be used to program the minimum time that LTSSM waits on entering Detect.Quiet state. 00 : 0us minimum wait time in Detect.Quiet state. 01 : 100us minimum wait time in Detect.Quiet state. 10 : 1ms minimum wait time in Detect.Quiet state. 11 : 2ms minimum wait time in Detect.Quiet state.
0 LK_TRN R/W 1h This bit is AND'ed with the input LINK_TRAINING_ENABLE strap to enable Link Training.

2.5.1.372 PCIE0_I_MULTI_VC_CONROL_REG Register (Offset = 100070h) [reset = 2]

Short Description:

Long Description:

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Table 12-2217 Instance Table
Instance Name Base Address
PCIE0 0D10 0070h
Figure 12-1125 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_MULTI_VC_CONROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31 RES4 RES2 WAIT_4_ALL_VC_CC_RDY DMAAM
R R R R/W R
0 0 0 1 0

Access Types Legend

Table 12-2218 I_MULTI_VC_CONROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 5 R31 R 0h Reserved
4 RES4 R 0h Reserved
3 - 2 RES2 R 0h Reserved
1 WAIT_4_ALL_VC_CC_RDY R/W 1h When this bit is set, the controller waits for credits to be available to be able to send atleast 1 max payload TLP in all enabled VCs. When this bit is not set, the controller waits for credits to be available to be able to send atleast 1 max payload TLP in any of the enabled VCs [PCI-SIG recommended].
0 DMAAM R 0h Reserved

2.5.1.373 PCIE0_I_SRIS_CONTROL_REG Register (Offset = 100074h) [reset = 0]

Short Description:

Long Description:

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Table 12-2219 Instance Table
Instance Name Base Address
PCIE0 0D10 0074h
Figure 12-1126 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SRIS_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31 SRISE
R R/W
0 0

Access Types Legend

Table 12-2220 I_SRIS_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 1 R31 R 0h Reserved
0 SRISE R/W 0h Setting this bit enables SRIS mode in the PHY layer. This bit should be changed before link training begins by holding the LINK_TRAINING_ENABLE input to 1'b0. When SRIS is disabled using this bit the Lower SKP OS Generation Supported Speeds Vector and Lower SKP OS Reception Supported Speeds Vector in the Link Capabilities Register 2 will be forced to ZERO. The default value of this register can be controlled using the SRIS_ENABLE strap input.

2.5.1.374 PCIE0_I_RCV_CRED_LIM_0_REG_VC1 Register (Offset = 100080h) [reset = 33685568]

Short Description:

Long Description:

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Table 12-2221 Instance Table
Instance Name Base Address
PCIE0 0D10 0080h
Figure 12-1127 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R/W R/W
100000 100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R/W R/W
100000 1000000

Access Types Legend

Table 12-2222 I_RCV_CRED_LIM_0_REG_VC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R/W 20h Non-Posted payload credit limit advertised by the Controller for VC 1 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19 - 12 PHC R/W 20h Posted header credit limit advertised by the Controller for VC 1. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11 - 0 PPC R/W 40h Posted payload credit limit advertised by the Controller for VC 1. [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.375 PCIE0_I_RCV_CRED_LIM_1_REG_VC1 Register (Offset = 100084h) [reset = 32]

Short Description:

Long Description:

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Table 12-2223 Instance Table
Instance Name Base Address
PCIE0 0D10 0084h
Figure 12-1128 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R2 CPC
R/W R R/W
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHCL
R/W R/W
0 100000

Access Types Legend

Table 12-2224 I_RCV_CRED_LIM_1_REG_VC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R/W 0h Completion header credit limit advertised by the Controller for VC 1 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23 - 20 R2 R 0h Reserved
19 - 8 CPC R/W 0h Completion payload credit limit advertised by the Controller for VC 1 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7 - 0 NPHCL R/W 20h Non-Posted header credit limit advertised by the Controller for VC 1 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.376 PCIE0_I_TRANSM_CRED_LIM_0_REG_VC1 Register (Offset = 100088h) [reset = 0]

Short Description:

Long Description:

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Table 12-2225 Instance Table
Instance Name Base Address
PCIE0 0D10 0088h
Figure 12-1129 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R R
0 0

Access Types Legend

Table 12-2226 I_TRANSM_CRED_LIM_0_REG_VC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R 0h Non-Posted payload credit limit received by the Controller for Link 0 . [in units of 4 Dwords]
19 - 12 PHC R 0h Posted header credit limit received by the Controller for this link . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
11 - 0 PPC R 0h Posted payload credit limit received by the Controller for this link . [in units of 4 Dwords]

2.5.1.377 PCIE0_I_TRANSM_CRED_LIM_1_REG_VC1 Register (Offset = 10008Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2227 Instance Table
Instance Name Base Address
PCIE0 0D10 008Ch
Figure 12-1130 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R3 CPC
R R R
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHC
R R
0 0

Access Types Legend

Table 12-2228 I_TRANSM_CRED_LIM_1_REG_VC1 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R 0h Completion header credit limit received by the Controller for VC 1 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
23 - 20 R3 R 0h Reserved
19 - 8 CPC R 0h Completion payload credit limit received by the Controller for VC 1 . [in units of 4 Dwords]
7 - 0 NPHC R 0h Non-Posted header credit limit received by the Controller for VC 1 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.

2.5.1.378 PCIE0_I_RCV_CRED_LIM_0_REG_VC2 Register (Offset = 100090h) [reset = 33685568]

Short Description:

Long Description:

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Table 12-2229 Instance Table
Instance Name Base Address
PCIE0 0D10 0090h
Figure 12-1131 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R/W R/W
100000 100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R/W R/W
100000 1000000

Access Types Legend

Table 12-2230 I_RCV_CRED_LIM_0_REG_VC2 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R/W 20h Non-Posted payload credit limit advertised by the Controller for VC 2 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19 - 12 PHC R/W 20h Posted header credit limit advertised by the Controller for VC 2. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11 - 0 PPC R/W 40h Posted payload credit limit advertised by the Controller for VC 2. [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.379 PCIE0_I_RCV_CRED_LIM_1_REG_VC2 Register (Offset = 100094h) [reset = 32]

Short Description:

Long Description:

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Table 12-2231 Instance Table
Instance Name Base Address
PCIE0 0D10 0094h
Figure 12-1132 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R2 CPC
R/W R R/W
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHCL
R/W R/W
0 100000

Access Types Legend

Table 12-2232 I_RCV_CRED_LIM_1_REG_VC2 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R/W 0h Completion header credit limit advertised by the Controller for VC 2 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23 - 20 R2 R 0h Reserved
19 - 8 CPC R/W 0h Completion payload credit limit advertised by the Controller for VC 2 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7 - 0 NPHCL R/W 20h Non-Posted header credit limit advertised by the Controller for VC 2 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.380 PCIE0_I_TRANSM_CRED_LIM_0_REG_VC2 Register (Offset = 100098h) [reset = 0]

Short Description:

Long Description:

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Table 12-2233 Instance Table
Instance Name Base Address
PCIE0 0D10 0098h
Figure 12-1133 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R R
0 0

Access Types Legend

Table 12-2234 I_TRANSM_CRED_LIM_0_REG_VC2 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R 0h Non-Posted payload credit limit received by the Controller for Link 0 . [in units of 4 Dwords]
19 - 12 PHC R 0h Posted header credit limit received by the Controller for this link . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
11 - 0 PPC R 0h Posted payload credit limit received by the Controller for this link . [in units of 4 Dwords]

2.5.1.381 PCIE0_I_TRANSM_CRED_LIM_1_REG_VC2 Register (Offset = 10009Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2235 Instance Table
Instance Name Base Address
PCIE0 0D10 009Ch
Figure 12-1134 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R3 CPC
R R R
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHC
R R
0 0

Access Types Legend

Table 12-2236 I_TRANSM_CRED_LIM_1_REG_VC2 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R 0h Completion header credit limit received by the Controller for VC 2 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
23 - 20 R3 R 0h Reserved
19 - 8 CPC R 0h Completion payload credit limit received by the Controller for VC 2 . [in units of 4 Dwords]
7 - 0 NPHC R 0h Non-Posted header credit limit received by the Controller for VC 2 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.

2.5.1.382 PCIE0_I_RCV_CRED_LIM_0_REG_VC3 Register (Offset = 1000A0h) [reset = 33685568]

Short Description:

Long Description:

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Table 12-2237 Instance Table
Instance Name Base Address
PCIE0 0D10 00A0h
Figure 12-1135 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R/W R/W
100000 100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R/W R/W
100000 1000000

Access Types Legend

Table 12-2238 I_RCV_CRED_LIM_0_REG_VC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R/W 20h Non-Posted payload credit limit advertised by the Controller for VC 3 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
19 - 12 PHC R/W 20h Posted header credit limit advertised by the Controller for VC 3. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
11 - 0 PPC R/W 40h Posted payload credit limit advertised by the Controller for VC 3. [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.383 PCIE0_I_RCV_CRED_LIM_1_REG_VC3 Register (Offset = 1000A4h) [reset = 32]

Short Description:

Long Description:

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Table 12-2239 Instance Table
Instance Name Base Address
PCIE0 0D10 00A4h
Figure 12-1136 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R2 CPC
R/W R R/W
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHCL
R/W R/W
0 100000

Access Types Legend

Table 12-2240 I_RCV_CRED_LIM_1_REG_VC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R/W 0h Completion header credit limit advertised by the Controller for VC 3 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
23 - 20 R2 R 0h Reserved
19 - 8 CPC R/W 0h Completion payload credit limit advertised by the Controller for VC 3 . [in units of 4 Dwords] Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.
7 - 0 NPHCL R/W 20h Non-Posted header credit limit advertised by the Controller for VC 3 [in number of packets]. [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP. Caution: The programmed Header and Payload credit values must not exceed the actual size of the Receive Buffer.

2.5.1.384 PCIE0_I_TRANSM_CRED_LIM_0_REG_VC3 Register (Offset = 1000A8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2241 Instance Table
Instance Name Base Address
PCIE0 0D10 00A8h
Figure 12-1137 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPPC PHC
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHC PPC
R R
0 0

Access Types Legend

Table 12-2242 I_TRANSM_CRED_LIM_0_REG_VC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 20 NPPC R 0h Non-Posted payload credit limit received by the Controller for Link 0 . [in units of 4 Dwords]
19 - 12 PHC R 0h Posted header credit limit received by the Controller for this link . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
11 - 0 PPC R 0h Posted payload credit limit received by the Controller for this link . [in units of 4 Dwords]

2.5.1.385 PCIE0_I_TRANSM_CRED_LIM_1_REG_VC3 Register (Offset = 1000ACh) [reset = 0]

Short Description:

Long Description:

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Table 12-2243 Instance Table
Instance Name Base Address
PCIE0 0D10 00ACh
Figure 12-1138 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC3 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHC R3 CPC
R R R
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPC NPHC
R R
0 0

Access Types Legend

Table 12-2244 I_TRANSM_CRED_LIM_1_REG_VC3 Register Field Descriptions
Bit Field Type Reset Description
31 - 24 CHC R 0h Completion header credit limit received by the Controller for VC 3 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.
23 - 20 R3 R 0h Reserved
19 - 8 CPC R 0h Completion payload credit limit received by the Controller for VC 3 . [in units of 4 Dwords]
7 - 0 NPHC R 0h Non-Posted header credit limit received by the Controller for VC 3 . [in units of 1 Packet Header] Note: Packet Header represents one maximum-size TLP Header + TLP Digest + maximum number of End-End TLP Prefixes permitted in a TLP.

2.5.1.386 PCIE0_I_FC_INIT_DELAY_REG Register (Offset = 1000F0h) [reset = 50]

Short Description:

Long Description:

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Table 12-2245 Instance Table
Instance Name Base Address
PCIE0 0D10 00F0h
Figure 12-1139 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_FC_INIT_DELAY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R4
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCINITDLY
R/W
110010

Access Types Legend

Table 12-2246 I_FC_INIT_DELAY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R4 R 0h Reserved
15 - 0 FCINITDLY R/W 32h Delay between successive sets of P, NP, CPL FC_INIT DLLP transmissions for VCx.

2.5.1.387 PCIE0_I_SHDW_HDR_LOG_0_REG Register (Offset = 100100h) [reset = 0]

Short Description:

Long Description:

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Table 12-2247 Instance Table
Instance Name Base Address
PCIE0 0D10 0100h
Figure 12-1140 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHDW_HDR_LOG_0
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHDW_HDR_LOG_0
R/W
0

Access Types Legend

Table 12-2248 I_SHDW_HDR_LOG_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 SHDW_HDR_LOG_0 R/W 0h The value here will be reflected in the target function's header log register when f/w sets any bit in the shadow error register. If the header log is already set in the function's AER space, the value here may not get written and a header log overflow bit would get set. This register holds [31:0] value of the TLP header.

2.5.1.388 PCIE0_I_SHDW_HDR_LOG_1_REG Register (Offset = 100104h) [reset = 0]

Short Description:

Long Description:

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Table 12-2249 Instance Table
Instance Name Base Address
PCIE0 0D10 0104h
Figure 12-1141 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHDW_HDR_LOG_1
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHDW_HDR_LOG_1
R/W
0

Access Types Legend

Table 12-2250 I_SHDW_HDR_LOG_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 SHDW_HDR_LOG_1 R/W 0h The value here will be reflected in the target function's header log register when f/w sets any bit in the shadow error register. If the header log is already set in the function's AER space, the value here may not get written and a header log overflow bit would get set. This register holds [63:32] value of the TLP header.

2.5.1.389 PCIE0_I_SHDW_HDR_LOG_2_REG Register (Offset = 100108h) [reset = 0]

Short Description:

Long Description:

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Table 12-2251 Instance Table
Instance Name Base Address
PCIE0 0D10 0108h
Figure 12-1142 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHDW_HDR_LOG_2
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHDW_HDR_LOG_2
R/W
0

Access Types Legend

Table 12-2252 I_SHDW_HDR_LOG_2_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 SHDW_HDR_LOG_2 R/W 0h The value here will be reflected in the target function's header log register when f/w sets any bit in the shadow error register. If the header log is already set in the function's AER space, the value here may not get written and a header log overflow bit would get set. This register holds [95:64] value of the TLP header.

2.5.1.390 PCIE0_I_SHDW_HDR_LOG_3_REG Register (Offset = 10010Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2253 Instance Table
Instance Name Base Address
PCIE0 0D10 010Ch
Figure 12-1143 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_3_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHDW_HDR_LOG_3
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHDW_HDR_LOG_3
R/W
0

Access Types Legend

Table 12-2254 I_SHDW_HDR_LOG_3_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 SHDW_HDR_LOG_3 R/W 0h The value here will be reflected in the target function's header log register when f/w sets any bit in the shadow error register. If the header log is already set in the function's AER space, the value here may not get written and a header log overflow bit would get set. This register holds [127:96] value of the TLP header.

2.5.1.391 PCIE0_I_SHDW_FUNC_NUM_REG Register (Offset = 100110h) [reset = 0]

Short Description:

Long Description:

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Table 12-2255 Instance Table
Instance Name Base Address
PCIE0 0D10 0110h
Figure 12-1144 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_FUNC_NUM_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 SHDW_FUNC_NUM
R R/W
0 0

Access Types Legend

Table 12-2256 I_SHDW_FUNC_NUM_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 8 R0 R 0h Reserved
7 - 0 SHDW_FUNC_NUM R/W 0h The value here will be the target function number when f/w sets any bit in the shadow error register.

2.5.1.392 PCIE0_I_SHDW_UR_ERR_REG Register (Offset = 100114h) [reset = 0]

Short Description:

Long Description:

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Table 12-2257 Instance Table
Instance Name Base Address
PCIE0 0D10 0114h
Figure 12-1145 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_SHDW_UR_ERR_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 NP_UR_ERR P_UR_ERR
R W W
0 0 0

Access Types Legend

Table 12-2258 I_SHDW_UR_ERR_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 2 R0 R 0h Reserved
1 NP_UR_ERR W 0h If this bit is set, the corresponding non-posted UR error bits will be set in the AER and device status registers of the target function.
0 P_UR_ERR W 0h If this bit is set, the corresponding posted UR error bits will be set in the AER and device status registers of the target function.

2.5.1.393 PCIE0_I_PM_CLK_FREQUENCY_REG Register (Offset = 100140h) [reset = 25]

Short Description:

Long Description:

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Table 12-2259 Instance Table
Instance Name Base Address
PCIE0 0D10 0140h
Figure 12-1146 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PM_CLK_FREQUENCY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 PMCLKFRQ
R R/W
0 11001

Access Types Legend

Table 12-2260 I_PM_CLK_FREQUENCY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 8 R0 R 0h Reserved
7 - 0 PMCLKFRQ R/W 19h This field specifies the PM_CLK Frequency selected. The encoding is described below:
000000: Reserved
000001: Reserved
000010: PM_CLK is 2 MHz
000011: PM_CLK is 3 MHz
000100: PM_CLK is 4 MHz
000101: PM_CLK is 5 MHz
..
111010: PM_CLK is 58 MHz
111011: PM_CLK is 59 MHz
111100: PM_CLK is 60 MHz
111101 : Reserved
111110 : Reserved
111111 : Reserved .

2.5.1.394 PCIE0_I_DEBUG_DLLP_COUNT_GEN1_REG Register (Offset = 100144h) [reset = 0]

Short Description:

Long Description:

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Table 12-2261 Instance Table
Instance Name Base Address
PCIE0 0D10 0144h
Figure 12-1147 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLPCNT1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLLPCNT1
R
0

Access Types Legend

Table 12-2262 I_DEBUG_DLLP_COUNT_GEN1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DLLPCNT1 R 0h Reflects the total number of DLLPs received by the Controller at GEN1 speed.

2.5.1.395 PCIE0_I_DEBUG_DLLP_COUNT_GEN2_REG Register (Offset = 100148h) [reset = 0]

Short Description:

Long Description:

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Table 12-2263 Instance Table
Instance Name Base Address
PCIE0 0D10 0148h
Figure 12-1148 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLPCNT2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLLPCNT2
R
0

Access Types Legend

Table 12-2264 I_DEBUG_DLLP_COUNT_GEN2_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DLLPCNT2 R 0h Reflects the total number of DLLPs received by the Controller at GEN2 speed.

2.5.1.396 PCIE0_I_DEBUG_DLLP_COUNT_GEN3_REG Register (Offset = 10014Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2265 Instance Table
Instance Name Base Address
PCIE0 0D10 014Ch
Figure 12-1149 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN3_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLPCNT3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLLPCNT3
R
0

Access Types Legend

Table 12-2266 I_DEBUG_DLLP_COUNT_GEN3_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 DLLPCNT3 R 0h Reflects the total number of DLLPs received by the Controller at GEN3 speed.

2.5.1.397 PCIE0_I_VENDOR_DEFINED_MESSAGE_TAG_REG Register (Offset = 100158h) [reset = 0]

Short Description:

Long Description:

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Table 12-2267 Instance Table
Instance Name Base Address
PCIE0 0D10 0158h
Figure 12-1150 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_VENDOR_DEFINED_MESSAGE_TAG_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VDMTAG
NONE R/W
0

Access Types Legend

Table 12-2268 I_VENDOR_DEFINED_MESSAGE_TAG_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 VDMTAG R/W 0h The Controller will use the tag programed in this register for all Outbound Vendor Defined Messages.

2.5.1.398 PCIE0_I_NEGOTIATED_LANE_MAP_REG Register (Offset = 100200h) [reset = 1]

Short Description:

Long Description:

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Table 12-2269 Instance Table
Instance Name Base Address
PCIE0 0D10 0200h
Figure 12-1151 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_NEGOTIATED_LANE_MAP_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R71 LRS
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R70 NLM
R R
0 1

Access Types Legend

Table 12-2270 I_NEGOTIATED_LANE_MAP_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 17 R71 R 0h Reserved
16 LRS R 0h This bit set by the Controller at the end of link training if the LTSSM had to reverse the lane numbers to form the link.
15 - 1 R70 R 0h Reserved
0 NLM R 1h Bit i of this field is set to 1 at the end of link training if Lane i is part of the PCIe link. The value of this field is valid only when the link is in L0 or L0s states.

2.5.1.399 PCIE0_I_RECEIVE_FTS_COUNT_REG Register (Offset = 100204h) [reset = 0]

Short Description:

Long Description:

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Table 12-2271 Instance Table
Instance Name Base Address
PCIE0 0D10 0204h
Figure 12-1152 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_FTS_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R24 R16
R R
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFC8S RFC5S
R R
0 0

Access Types Legend

Table 12-2272 I_RECEIVE_FTS_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 R24 R 0h Reserved
23 - 16 R16 R 0h Reserved
15 - 8 RFC8S R 0h FTS count received from the other side during link training for use at the 8 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state, when operating at the 8 GT/s speed.
7 - 0 RFC5S R 0h FTS count received from the other side during link training for use at the 5 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state, when operating at the 5 GT/s speed.

2.5.1.400 PCIE0_I_DEBUG_MUX_CONTROL_REG Register (Offset = 100208h) [reset = 2147483648]

Short Description:

Long Description:

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Table 12-2273 Instance Table
Instance Name Base Address
PCIE0 0D10 0208h
Figure 12-1153 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFSRTCA DOC DFCUT DEI DGLUS IEDPPE ESPC EFLT DLUC DLRFE DSHEC DCIVMC DIOAEFC DOASFC HPRSUPP AWRPRI
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDS DSSPLM R1313 R1212 R1111 DRXNPSP MSIVCMS DIDBOC R77 R6 MS
R/W R/W R R R/W R/W R/W R/W R/W R R/W
0 0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2274 I_DEBUG_MUX_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 EFSRTCA R/W 1h Setting this bit to 0 causes all the enabled Functions to report an error when a Type-1 configuration access is received by the Controller, targeted at any Function. Setting it to 1 limits the error reporting to the type-0 Function whose number matches with the Function number specified in the request. If the Function number in the request refers to an unimplemented or disabled Function, all enabled Functions report the error regardless of the setting of this bit.
30 DOC R/W 0h Setting this bit to 1 disables the ordering check in the Controller between Completions and Posted requests received from the link.
29 DFCUT R/W 0h When this bit is 0, the Controller will time out and re-train the link when no Flow Control Update DLLPs are received from the link within an interval of 128 us. Setting this bit to 1 disables this timeout. When the advertised receive credit of the link partner is infinity for the header and payload of all credit types, this timeout is always suppressed. The setting of this bit has no effect in this case. This bit should not be set during normal operation, but is useful for testing.
28 DEI R/W 0h Setting this bit to 1 disables the inferring of electrical idle in the L0 state. Electrical idle is inferred when no flow control updates and no SKP sequences are received within an interval of 128 us. This bit should not be set during normal operation, but is useful for testing.
27 DGLUS R/W 0h Setting this bit to 1 disables the update of the LFSRs in the Gen3 descramblers of the Controller, from the values received in SKP sequences. This bit should not be set during normal operation, but is useful for testing.
26 IEDPPE R/W 0h When set to 1, this bit inverts the Parity bits generated by the Controller for end-to-end data protection. This will result in the inversion of Parity bits for data payloads delivered through the HAL Target Interface request descriptor. This bit is to be used for diagnostics only, and should not be set during normal operation.
25 ESPC R/W 0h When this bit is set to 1, the Controller will capture the Slot Power Limit Value and Slot Power Limit Scale parameters from a Set_Slot_Power_Limit message received in the Device Capabilities Register. When this bit is 0, the capture is disabled. This bit is valid only when the Controller is configured as an EndPoint. It has no effect when the Controller is a Root Complex.
24 EFLT R/W 0h This bit is provided to shorten the link training time to facilitate fast simulation of the design, especially at the gate level. Enabling this bit has the following effects: 1. The 1 ms, 2 ms, 12 ms, 24 ms, 32 ms and 48 ms timeout intervals in the LTSSM are shortened by a factor of 500. 2. In the Polling.Active state of the LTSSM, only 16 training sequences are required to be transmitted [Instead of 1024] to make the transition to the Configuration state. This bit should not be set during normal operation of the Controller.
23 DLUC R/W 0h The user may set this bit to turn off the link upconfigure capability of the Controller. Setting this bit prevents the Controller from advertising the link upconfigure capability in training sequences transmitted in the Configuration.Complete state. In addition, setting this bit causes the Controller to put the unused lanes into Turn Off mode. When disable_link_upconfigure_capability == 1: Controller drives PIPE_TX_ELEC_IDLE == 1 AND PIPE_TX_COMPLIANCE == 1 for the Unused upper lanes. The Unused upper lanes are put into Turn Off mode by the PHY as per PIPE specification. When disable_link_upconfigure_capability == 0: Controller drives PIPE_TX_ELEC_IDLE == 1 AND PIPE_TX_COMPLIANCE == 0 for the Unused upper lanes. The Unused upper lanes are put into Electrical Idle by the PHY.
22 DLRFE R/W 0h When this bit is 1, the Controller will not transition its LTSSM into the Recovery state when it detects a Framing Error at 8 GT/s speed [as defined in Section 4.2.2.3.3 of the PCIe Base Specification 3.0. This bit must normally be set to 0 so that a Framing Error will cause the LTSSM to enter Recovery. The setting of this bit has no effect on the operation of the Controller at 2.5 and 5 GT/s speeds.
21 DSHEC R/W 0h When this bit is 0, the Controller will signal a framing error if it detects a sync header error in the received blocks at 8 GT/s speed [A 00 or 11 binary setting of the sync header on the received blocks in any lane constitutes a framing error]. Setting this bit to 1 suppresses this error check. This bit should normally be set to 0, as the sync header check is mandatory in the PCIe 3.0 Specifications.
20 DCIVMC R/W 0h When this bit is 1, the Controller will not check for invalid message codes. This bit should normally set to 0, as the invalid message code checking is mandatory in the PCIe 3.0 specifications.
19 DIOAEFC R/W 0h When this bit is 1, the Controller will not check for illegal OS after EDS as part of Gen3 Framing Error Checks. This bit should normally set to 0, as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications.
18 DOASFC R/W 0h When this bit is 1, the Controller will not check for OS after SKIP OS as part of Gen3 Framing Error Checks. This bit should normally set to 0, as this is a mandatory Gen3 Framing Error check in the PCIe 3.0 specifications.
17 HPRSUPP R/W 0h When this bit is 1, data path Parity check is disabled on the TX side of the Controller.
16 AWRPRI R/W 0h When this bit is 1, the AXI bridge places a write request on the HAL Master interface in preference over a read request if both AXI write and AXI read requests are available to be asserted on the same clock cycle.
15 FDS R/W 0h Disable Scrambling/Descrambling in Gen1/Gen2.
14 DSSPLM R/W 0h Disable sending Set Slot Power Limit Message if the Slot Capabilitied register is configured
13 R1313 R 0h N/A
12 R1212 R 0h N/A
11 R1111 R/W 0h When this bit is 1, Disable Client TX MUX Completion and PNP request arbitartion,roundrobin priority logic added to prevent PNP requests from starving when completions are present
10 DRXNPSP R/W 0h As per PCIe specification, Non Posted packets should not pass ahead of a Posted packet. Posted and Non Posted packets are stored in a common Receive PNP FIFO. Controller ensures that the P and NP are delivered to the HAL/AXI target interface without violating the Ordering rules. When a mix of P and NP requests are received over the link, the NP packets can be starved if multiple Posted packets are stored in the PNP RX FIFO. Controller implements a mechanism to prevent NP Starvation Prevention which can be programmed through this bit: 0: Send P and NP in the received order, instead of giving priority only for P and starve NP when continuous P, NP packets are received. 1: Priority only for P. Starve NP when continuous P, NP packets are received. NP packets sent to HAL/AXI target interface only when all P packets in the PNP FIFO are delivered.
9 MSIVCMS R/W 0h Sets the mode of generating MSI_VECTOR_COUNT output for all functions. 0 - MSI_VECTOR_COUNT always outputs the configured value of MSI Multiple Message Enable[2:0] register. 1 - MSI_VECTOR_COUNT outputs the lesser of the MSI Multiple Message Enable[2:0] and MSI Multiple Message Capable[2:0] This mode can be used to handle any programming error form the Host software.
8 DIDBOC R/W 0h Setting this bit to 1 disables the ID Based Ordering check in the Controller between Completions and Posted requests received from the link.
7 R77 R/W 0h This bit should be set to 0 for backward compatibility.
6 - 5 R6 R 0h N/A
4 - 0 MS R/W 0h Bits 4:3 select the module and bits 2:0 select the group of signals within the module that are driven on the debug bus. The assignments of signals on the debug outputs of the Controller are given in Appendix B.

2.5.1.401 PCIE0_I_LOCAL_ERROR_STATUS_REGISTER Register (Offset = 10020Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2275 Instance Table
Instance Name Base Address
PCIE0 0D10 020Ch
Figure 12-1154 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_ERROR_STATUS_REGISTER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REORDER_ER_UN AXISLAVE_WFIFO_ER_UN AXIMASTER_RFIFO_ER_UN AXIMASTER_DIB_ER_UN R27 MSIXMSKST R24 R23_1 HAWCD R22 MMVC UTC EEPE R13
R/W1TC R/W1TC R/W1TC R/W1TC R R/W1TC R R R/W1TC R R/W1TC R/W1TC R/W1TC R
0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R13 R12 CT FCE UCR MTR PE RTR RT CRFO PRFO RRPE CRFPE PRFPE
R R R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2276 I_LOCAL_ERROR_STATUS_REGISTER Register Field Descriptions
Bit Field Type Reset Description
31 REORDER_ER_UN R/W1TC 0h This indicates an uncorrectable axi slave reorder ram Parity/ECC error
30 AXISLAVE_WFIFO_ER_UN R/W1TC 0h This indicates an uncorrectable axi slave write FIFO ram Parity/ECC error
29 AXIMASTER_RFIFO_ER_UN R/W1TC 0h This indicates an uncorrectable axi master write FIFO ram Parity/ECC error
28 AXIMASTER_DIB_ER_UN R/W1TC 0h This indicates an uncorrectable axi slave write FIFO ram Parity/ECC error
27 - 26 R27 R 0h Reserved
25 MSIXMSKST R/W1TC 0h This status bit indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW.
24 - 23 R24 R 0h Reserved
22 R23_1 R 0h Reserved
21 HAWCD R/W1TC 0h This interrupt status bit indicates that the Host toggled the Hardware Autonomous Width Change bit in the Link Control Register through a Config Write. Upon this interrupt, the Client firmware must read the Link Control Register to check the value set by Host in the Hardware Autonomous Width Change bit. The Host Software may disable autonomous width change by setting Hardware Autonomous Width Disable bit in the Link Control register. If disabled by the Host and if the Endpoint firmware had initiated an autonomous width downsizing prior to this interrupt, then the local Client firmware is responsible to upconfigure the Link to go to its full functional width by initiating the link_upconfigure_retrain_link within 1 ms of this interrupt.
20 R22 R 0h Reserved
19 MMVC R/W1TC 0h This status bit is set whenever the MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller
18 UTC R/W1TC 0h Unmapped TC error.
17 EEPE R/W1TC 0h The Controller detected an End to End Parity Error
16 - 13 R13 R 0h Reserved
12 R12 R 0h Reserved
11 CT R/W1TC 0h A request timed out waiting for completion.
10 FCE R/W1TC 0h An error was observed in the flow control advertisements from the other side.
9 UCR R/W1TC 0h Unexpected Completion received from the link.
8 MTR R/W1TC 0h Malformed TLP received from the link.
7 PE R/W1TC 0h Phy error detected on receive side. This bit is set when an error is detected in the receive side of the Physical Layer of the Controller [e.g. a bit error or coding violation]. This bit is set upon any of the following errors: [1] PHY reported 8B10B error, Disparity Error, Elastic Buffer Overflow Error, Underflow Error [2] GEN3 TLP, DLLP Framing Errors [3] OS Block Received Without EDS [4] Data Block Received After EDS [5] Illegal OS Block After EDS [6] OS Block Received After SKIP OS [7] OS Block Received After SDS [8] Sync Header Error [9] Loss of Gen3 Block Alignment This error is not Function-specific..
6 RTR R/W1TC 0h Replay timer rolled over after 4 transmissions of the same TLP.
5 RT R/W1TC 0h Replay timer timed out
4 CRFO R/W1TC 0h Overflow occurred in the Completion Receive FIFO.
3 PRFO R/W1TC 0h Overflow occurred in the PNP Receive FIFO.
2 RRPE R/W1TC 0h Parity error detected while reading from Replay Buffer RAM.
1 CRFPE R/W1TC 0h Parity error detected while reading from the Completion Receive FIFO RAM.
0 PRFPE R/W1TC 0h Parity error detected while reading from the PNP Receive FIFO RAM.

2.5.1.402 PCIE0_I_LOCAL_INTRPT_MASK_REG Register (Offset = 100210h) [reset = 36573183]

Short Description:

Long Description:

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Table 12-2277 Instance Table
Instance Name Base Address
PCIE0 0D10 0210h
Figure 12-1155 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_INTRPT_MASK_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REORDER_ER_UN AXISLAVE_WFIFO_ER_UN AXIMASTER_RFIFO_ER_UN AXIMASTER_DIB_ER_UN R27 MSIXMSK R24 R23_1 HAWCD R45 MMVC UTC EEPE R13
R/W R/W R/W R/W R R/W R R R/W R R/W R/W R/W R
0 0 0 0 0 1 0 0 1 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R13 R12 CT FCE UCR MTR PE RTR RT CRFO PRFO RRPE CRFPE PRFPE
R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 1 1 1 1 1 1 1 1 1 1 1 1

Access Types Legend

Table 12-2278 I_LOCAL_INTRPT_MASK_REG Register Field Descriptions
Bit Field Type Reset Description
31 REORDER_ER_UN R/W 0h Mask for uncorrectable axi slave reorder ram Parity/ECC error
30 AXISLAVE_WFIFO_ER_UN R/W 0h Mask for uncorrectable axi slave write FIFO ram Parity/ECC error
29 AXIMASTER_RFIFO_ER_UN R/W 0h Mask for uncorrectable axi master write FIFO ram Parity/ECC error
28 AXIMASTER_DIB_ER_UN R/W 0h Mask for uncorrectable axi slave write FIFO ram Parity/ECC error
27 - 26 R27 R 0h Reserved
25 MSIXMSK R/W 1h This bit is used to mask interrupt that indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW.
24 - 23 R24 R 0h Reserved
22 R23_1 R 0h Reserved
21 HAWCD R/W 1h This bit is used to mask interrupt that indicates that the Host toggled the Hardware Autonomous Width Change in the Endpoint Link Control Register through a Config Write.
20 R45 R 0h Reserved
19 MMVC R/W 1h MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller
18 UTC R/W 1h Unmapped TC error
17 EEPE R/W 1h The Controller detected an End to End Parity Error
16 - 13 R13 R 0h Reserved
12 R12 R 0h Reserved
11 CT R/W 1h A request timed out waiting for completion.
10 FCE R/W 1h An error was observed in the flow control advertisements from the other side.
9 UCR R/W 1h Unexpected Completion received from the link.
8 MTR R/W 1h Malformed TLP received from the link.
7 PE R/W 1h Phy error detected on receive side.
6 RTR R/W 1h Replay timer rolled over after 4 transmissions of the same TLP.
5 RT R/W 1h Replay timer timed out
4 CRFO R/W 1h Overflow occurred in the Completion Receive FIFO.
3 PRFO R/W 1h Overflow occurred in the PNP Receive FIFO.
2 RRPE R/W 1h Parity error detected while reading from Replay Buffer RAM.
1 CRFPE R/W 1h Parity error detected while reading from the Completion Receive FIFO RAM.
0 PRFPE R/W 1h Parity error detected while reading from the PNP Receive FIFO RAM.

2.5.1.403 PCIE0_I_LCRC_ERR_COUNT_REG Register (Offset = 100214h) [reset = 0]

Short Description:

Long Description:

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Table 12-2279 Instance Table
Instance Name Base Address
PCIE0 0D10 0214h
Figure 12-1156 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LCRC_ERR_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R11
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
R/W1TC
0

Access Types Legend

Table 12-2280 I_LCRC_ERR_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R11 R 0h Reserved
15 - 0 LEC R/W1TC 0h Number of TLPs received with LCRC errors.

2.5.1.404 PCIE0_I_ECC_CORR_ERR_COUNT_REG Register (Offset = 100218h) [reset = 0]

Short Description:

Long Description:

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Table 12-2281 Instance Table
Instance Name Base Address
PCIE0 0D10 0218h
Figure 12-1157 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_ECC_CORR_ERR_COUNT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31_2 RRCER
R R/W1TC
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFRCER PFRCER
R/W1TC R/W1TC
0 0

Access Types Legend

Table 12-2282 I_ECC_CORR_ERR_COUNT_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 R31_2 R 0h Reserved
23 - 16 RRCER R/W1TC 0h Number of correctable errors detected while reading from the Replay Buffer RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.
15 - 8 SFRCER R/W1TC 0h Number of correctable errors detected while reading from the SC FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.
7 - 0 PFRCER R/W1TC 0h Number of correctable errors detected while reading from the PNP FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.

2.5.1.405 PCIE0_I_LTR_SNOOP_LAT_REG Register (Offset = 10021Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2283 Instance Table
Instance Name Base Address
PCIE0 0D10 021Ch
Figure 12-1158 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LTR_SNOOP_LAT_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SL R13 SLS SLV
R/W R R/W R/W
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSLR R12 NSLS NSLV
R/W R R/W R/W
0 0 0 0

Access Types Legend

Table 12-2284 I_LTR_SNOOP_LAT_REG Register Field Descriptions
Bit Field Type Reset Description
31 SL R/W 0h The client software must set this bit to 1 to set the Snoop Latency Requirement bit in the LTR message to be sent.
30 - 29 R13 R 0h Reserved
28 - 26 SLS R/W 0h The client software must program this field with the value to be sent in the Snoop Latency Scale field of the LTR message.
25 - 16 SLV R/W 0h The client software must program this field with the value to be sent in the Snoop Latency Value field of the LTR message.
15 NSLR R/W 0h The client software must set this bit to 1 to set the No-Snoop Latency Requirement bit in the LTR message to be sent.
14 - 13 R12 R 0h N/A
12 - 10 NSLS R/W 0h The client software must program this field with the value to be sent in the No-Snoop Latency Scale field of the LTR message.
9 - 0 NSLV R/W 0h The client software must program this field with the value to be sent in the No-Snoop Latency Value field of the LTR message.

2.5.1.406 PCIE0_I_LTR_MSG_GEN_CTL_REG Register (Offset = 100220h) [reset = 6394]

Short Description:

Long Description:

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Table 12-2285 Instance Table
Instance Name Base Address
PCIE0 0D10 0220h
Figure 12-1159 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LTR_MSG_GEN_CTL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TMFPSC TMLMET SLM MLI
NONE R/W R/W R R/W
1 1 0 11111010

Access Types Legend

Table 12-2286 I_LTR_MSG_GEN_CTL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
12 TMFPSC R/W 1h When this bit is set to 1, the Controller will automatically transmit an LTR message when all the Functions in the Controller have transitioned to a non-D0 power state, provided that the following conditions are both true: 1. The Controller sent at least one LTR message since the Data Link layer last transitioned from down to up state. 2. The most recent LTR message transmitted by the Controller had as least one of the Requirement bits set. The Controller will set the Requirement bits in this LTR message to 0. When this bit 12 is 0, the Controller will not, by itself, send any LTR messages in response to Function Power State changes. Client logic may monitor the FUNCTION_POWER_STATE outputs of the Controller and transmit LTR messages through the master interface, in response to changes in their states.
11 TMLMET R/W 1h When this bit is set to 1, the Controller will automatically transmit an LTR message whenever the LTR Mechanism Enable bit in the Device Control 2 Register changes from 0 to 1, with the parameters specified in the LTR Snoop/No-Snoop Latency Register. When this bit is 1, the Controller will also transmit an LTR message whenever the LTR Mechanism Enable bit is cleared, if the following conditions are both true: 1. The Controller sent at least one LTR message since the LTR Mechanism Enable bit was last set. 2. The most recent LTR message transmitted by the Controller had as least one of the Requirement bits set. The Controller will set the Requirement bits in this LTR message to 0. When this bit 11 is 0, the Controller will not, by itself, send any LTR messages in response to state changes of the LTR Mechanism Enable bit. Client logic may monitor the state of the LTR_MECHANISM_ ENABLE output of the Controller and transmit LTR messages through the master interface, in response to its state changes.
10 SLM R 0h Setting this bit causes the Controller to transmit an LTR message with the parameters specified in the LTR Snoop/No-Snoop Latency Register [Section 8.4.2.9]. This bit is cleared by the Controller on transmitting the LTR message, and stays set until then. Client software must read this register and verify that this bit is 0 before setting it again to send a new message. This field becomes writable when LTR mechanism is enabled in device control-2 register.
9 - 0 MLI R/W FAh This field specifies the minimum spacing between LTR messages transmitted by the Controller in units of microseconds. The PCI Express Specifications recommend sending no more than two LTR messages within a 500 microsecond interval. The Controller will wait for the minimum delay specified by this field after sending an LTR message, before transmitting a new LTR message. NOTE: The LINK can be in low power states[L0s and L1] when send LTR Message is triggered. So, the user has to consider the exit latencies while programming this field. It is recommended to program this field with about 2 us higher than the required interval to account for the L0s/L1 exit latencies.

2.5.1.407 PCIE0_I_PME_SERVICE_TIMEOUT_DELAY_REG Register (Offset = 100224h) [reset = 100000]

Short Description:

Long Description:

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Table 12-2287 Instance Table
Instance Name Base Address
PCIE0 0D10 0224h
Figure 12-1160 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PME_SERVICE_TIMEOUT_DELAY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R21 DPMOPS PSTD
R R/W R/W
0 0 11000011010100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSTD
R/W
11000011010100000

Access Types Legend

Table 12-2288 I_PME_SERVICE_TIMEOUT_DELAY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 21 R21 R 0h Reserved
20 DPMOPS R/W 0h When this bit is set, Controller will not automatically send a PME message, when PM Status bit in PMCSR register is set
19 - 0 PSTD R/W 186A0h Specifies the timeout delay for retransmission of PM_PME messages. The value is in units of microseconds. The actual time elapsed has a +1 microseconds tolerance from The value programmed.

2.5.1.408 PCIE0_I_ROOT_PORT_REQUESTOR_ID_REG Register (Offset = 100228h) [reset = 0]

Short Description:

Long Description:

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Table 12-2289 Instance Table
Instance Name Base Address
PCIE0 0D10 0228h
Figure 12-1161 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_ROOT_PORT_REQUESTOR_ID_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPRI
R/W
0

Access Types Legend

Table 12-2290 I_ROOT_PORT_REQUESTOR_ID_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R0 R 0h Reserved
15 - 0 RPRI R/W 0h RID [bus, device and function numbers] for all TLPs internally generated by Root Port

2.5.1.409 PCIE0_I_EP_BUS_DEVICE_NUMBER_REG Register (Offset = 10022Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2291 Instance Table
Instance Name Base Address
PCIE0 0D10 022Ch
Figure 12-1162 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_EP_BUS_DEVICE_NUMBER_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R16
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPBN R5 EPDN
R R R
0 0 0

Access Types Legend

Table 12-2292 I_EP_BUS_DEVICE_NUMBER_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R16 R 0h Reserved
15 - 8 EPBN R 0h Bus Number captured by Function 0 in End Point mode
7 - 5 R5 R 0h Reserved
4 - 0 EPDN R 0h Device Number captured by Function 0 in End Point mode

2.5.1.410 PCIE0_I_DEBUG_MUX_CONTROL_2_REG Register (Offset = 100234h) [reset = 268503104]

Short Description:

Long Description:

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Table 12-2293 Instance Table
Instance Name Base Address
PCIE0 0D10 0234h
Figure 12-1163 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HRLT R30 DRXRMFR DFLRTRB DTAE2EP R26 R25 R24 VARCCLKEN MAXNPREQ
R/W R R/W R/W R/W R R R R/W R/W
0 0 0 1 0 0 0 0 0 1000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXNPREQ AXINPSPEN_RSVD CMPTOADV PSNADV MSIPIMS R8 BLKALNWIN BLKALNCHK R4 ENLNCHK DISSDSCHK EXTSNP DLFFS
R/W R R/W R/W R/W R R/W R/W R R/W R/W R/W R/W
1000 0 1 0 0 0 1 0 0 0 0 0 0

Access Types Legend

Table 12-2294 I_DEBUG_MUX_CONTROL_2_REG Register Field Descriptions
Bit Field Type Reset Description
31 HRLT R/W 0h If set this bit makes the HOT_RESET_OUT signal behave as a level signal rather than a pulse. When set , the HOT_RESET_OUT will be asserted as long as the controller is in the HOT Reset state.
30 R30 R 0h Reserved
29 DRXRMFR R/W 0h By default, when an Uncorrectable error is detected on a receive FIFO RAM, then no packets are read out of the RAM subsequent to the error and the RAMs are frozen. 0 : Receive FIFO RAMs are frozen after an uncorrectable error. 1 : Receive FIFO RAMs continue to read subsequent packets after an uncorrectable error.
28 DFLRTRB R/W 1h 1 : NP Termination due to FLR/Completion Timeout is delayed till the RX Completion FIFO is Empty. 0 : NP Termination due to FLR is done immediately on receiving FLR/Completion Timeout.
27 DTAE2EP R/W 0h By default, when End to End Parity error is detected on inbound/outbound data streams, then all the transmitted outbound packets will be Nullified by the Controller. This bit can be used to turn off nullifying Tx packets on End to End Parity Error.
26 R26 R 0h Reserved
25 R25 R 0h Reserved
24 R24 R 0h Reserved
23 VARCCLKEN R/W 0h If this bit is set the CORE_CLK input can be driven with Variable Clock depending on the Link Speed,similar to the PIPE_PCLK.
22 - 13 MAXNPREQ R/W 8h The Controller supports 8 outstanding NP requests that can be initiated by the User. However, the number of split completion TLPs that can be stored in the Controller is limited to 128. The Completion FIFO will overflow if more than 128 split completion packets are pending. If the User interface can accept inbound Posted and Completion packets at the same rate as received from PCIe link, then the split completion FIFO will never reach the FULL condition. However, if the User cannot guarantee this, then this register needs to be programmed as described in the Programming Guide section of the Controller User guide. The Controller will limit the maximum number of outstanding NP requests to The value programmed in this register. Example: 8 : Controller will limit maximum number of outstanding NP requests to 8. 0-7 : Reserved Default Value is 8
12 AXINPSPEN_RSVD R 0h RESERVED
11 CMPTOADV R/W 1h As per PCIe specification on Error Signaling, the Requester detecting a Completion Timeout is allowed to handle this as an Advisory Non Fatal Error. 1: Completion Timeout is handled as Advisory Non-Fatal Error. 0: Completion Timeout is handled as normally as a Non-Fatal Error.
10 PSNADV R/W 0h As per PCIe specification 2.7.2.2, the following Poisoned TLP requests must be handled as Uncorrectable and not as Advisory: I/O Write Request, Memory Write Request, or non-vendor-defined Message with data that target a Control structure. Since it is not possible for the Controller to determine if the target is a Control or a non-Control strusture, the Controller implements this bit for the user to determine the required handling. 1: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Advisory Non-Fatal Error. 0: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Uncorrectable Error. Note: Poisoned CplD will always be reported as Advisory Non-Fatal and is not controlled by this register setting.
9 MSIPIMS R/W 0h If the Client wishes to use the MSI_PENDING_STATUS_IN Signal to Update the MSI pending Bits register, this bit needs to be set to 1. Otherwise the Pending Bits register is updated via the APB Interface
8 R8 R 0h Reserved
7 - 6 BLKALNWIN R/W 1h When in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY. If the block alignment is lost, then the PHY may deassert pipe_rx_valid. Controller reports loss of block alignment if pipe_rx_valid or pipe_rx_data_valid=0 for a period consecutive clock cycles as programmed in this field. 00: 8 CORE_CLK cycles 01: 16 CORE_CLK cycles 10: 64 CORE_CLK cycles 11: 256 CORE_CLK cycles
5 BLKALNCHK R/W 0h When in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY. If the block alignment is lost, then the PHY may deassert pipe_rx_valid. Block Alignment may be lost if the received sync header is invalid. Controller supports detecting loss of block alignment while in a data stream in Gen3. 0: Enable check for loss of Gen3 Block Alignment during data stream. 1: Disable check for loss of Gen3 Block Alignment.
4 R4 R 0h Reserved
3 ENLNCHK R/W 0h As per PCIe specification, LTSSM should transition to Disabled after any Lanes that are transmitting TS1 Ordered Sets receive two consecutive TS1 Ordered Sets with the Disable Link bit asserted. Similarly, LTSSM should transition to Loopback after all Lanes that are transmitting TS1 Ordered Sets, that are also receiving TS1 Ordered Sets, receive the Loopback bit asserted in two consecutive TS1 Ordered Sets. Controller ignores the Link and Lane Number in the Received TS1s with Loopback/Disable bit set. Setting this bit to 1 turns on the check for link number [assigned by RC in Recovery.Idle] and lane number [PAD in Config.LW.Start or as assigned by RC in Recovery.Idle]. This bit is recommended to be kept at the default value of 0.
2 DISSDSCHK R/W 0h As per PCIe specification, When using 128b/130b encoding, next state is L0 if eight consecutive Symbol Times of Idle data are received on all configured Lanes. The Controller checks to ensure that the Idle symbols of data are received in Data Blocks after SDS OS. This check is enabled by default. Setting this bit to 1 turns off this check. This bit is recommended to be kept at the default value of 0.
1 EXTSNP R/W 0h This bit can be set if an extra clock cycle is required by the Client Application logic to respond with the Read Data on Configuration Snoop Interface. Please refer to the user guide section on Configuration Snoop Interface for timing diagrams.
0 DLFFS R/W 0h As per PIPE 4.2 specification, the LOCALLF, LOCALFS outputs from PHY can be sampled uponf PHYSTATUS pulse after Reset# OR upon the first PHYSTATUS pulse after speed change to GEN3. This bit can be set to 1 to disable sampling after speed change to GEN3 or higher

2.5.1.411 PCIE0_I_PHY_STATUS_1_REG Register (Offset = 100238h) [reset = 0]

Short Description:

Long Description:

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Table 12-2295 Instance Table
Instance Name Base Address
PCIE0 0D10 0238h
Figure 12-1164 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PHY_STATUS_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31 LOSBLKALN INVSYNHR OSAFSDS G3FRERR OSWOEDS DATEDS ILOSEDS OSASKP TLPPHYER
R R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC
0 0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2296 I_PHY_STATUS_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 9 R31 R 0h Reserved
8 LOSBLKALN R/W1TC 0h This bit is set if the PHY Loses Block Alignment during data stream. This is detected based upon an unexpected PIPE_RX_VALID input de-assertion during data stream. Write a 1 to clear this error.
7 INVSYNHR R/W1TC 0h This bit is set if an invalid Sync Header is detected. 00 and 11 are Invalid Sync Headers. Write a 1 to clear this error. .
6 OSAFSDS R/W1TC 0h This bit is set if an SDS is received after an SDS. This is a framing error. Write a 1 to clear this error.
5 G3FRERR R/W1TC 0h This bit is set if a framing error is detected while receiving a TLP in Gen3. Example, if an invalid token is received in a data stream, this error is flagged. Write a 1 to clear this error.
4 OSWOEDS R/W1TC 0h This bit is set if an Ordered Set Block is received without an EDS. This is a framing error. Write a 1 to clear this error.
3 DATEDS R/W1TC 0h This bit is set if a Data Block is received after an EDS. Write a 1 to clear this error.
2 ILOSEDS R/W1TC 0h The Valid OS blocks after an EDS are EIOS, EIEOS and SKP. If any other OS blocks are received after EDS, then it is a framing error and this bit is asserted.
1 OSASKP R/W1TC 0h This bit indicates that an Ordered Set Block was received immediately after a SKIP OS. This is a framing error. Write a 1 to clear this field.
0 TLPPHYER R/W1TC 0h This bit indicates that a PHY Error was detected on the PIPE_RX_STATUS within a TLP. Write a 1 to clear this field.

2.5.1.412 PCIE0_I_DEBUG_MUX_CONTROL_3_REG Register (Offset = 10023Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2297 Instance Table
Instance Name Base Address
PCIE0 0D10 023Ch
Figure 12-1165 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_3_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R2 R4 DSDES DLTE R1 R0
R R R/W R/W R R
0 0 0 0 0 0

Access Types Legend

Table 12-2298 I_DEBUG_MUX_CONTROL_3_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 5 R2 R 0h Reserved
4 R4 R 0h Reserved
3 DSDES R/W 0h Used to disable and enable Surprise Down Error status logging and by default it is enabled
2 DLTE R/W 0h Used to disable and enable link training error logging and by default it is enabled
1 R1 R 0h Reserved
0 R0 R 0h Reserved

2.5.1.413 PCIE0_I_RC_BAR_CONFIG_REG Register (Offset = 100300h) [reset = 10516]

Short Description:

Long Description:

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Table 12-2299 Instance Table
Instance Name Base Address
PCIE0 0D10 0300h
Figure 12-1166 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RC_BAR_CONFIG_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCBCE R10 RCBARPIS RCBARPIE RCBARPMS RCBARPME RCBAR1C
R/W R R/W R/W R/W R/W R/W
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCBAR1C RCBAR1A RCBAR0C RCBAR0A
R/W R/W R/W R/W
0 10100 100 10100

Access Types Legend

Table 12-2300 I_RC_BAR_CONFIG_REG Register Field Descriptions
Bit Field Type Reset Description
31 RCBCE R/W 0h This bit must be set to 1 to enable BAR checking in the RC mode. When this bit is set to 0, the Controller will forward all incoming memory requests to the client logic without checking their address ranges.
30 - 21 R10 R 0h Reserved
20 RCBARPIS R/W 0h Width of IO Base and Limit registers in type1 config space.
0 = 32 bits,
1 = 64bits
19 RCBARPIE R/W 0h Enable for IO Base and Limit registers in type1 config space
18 RCBARPMS R/W 0h Width of Prefetchable Memory Base and Limit registers in type1 config space. 0=32 bits, 1=64bits
17 RCBARPME R/W 0h Enable for Prefetchable memory base and limit registers in type1 config space
16 - 14 RCBAR1C R/W 0h Specifies the configuration of RC BAR1. The various encodings are:
000: Disabled
001: 32bit IO BAR
010-011: Reserved
100: 32bit memory BAR, non prefetchable
101: 32bit memory BAR, prefetchable 110-111: Reserved
13 - 9 RCBAR1A R/W 14h This field specifies the aperture of the RC BAR 1. The encodings are:
0000 = 4,
00001 =8B,
.....
1_1101 = 2G
8 - 6 RCBAR0C R/W 4h Specifies the configuration of RC BAR0. The various encodings are:
000: Disabled
001: 32bit IO BAR 010-011: Reserved
100: 32bit memory BAR, non prefetchable
101: 32bit memory BAR, prefetchable
110: 64bit memory BAR, non prefetchable
111: 64bit memory BAR, prefetchable
5 - 0 RCBAR0A R/W 14h This field specifies the aperture of the RC BAR 0. The encodings are:
0000 = 4,
00001 =8B,
.....
01_1111 = 8G, .
...
10_0100 = 256G.

2.5.1.414 PCIE0_I_GEN3_DEFAULT_PRESET_REG Register (Offset = 100360h) [reset = 524032]

Short Description:

Long Description:

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Table 12-2301 Instance Table
Instance Name Base Address
PCIE0 0D10 0360h
Figure 12-1167 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_GEN3_DEFAULT_PRESET_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31 S8GPR
R R/W
0 11111111111
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S8GPR R7 GDRXPH GDTXP
R/W R R/W R/W
11111111111 0 0 0

Access Types Legend

Table 12-2302 I_GEN3_DEFAULT_PRESET_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 19 R31 R 0h Reserved
18 - 8 S8GPR R/W 7FFh This register can be used to program the Presets that are supported by local Transmitter at 8Gbps. Default value of this register is determined by the SUPPORTED_PRESET strap input. Note: At 8.0 GT/s and 16.0 GT/s all preset values must be supported for Full swing signaling. Reduced swing signaling must implement presets #4, #1, #9, #5, #6, and #3.
7 R7 R 0h Reserved
6 - 4 GDRXPH R/W 0h Default receiver preset hint value used for a lane that did not receive EQ TS2 in Recovery.RcvrCfg LTSSM state
3 - 0 GDTXP R/W 0h Default transmitter preset value used for a lane that did not receive EQ TS2 in Recovery.RcvrCfg LTSSM state

Short Description:

Long Description:

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Table 12-2303 Instance Table
Figure 12-1168 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_TIMEOUT_2MS_REG Name Register

Access Types Legend

Table 12-2304 I_GEN3_LINK_EQ_TIMEOUT_2MS_REG Register Field Descriptions

2.5.1.416 PCIE0_I_PIPE_FIFO_LATENCY_CTRL_REG Register (Offset = 100368h) [reset = 32768]

Short Description:

Long Description:

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Table 12-2305 Instance Table
Instance Name Base Address
PCIE0 0D10 0368h
Figure 12-1169 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PIPE_FIFO_LATENCY_CTRL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPTFWF R14 DPRFLR DPTFCE
R/W R R/W R/W
1 0 0 0

Access Types Legend

Table 12-2306 I_PIPE_FIFO_LATENCY_CTRL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 R31 R 0h Reserved
15 DPTFWF R/W 1h This bit can be used to prevent PIPE_TX_FIFO from reaching full during TX Electrical Idle. 0: During TX Electrical Idle, the PIPE_TX_FIFO is kept at half fill level by filtering the writes into the PIPE_TX_FIFO. 1: The PIPE_TX_FIFO write filtering logic is turned off. Default value of this bit is 1.
14 - 2 R14 R 0h Reserved
1 DPRFLR R/W 0h 0: If FIFO empty is reached, the PIPE RX FIFO accumulates 2 entries before reading the FIFO again. 1: If FIFO empty is reached, the PIPE RX FIFO accumulates 6 entries before reading the FIFO again. This is to prevent FIFO from reaching empty again. Default value of this bit is 0, in order to reduce the latency through the PIPE RX FIFO.
0 DPTFCE R/W 0h By default, if FIFO empty is reached, the PIPE TX FIFO accumulates 2 entries before reading the FIFO again. This is to prevent FIFO from reaching empty again. This bit must remain at 0 to allow the PIPE TX FIFO to recover effectively from a Empty condition.

Short Description:

Long Description:

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Table 12-2307 Instance Table
Figure 12-1170 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_CTRL_REG Name Register

Access Types Legend

Table 12-2308 I_GEN3_LINK_EQ_CTRL_REG Register Field Descriptions

Short Description:

Long Description:

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Table 12-2309 Instance Table
Figure 12-1171 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Name Register

Access Types Legend

Table 12-2310 I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register Field Descriptions

2.5.1.419 PCIE0_I_ECC_CORR_ERR_COUNT_REG_AXI Register (Offset = 100C80h) [reset = 0]

Short Description:

Long Description:

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Table 12-2311 Instance Table
Instance Name Base Address
PCIE0 0D10 0C80h
Figure 12-1172 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_ECC_CORR_ERR_COUNT_REG_AXI Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXI_MASTER_DIB_CER AXI_MASTER_RFIFO_CER
R/W1TC R/W1TC
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXI_SLAVE_WFIFO_CER REORDER_CER
R/W1TC R/W1TC
0 0

Access Types Legend

Table 12-2312 I_ECC_CORR_ERR_COUNT_REG_AXI Register Field Descriptions
Bit Field Type Reset Description
31 - 24 AXI_MASTER_DIB_CER R/W1TC 0h Number of correctable errors detected while reading from the AXI Master Read Data interleave RAM. This is an 8-bit saturating counter that can be cleared by writing all 1s into it.
23 - 16 AXI_MASTER_RFIFO_CER R/W1TC 0h Number of correctable errors detected while reading from the AXI master read FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.
15 - 8 AXI_SLAVE_WFIFO_CER R/W1TC 0h Number of correctable errors detected while reading from the AXI slave write FIFO RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.
7 - 0 REORDER_CER R/W1TC 0h Number of correctable errors detected while reading from the AXI slave reorder RAM. This is an 8-bit saturating counter that can be cleared by writing all 1's into it.

2.5.1.420 PCIE0_LOW_POWER_DEBUG_AND_CONTROL0 Register (Offset = 100C88h) [reset = 0]

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Long Description:

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Table 12-2313 Instance Table
Instance Name Base Address
PCIE0 0D10 0C88h
Figure 12-1173 PCIE0_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED L1DLEUP L1EM L1DBRI L1XDELAY
NONE R/W R R/W R/W
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1XDELAY
R/W
0

Access Types Legend

Table 12-2314 LOW_POWER_DEBUG_AND_CONTROL0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
27 L1DLEUP R/W 0h Pending Tlps trigger a L1 exit by default. This includes internally generated messages and internally blocked TLPs. Setting this bit changes the default behavior. This is required only for debug purpose.
26 - 25 L1EM R 0h This field shows the last entered L1 mode. This is useful for debug. bit 0 - Entry mode was ASPM. Bit 1 - Entry mode was PM. This is reset before any new L1 entry.
24 L1DBRI R/W 0h Before entering L1, controller internally blocks all TLP and Register Request interface entering controller. interfaces are internally unblocked while exiting L1. This field control this behavior. '1' in this field makes the controller to do not perform any blocking to interfaces. '0' makes the controller behaves normally. This is required only for debug purpose. Power shutoff feature has to be disabled while using this field.
23 - 0 L1XDELAY R/W 0h Normally L1 substate entry process is initiated immediately after LTSSM enters L1. A delay in micro-seconds can be given in this field to delay L1 substate entry process. This timeout has 0-1us margin of error. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_L1_SUBSTATE_ENTRY_DELAY

2.5.1.421 PCIE0_LOW_POWER_DEBUG_AND_CONTROL1 Register (Offset = 100C8Ch) [reset = 0]

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Long Description:

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Table 12-2315 Instance Table
Instance Name Base Address
PCIE0 0D10 0C8Ch
Figure 12-1174 PCIE0_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED L1ER
NONE R
0

Access Types Legend

Table 12-2316 LOW_POWER_DEBUG_AND_CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 L1ER R 0h This field shows the values of possible L1 or L1-substate exit triggers. This is useful for debug. this is captured during L1 or L1-substate exit process. this field is reset during L1 entry. 0 : CLIENT_REQ_EXIT_L1 asserted; 1 : Electrical Idle exit detected at link; 2 : New TLP request detected; 3 : Internal request to send TLP. This includes CFG completions. internal messages. INTx messages; 4 : Pending TX traffic available. This could be traffic from DMA and blocked traffic due to credits at AXI.; 5 : #CLKREQ assert detected; 6 : CLIENT_REQ_EXIT_L1_SUBSTATE asserted 7 : Reg Access request detected; Triggers #5,6,7 are valid only with L1-substate supported configs.

2.5.1.422 PCIE0_LOW_POWER_DEBUG_AND_CONTROL2 Register (Offset = 100C90h) [reset = 2818572288]

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Long Description:

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Table 12-2317 Instance Table
Instance Name Base Address
PCIE0 0D10 0C90h
Figure 12-1175 PCIE0_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L1UPACR L1CSC L1DAET L1TROW L1PS L1ERC L1EOC RESERVED L1TWROI
R/W R/W R/W R R/W R/W R/W NONE R/W
1 0 1 0 1 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L1TWROI
R/W
0

Access Types Legend

Table 12-2318 LOW_POWER_DEBUG_AND_CONTROL2 Register Field Descriptions
Bit Field Type Reset Description
31 L1UPACR R/W 1h Setting this field make the state machine to consider LP_CTRL_POWER_RECOVER_ACK as Client system recovery Complete ACK instead of the Controller power stable ACK. This field is ignored if LP_CTRL_BYPASS_ENABLE unset. If this field is set, L1-substate machines expect that the client system finishes power up of the controller within power_on time in the L1-substate capability register and Controller will be waiting in recovery state for ACK. This ensure that the PHY PLL lock and client system initialization goes on in parallel. Default value of this register can be set with the define:den_db_LP_DBG_CTRL_RECOVER_ACK_AS_CLIENT_RECOVER_ACK. Setting this field gives the best system performance.
30 L1CSC R/W 0h L1-substate removes CORE_CLK. since the registers are implemented in core-clk, register access is not possible during L1-substate. If client can supply a slow clock to core[CORE_CLK] during L1-substates, APB/mgmt access is possible in L1.x. set this bit if client can supply slow clock to CORE_CLK when CLKREQ_IN_N is 1[de-asserted]. If this bit is set, Controller neither wake-up from L1 or generate error response for APB access during L1.x. Controller behavior is undefined if register write is performed while slow clock is supplied to core_clk. Recommended flow is to first exit from L1-substate and perform register writes. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_CLIENT_SUPPLIES_SLOW_CLK_TO_CORE_DURING_L1
29 L1DAET R/W 1h L1.x turns off clocks to the controller. Default behavior is made to exit L1.x if Register access request is present at register interface. Setting this bit disables this feature. If this bit is set and CLKREQ_IN_N is 1[de-asserted], Controller responds with ERROR response to APB requests. Client can use CLIENT_EXIT_L1_SUBSTATE pin to trigger L1.x exit if autonomous exit is disabled for register access. This bit is ignored if L1 substate is disabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_DISABLE_AUTONOMOUS_L1_EXIT_ON_NEW_REG_REQ
28 L1TROW R 0h This is a debug status field. '1' in this field indicates that a timeout has occurred while waiting for RX path or OUTstanding packet IDLE conditions. This is cleared on new entry to L1.
27 L1PS R/W 1h This field enabled power shutoff mechanism in L1.2 state. This field is ignored if L1.x is not enabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_POWER_SHUTOFF_ENABLE
26 L1ERC R/W 0h Enables waiting for RX path IDLE condition before entering L1.x. This checks that all packets from PCIE link has reached client side before entering L1.x. This only a tuning register. Not setting this register will cause controller to enter L1.x to save power without checking this. controller will resume transferring RX data once it exit from L1.x state if RX buffers were not empty. This field is ignored if Power shutoff mechanism is enabled for L1.x and Controller will always check RX path idle condition before turning off internal power[with cpf flow]. If timeout is enabled, controller enters L1.x without internal power shutoff after timeout. This bit is ignored if L1 substate is disabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_WAIT_FOR_RX_BUFFER_IDLE
25 L1EOC R/W 0h Enable waiting for outstanding completions before entering L1.x. Outstanding packets expected from pcie link as well as from AXI side is checked. FOR HAL configurations client has to assert PREVENT_L1x_ENTRY signal to prevent L1x entry. This only a tuning register. Not setting this register will cause controller to enter L1.x to save power without checking this. controller exit from L1.x as soon as it receives expected TLps. This field is ignored if Power shutoff mechanism is selected for L1.x and Controller will always wait for outstanding packets before turning off internal power[with cpf flow]. If timeout is enabled, controller enters L1.x without internal power shutoff after timeout. This bit is ignored if L1 substate is disabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_WAIT_FOR_OUTSTANDING_CPLS
RESERVED NONE Reserved
23 - 0 L1TWROI R/W 0h This field enables a timeout mechanism while waiting for RX buffers and Outstanding Pkts before turning off power. Controller enters L1 substate after timeout. A value of 0x0 disables this timeout mechanism. Controller do not select internal power shutoff if it enters L1.x with this timeout. User can give timeout in micro-seconds using this register. This field is ignored if L1 substate is disabled. Power on reset value of this register can be adjusted by modifying the define den_db_LP_DBG_CTRL_RX_CPL_IDLE_CHECK_TIMEOUT

2.5.1.423 PCIE0_TL_INTERNAL_CONTROL Register (Offset = 100C94h) [reset = 2]

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Long Description:

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Table 12-2319 Instance Table
Instance Name Base Address
PCIE0 0D10 0C94h
Figure 12-1176 PCIE0_LM_I_REGF_LM_PCIE_BASE_TL_INTERNAL_CONTROL Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DOOC ECFLR
NONE R/W R/W
1 0

Access Types Legend

Table 12-2320 TL_INTERNAL_CONTROL Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 DOOC R/W 1h Ordering between outbound Completions and posted packets are maintained in transaction layer. This is achieved by blocking Completions if required. Completions arrived after EOP of a posted packet are blocked till that posted packet is transmitted. This Ordering check is required to conform to the PCIe ordering rules. This ordering check can be disabled by setting this field. Power on reset value of this register can be adjusted by modifying the define den_db_TL_CTRL_DISABLE_OB_ORDERING_CHECK
0 ECFLR R/W 0h By default controller ignores config request if a function is under going FLR. Setting this bit Makes the controller to respond with CRS response. Power on reset value of this register can be adjusted by modifying the define den_db_TL_CTRL_ENABLE_CRS_UNDER_FLR

2.5.1.424 PCIE0_I_LOCAL_ERROR_STATUS_2_REGISTER Register (Offset = 100D00h) [reset = 0]

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Long Description:

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Table 12-2321 Instance Table
Instance Name Base Address
PCIE0 0D10 0D00h
Figure 12-1177 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_ERROR_STATUS_2_REGISTER Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31 LEQRQIN R13_11 R10 PTMCNTAINV NFTSTOS R4 R23 R01
R R/W1TC R R R/W1TC R/W1TC R R R
0 0 0 0 0 0 0 0 0

Access Types Legend

Table 12-2322 I_LOCAL_ERROR_STATUS_2_REGISTER Register Field Descriptions
Bit Field Type Reset Description
31 - 15 R31 R 0h Reserved
14 LEQRQIN R/W1TC 0h EP Mode: Indicates that the Controller hardware detected a problem with equalization and automatically requested for equalization redo at the end of the equalization. Controller checks for problems in Recovery.Rcvr.Lock state by comparing the Tx Coefficients agreed at end of Eq Phase2 with the Tx Coefficients received in TS1s in Recovery.Rcvr.Lock state at the end of equalization. Any mismatch is detected and the Request Equalization bit is set in Recovery.Rcvg.Cfg. RC Mode: Indicates that the Controller received Equalization Request from downstream component.
13 - 11 R13_11 R 0h Reserved
10 R10 R 0h Reserved
9 PTMCNTAINV R/W1TC 0h This status bit indicates that the Controller automatically invalidated PTM Context because of PCIe Link exit from L0 State.
8 NFTSTOS R/W1TC 0h This status bit indicates that a NFTS Timeout occurred. This could occur if the PHY failed to achieve lock on the receive data before the NFTS Timeout during Rx_L0s.FTS state. Local Firmware should consider increasing the advertized NFTS values if this event occurs.
7 - 4 R4 R 0h Reserved
3 - 2 R23 R 0h Reserved
1 - 0 R01 R 0h Reserved

2.5.1.425 PCIE0_I_LOCAL_INTRPT_MASK_2_REG Register (Offset = 100D04h) [reset = 16896]

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Long Description:

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Table 12-2323 Instance Table
Instance Name Base Address
PCIE0 0D10 0D04h
Figure 12-1178 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_INTRPT_MASK_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R31
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R31 LEQRQINM R13_11 R10 PCAIM NFTSTOM R4 R23 R01
R R/W R R R/W R/W R R R
0 1 0 0 1 0 0 0 0

Access Types Legend

Table 12-2324 I_LOCAL_INTRPT_MASK_2_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 15 R31 R 0h Reserved
14 LEQRQINM R/W 1h Mask for Link Equalization Request Interrupt.
13 - 11 R13_11 R 0h Reserved
10 R10 R 0h Reserved
9 PCAIM R/W 1h Mask for PTM Context Auto Invalidated event.
8 NFTSTOM R/W 0h Mask for NFTS Timeout.
7 - 4 R4 R 0h Reserved
3 - 2 R23 R 0h Reserved
1 - 0 R01 R 0h Reserved

2.5.1.426 PCIE0_I_LD_CTRL Register (Offset = 100DA0h) [reset = 23027216]

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Long Description:

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Table 12-2325 Instance Table
Instance Name Base Address
PCIE0 0D10 0DA0h
Figure 12-1179 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LD_CTRL Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R7 AUTO_EN LDTIMER
R R/W R/W
0 1 10111110101111000010000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDTIMER
R/W
10111110101111000010000

Access Types Legend

Table 12-2326 I_LD_CTRL Register Field Descriptions
Bit Field Type Reset Description
31 - 25 R7 R 0h Reserved
24 AUTO_EN R/W 1h This bit when set indicates that the link down indication auto reset is enabled
23 - 0 LDTIMER R/W 5F5E10h This is a counter timeout value which triggers the internal logic to reset the link down indication bit in the AXI Configuration registers

2.5.1.427 PCIE0_RX_ELEC_IDLE_FILTER_CONTROL Register (Offset = 100DA4h) [reset = 69206016]

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Long Description:

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Table 12-2327 Instance Table
Instance Name Base Address
PCIE0 0D10 0DA4h
Figure 12-1180 PCIE0_LM_I_REGF_LM_PCIE_BASE_RX_ELEC_IDLE_FILTER_CONTROL Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GFLCP GFLCC
R/W R/W
100 100000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVGFLD GFLD
R R/W
0 0

Access Types Legend

Table 12-2328 RX_ELEC_IDLE_FILTER_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31 - 24 GFLCP R/W 4h This controls the glitch filter on PM Clock domain. This counter indicates the number of PM Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as [PM Clock Period * Number of PM Clocks] this delay should be same or close enough for both Core Clock[GFLCC] and PM Clock[GFLCP]
23 - 16 GFLCC R/W 20h This controls the glitch filter on CORE Clock domain. This counter indicates the number of CORE Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as [CORE Clock Period * Number of CORE Clocks] this delay should be same or close enough for both CORE Clock[GFLCC] and PM Clock[GFLCP]
15 - 1 RSVGFLD R 0h Reserved
0 GFLD R/W 0h By default controller enables glitch filter on all lanes. Setting this bit to one makes the controller to disable the glitch filter on that corresponding lanes in which the bit is set. When all bits are set to one the Glitch filter is completely bypassed, When any bit is zero glitch filter is enabled, and de-glitching is done only on the lanes that are set to zero

2.5.1.428 PCIE0_I_PTM_LOCAL_CONTROL_REG Register (Offset = 100DA8h) [reset = 4368]

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Table 12-2329 Instance Table
Instance Name Base Address
PCIE0 0D10 0DA8h
Figure 12-1181 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_LOCAL_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RES29 DAINVCNT INVPTMCNT RES18 PTMRSEN PTMRSM
R R/W W R R/W R/W
0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMRINT PTMRFRVL PTMRFRSC RES2 PTMRQEN PTMRQM
R/W R/W R/W R R/W R/W
1 1 1 0 0 0

Access Types Legend

Table 12-2330 I_PTM_LOCAL_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 29 RES29 R 0h Reserved
28 DAINVCNT R/W 0h By default, the Controller automatically invalidates PTM Context when the LTSSM exits L0 state. Client may disable this by writing a 1 to this register.
27 INVPTMCNT W 0h Client Firmware may write a 1 to this bit in order to reset the PTM Context. This is a write-only bit. Controller internally clears this bit. Read from this bit returns 0. EP Mode: Resets the PTM Request State Machine. PTM Context is Cleared. RP Mode: Resets the PTM Response State Machine. PTM Context is Cleared.
26 - 18 RES18 R 0h Reserved
17 PTMRSEN R/W 0h EP Mode: Reserved RP Mode: This bit enables Controller [RP] to respond to the received PTM Requests. PTM Response/PTM ResponseD is determined by the PTM Response Mode bit.
1 : Controller automatically responds with Response/ResponseD messages.
0 : Controller does not respond for PTM Requests. [PTM Feature is Bypassed.]
16 PTMRSM R/W 0h EP Mode: Reserved. RP Mode: This bit is used to control the number of PTM dialogs used during each PTM Master Time Request.
1 : Two Dialog Mode - Each PTM Context will have Response followed by ResponseD. Example: Dialog0: Request -> Response. Dialog1: Request -> ResponseD Dialog2: Request -> Response Dialog3: Request -> ResponseD
0 : Continuous Dialog Mode - Each PTM Context will have Only ResponseD. Example: Dialog0: Request -> Response. Dialog1: Request -> ResponseD Dialog2: Request -> ResponseD Dialog3: Request -> ResponseD
15 - 12 PTMRINT R/W 1h EP Mode: In Single,Periodic Request Mode, this field is used to control the time interval [in us] between PTM Requests within a PTM Context. This represents the time the Requester State Machine waits in the WAIT_1US_STATE.
0001 - 1
0010 - 2
0011 - 3
0100 - 4
0101 - 5
0110 - 6
0111 - 7
1000 - 8
1001 - 9
..
1111 - 15 This value is in [us]. RP Mode: Reserved.
11 - 8 PTMRFRVL R/W 1h EP Mode: In Periodic Request Mode, this field is used to control the time interval [value] between successive PTM Context Refresh. This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE.
0001 - 1
0010 - 2
0011 - 3
0100 - 4
0101 - 5
0110 - 6
0111 - 7
1000 - 8
1001 - 9
1010 - 1111 Reserved
This value is multiplied with the scale to determine the PTM Request Time Interval. RP Mode: Reserved.
7 - 4 PTMRFRSC R/W 1h EP Mode: In Periodic Request Mode, this field is used to control the time interval [scale] between successive PTM Context Refresh. This represents the time the Requester State Machine waits in the VALID_PTM_CONTEXT_STATE.
0000 - 1 us
0001 - 10 us
0010 - 100 us
0011 - 1 ms
0100 - 10 ms
0101 - 100 ms
0110 - 1 s
0111 - 10 s
1000 - 100 s
1001 - 1111 - Reserved RP Mode: Reserved.
3 - 2 RES2 R 0h Reserved
1 PTMRQEN R/W 0h EP Mode: This enables Endpoint to request for PTM Master Time.
1 : PTM Requests are Enabled. In Single Request Mode, this bit is used to trigger PTM dialog to obtain PTM Master time exactly once. This bit is auto-cleared after the PTM Master time is obtained. In Periodic Request Mode, this bit enables periodic requests for PTM Master Time. This bit remains set till it is cleared by the EP local firmware.
0 : PTM Requests are Disabled. [PTM Feature is Bypassed.] User may disable PTM requests in the Controller and, if required, generate requests from Client Master Interface. RP Mode: Reserved.
0 PTMRQM R/W 0h EP Mode: This bit controls the pattern of PTM Requests issued by the Endpoint.
0: Single Request Mode.
1: Periodic Request Mode. In Single Request Mode, Endpoint initiates one or two PTM Dialogs till the PTM Master Time is obtained. In Periodic Request Mode, Endpoint initiates PTM Dialogs and obtains PTM Master at periodic intervals. The period is programmable. RP Mode: Reserved.

2.5.1.429 PCIE0_I_PTM_LOCAL_STATUS_REG Register (Offset = 100DACh) [reset = 0]

Short Description:

Long Description:

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Table 12-2331 Instance Table
Instance Name Base Address
PCIE0 0D10 0DACh
Figure 12-1182 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_LOCAL_STATUS_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RES3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES3 PTMCNST
R R
0 0

Access Types Legend

Table 12-2332 I_PTM_LOCAL_STATUS_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 4 RES3 R 0h Reserved
3 - 0 PTMCNST R 0h Reflects the current status of the PTM Context. In EP Mode:
0000 - Invalid PTM Context
0001 - Dialog 1 PTM Request Sent
0011 - Dialog 1 PTM Response Received
0111 - Dialog 2 PTM Request Sent
1111 - Dialog 2 PTM ResponseD Received and PTM Context Valid RP Mode:
0000 - Invalid PTM Context
0001 - Dialog 1 PTM Request Received
0011 - Dialog 1 PTM Response Sent
0111 - Dialog 2 PTM Request Received
1111 - Dialog 2 PTM ResponseD Sent and PTM Context Valid

2.5.1.430 PCIE0_I_PTM_LATENCY_PARAMETERS_INDEX_REG Register (Offset = 100DB0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2333 Instance Table
Instance Name Base Address
PCIE0 0D10 0DB0h
Figure 12-1183 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_LATENCY_PARAMETERS_INDEX_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RES4
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES4 PTMLATIN
R R/W
0 0

Access Types Legend

Table 12-2334 I_PTM_LATENCY_PARAMETERS_INDEX_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 4 RES4 R 0h Reserved
3 - 0 PTMLATIN R/W 0h This is used by FW to select the speed for which the Latency parameters are to be programmed. FW is required to set this to each of the supported speeds and program the corresponding latency parameters in the PTM Latency Parameters Register.
0000 - Gen1 Speed Select
0001 - Gen2 Speed Select
0010 - Gen3 Speed Select
0011 - Gen4 Speed Select
Others - Reserved

2.5.1.431 PCIE0_I_PTM_LATENCY_PARAMETERS_REG Register (Offset = 100DB4h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2335 Instance Table
Instance Name Base Address
PCIE0 0D10 0DB4h
Figure 12-1184 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_LATENCY_PARAMETERS_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDLTUN TXDLTUN RES20 PTMRXLAT
R/W R/W R R/W
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMRXLAT PTMTXLAT
R/W R/W
0 0

Access Types Legend

Table 12-2336 I_PTM_LATENCY_PARAMETERS_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 28 RXDLTUN R/W 0h In EP Mode: This field can be used to add a fixed offset to the captured timestamps t4 and t4_tick. In RP Mode: This field can be used to add a fixed offset to the captured timestamps t2 and t2_tick. Encoding:
0000: + 0 ns
0001: + 1ns
0010: + 2ns
....
1111: + 15ns Separate value can be programmed for each supported speed of operation. The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding value be programmed into this register.
27 - 24 TXDLTUN R/W 0h In EP Mode: This field can be used to add a fixed offset to the captured timestamps t1 and t1_tick. In RP Mode: This field can be used to add a fixed offset to the captured timestamps t3 and t3_tick. Encoding:
0000: + 0 ns
0001: + 1ns
0010: + 2ns
....
1111: + 15ns Separate value can be programmed for each supported speed of operation. The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding value be programmed into this register.
23 - 20 RES20 R 0h Reserved
19 - 10 PTMRXLAT R/W 0h This field should be programmed with the parameter Receive Latency in [ns] from the PHY Datasheet. Separate value can be programmed for each supported speed of operation. The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding latency be programmed into this register.
9 - 0 PTMTXLAT R/W 0h This field should be programmed with the parameter Transmit Latency in [ns] from the PHY Datasheet. Separate value can be programmed for each supported speed of operation. The speed of operation must first be programmed in the PTM Latency Parameters Index Register and then the corresponding latency be programmed into this register.

2.5.1.432 PCIE0_I_PTM_CONTEXT_1_REG Register (Offset = 100DB8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2337 Instance Table
Instance Name Base Address
PCIE0 0D10 0DB8h
Figure 12-1185 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT1T2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT1T2
R
0

Access Types Legend

Table 12-2338 I_PTM_CONTEXT_1_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT1T2 R 0h EP Mode : Represents the lower 32-bits of timestamp t1 in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of timestamp t2 in [ns] as recorded by RP.

2.5.1.433 PCIE0_I_PTM_CONTEXT_2_REG Register (Offset = 100DBCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2339 Instance Table
Instance Name Base Address
PCIE0 0D10 0DBCh
Figure 12-1186 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT1T2U
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT1T2U
R
0

Access Types Legend

Table 12-2340 I_PTM_CONTEXT_2_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT1T2U R 0h EP Mode : Represents the upper 32-bits of timestamp t1 in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of timestamp t2 in [ns] as recorded by RP.

2.5.1.434 PCIE0_I_PTM_CONTEXT_3_REG Register (Offset = 100DC0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2341 Instance Table
Instance Name Base Address
PCIE0 0D10 0DC0h
Figure 12-1187 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_3_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT4T3
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT4T3
R
0

Access Types Legend

Table 12-2342 I_PTM_CONTEXT_3_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT4T3 R 0h EP Mode : Represents the lower 32-bits of Timestamp t4 in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of Timestamp t3 in [ns] as recorded by RP.

2.5.1.435 PCIE0_I_PTM_CONTEXT_4_REG Register (Offset = 100DC4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2343 Instance Table
Instance Name Base Address
PCIE0 0D10 0DC4h
Figure 12-1188 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_4_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT4T3U
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT4T3U
R
0

Access Types Legend

Table 12-2344 I_PTM_CONTEXT_4_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT4T3U R 0h EP Mode : Represents the upper 32-bits of Timestamp t4 in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of imestamp t3 in [ns] as recorded by RP.

2.5.1.436 PCIE0_I_PTM_CONTEXT_5_REG Register (Offset = 100DC8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2345 Instance Table
Instance Name Base Address
PCIE0 0D10 0DC8h
Figure 12-1189 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_5_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT1KT2K
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT1KT2K
R
0

Access Types Legend

Table 12-2346 I_PTM_CONTEXT_5_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT1KT2K R 0h EP Mode : Represents the lower 32-bits of Timestamp t1_tick in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of Timestamp t2_tick in [ns] as recorded by RP.

2.5.1.437 PCIE0_I_PTM_CONTEXT_6_REG Register (Offset = 100DCCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2347 Instance Table
Instance Name Base Address
PCIE0 0D10 0DCCh
Figure 12-1190 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_6_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT1KT2KU
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT1KT2KU
R
0

Access Types Legend

Table 12-2348 I_PTM_CONTEXT_6_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT1KT2KU R 0h EP Mode : Represents the upper 32-bits of Timestamp t1_tick in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of Timestamp t2_tick in [ns] as recorded by RP.

2.5.1.438 PCIE0_I_PTM_CONTEXT_7_REG Register (Offset = 100DD0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2349 Instance Table
Instance Name Base Address
PCIE0 0D10 0DD0h
Figure 12-1191 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_7_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT4KT3K
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT4KT3K
R
0

Access Types Legend

Table 12-2350 I_PTM_CONTEXT_7_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT4KT3K R 0h EP Mode : Represents the lower 32-bits of Timestamp t4_tick in [ns] as recorded by Endpoint. RP Mode : Represents the lower 32-bits of Timestamp t3_tick in [ns] as recorded by RP.

2.5.1.439 PCIE0_I_PTM_CONTEXT_8_REG Register (Offset = 100DD4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2351 Instance Table
Instance Name Base Address
PCIE0 0D10 0DD4h
Figure 12-1192 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_8_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT4KT3KU
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT4KT3KU
R
0

Access Types Legend

Table 12-2352 I_PTM_CONTEXT_8_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT4KT3KU R 0h EP Mode : Represents the upper 32-bits of Timestamp t4_tick in [ns] as recorded by Endpoint. RP Mode : Represents the upper 32-bits of Timestamp t3_tick in [ns] as recorded by RP.

2.5.1.440 PCIE0_I_PTM_CONTEXT_9_REG Register (Offset = 100DD8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2353 Instance Table
Instance Name Base Address
PCIE0 0D10 0DD8h
Figure 12-1193 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_9_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMT3MT2
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMT3MT2
R
0

Access Types Legend

Table 12-2354 I_PTM_CONTEXT_9_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMT3MT2 R 0h Propagation Delay. EP Mode : Represents the Propagation Delay [t3 - t2] in [ns] as received in ResponseD Message by Endpoint. RP Mode - Reserved.

2.5.1.441 PCIE0_I_PTM_CONTEXT_10_REG Register (Offset = 100DDCh) [reset = 0]

Short Description:

Long Description:

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Table 12-2355 Instance Table
Instance Name Base Address
PCIE0 0D10 0DDCh
Figure 12-1194 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_10_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMMSTT1T
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMMSTT1T
R
0

Access Types Legend

Table 12-2356 I_PTM_CONTEXT_10_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMMSTT1T R 0h EP Mode - Represents the lower 32-bits of PTM Master Time at timestamp t1_tick in [ns] as computed by Endpoint. RP Mode - Reserved.

2.5.1.442 PCIE0_I_PTM_CONTEXT_11_REG Register (Offset = 100DE0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2357 Instance Table
Instance Name Base Address
PCIE0 0D10 0DE0h
Figure 12-1195 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_11_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTMMSTT1TU
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTMMSTT1TU
R
0

Access Types Legend

Table 12-2358 I_PTM_CONTEXT_11_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTMMSTT1TU R 0h EP Mode - Represents the upper 32-bits of PTM Master Time at Timestamp t1_tick in [ns] as computed by Endpoint. RP Mode - Reserved.

2.5.1.443 PCIE0_I_EQ_DEBUG_MON_CONTROL_REG Register (Offset = 100E4Ch) [reset = 1120]

Short Description:

Long Description:

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Table 12-2359 Instance Table
Instance Name Base Address
PCIE0 0D10 0E4Ch
Figure 12-1196 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R1
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R1 CAPTBEH CAPTSPDSEL CAPTPHSEL CAPTLNSEL CLRCAPT
R R R/W R/W R/W R/W
0 1 0 11 0 0

Access Types Legend

Table 12-2360 I_EQ_DEBUG_MON_CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 11 R1 R 0h Reserved
10 CAPTBEH R 1h If this is set , the first 64 equalization info events are captured else the last 64 events are captured
9 - 7 CAPTSPDSEL R/W 0h Selects the Link Speed at which capture is to be done 000 : Any speed, 001 : Gen 3, 010 : Gen 4, 100 : Gen 5
6 - 5 CAPTPHSEL R/W 3h Selects the Equalization Phase when capture is to be done 01 : Phase 2, 10 : Phase 3, 11 : Phase 2 and 3
4 - 1 CAPTLNSEL R/W 0h Selects the Lane whose Equalization Debug information is to be captured. Please note,this signifies the physical lane number.
0 CLRCAPT R/W 0h Setting this bit clears all captured information in the EQ Debug Status Registers. If it is unset then capture is allowed in status registers.

2.5.1.444 PCIE0_I_EQ_DEBUG_MON_STATUS0_REG Register (Offset = 100E50h) [reset = 0]

Short Description:

Long Description:

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Table 12-2361 Instance Table
Instance Name Base Address
PCIE0 0D10 0E50h
Figure 12-1197 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_STATUS0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R1 REMLF REMFS
R R R
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REMFS LCLLF LCLFS
R R R
0 0 0

Access Types Legend

Table 12-2362 I_EQ_DEBUG_MON_STATUS0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 24 R1 R 0h Reserved
23 - 18 REMLF R 0h Remote PHY's LF Value Of the Lane and Speed Selected.
17 - 12 REMFS R 0h Remote PHY's FS Value Of the Lane and Speed Selected.
11 - 6 LCLLF R 0h Local PHY's LF Value Of the Lane and Speed Selected.
5 - 0 LCLFS R 0h Local PHY's FS Value Of the Lane and Speed Selected.

2.5.1.445 PCIE0_I_EQ_DEBUG_MON_STATUS_REG Register (Offset = 100E54h) [reset = 0]

Short Description:

Long Description:

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Table 12-2363 Instance Table
Instance Name Base Address
PCIE0 0D10 0E54h
Figure 12-1198 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_STATUS_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EQPHASE DIRFED COEFFREJ EQPREVD EQPRE EQCOEFF
R R R R R R
0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EQCOEFF
R
0

Access Types Legend

Table 12-2364 I_EQ_DEBUG_MON_STATUS_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 30 EQPHASE R 0h Equalization Phase during Capture 00 : Phase 0, 01 : Phase 1, 10 : Phase 2, 11 : Phase 3
29 - 24 DIRFED R 0h EP Ph2/RC Ph3: Stores Direction Change Feedback or Preset feedback Transmitted to Remote Device. Bit-22, EQPREVD, indicates if this is a Preset feedback or Direction Change Feedback. EP Ph3/RC Ph2: Reserved
23 COEFFREJ R 0h Phase0: Set to '1' if an unsupported preset is received in Phase0. Phase1: Set to '0' since no reject in phase1. EP Ph2/RC Ph3: Indicates Reject by the Remote end device. This bit indicates that the current Coefficient or Preset was rejected by the remote end device. EP Ph3/RC Ph2: Indicates that Controller Rejected the received settings to Remote Device in the TX TS1/TS2. This Reject indicates the current Coefficients or Preset received from Remote Device are rejected
22 EQPREVD R 0h 1: Preset Valid, Indicates [21:18] is valid. Phase0: Set to '1' to indicate that the initial Local Preset is Valid. Phase1: Set to '1' to indicate that the advertised Remote Preset is Valid. EP Ph2/RC Ph3: Set to 1 if controller provide preset feedback and to 0 for coefficient feedback. EP Ph3/RC Ph2: Reflects the use preset bit received from the remote end.
21 - 18 EQPRE R 0h Phase0: Stores Initial Local TX Preset received in Phase0. Phase1: Stores Initial Remote Preset advertised in Phase1. EP Ph2/RC Phase3: Stores Current Preset of the Remote Device. EP Ph3/RC Phase2: Stores Preset Received from Remote Device.
17 - 0 EQCOEFF R 0h Phase0: Stores Initial Local TX Coefficients mapped from Initial Preset. Phase1: Stores Initial Remote Coefficients advertised in Phase1. [Cp, LF, FS] , EP Ph2/RC Phase3: Stores Current Coefficients of the Remote Device. EP Ph3/RC Phase2: Stores Coefficients Received from Remote Device.

2.5.1.446 PCIE0_I_AXI_FEATURE_REG Register (Offset = 100E5Ch) [reset = 2]

Short Description:

Long Description:

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Table 12-2365 Instance Table
Instance Name Base Address
PCIE0 0D10 0E5Ch
Figure 12-1199 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_AXI_FEATURE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R30
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R30 SLVERRCTRL R0
R R/W R
0 1 0

Access Types Legend

Table 12-2366 I_AXI_FEATURE_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 2 R30 R 0h Reserved
1 SLVERRCTRL R/W 1h This bit if set to 1, AXI Slave masks the SLVERR response to be given in case of UR or CRS completion for configuration requests. If this bit is set to 0,UR and CRS completions from the link causes SLVERR at AXI.
0 R0 R 0h Reserved

Short Description:

Long Description:

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Table 12-2367 Instance Table
Figure 12-1200 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_LINK_EQ_CONTROL_2_REG Name Register

Access Types Legend

Table 12-2368 I_LINK_EQ_CONTROL_2_REG Register Field Descriptions

2.5.1.448 PCIE0_I_CORE_FEATURE_REG Register (Offset = 100E64h) [reset = 0]

Short Description:

Long Description:

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Table 12-2369 Instance Table
Instance Name Base Address
PCIE0 0D10 0E64h
Figure 12-1201 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_CORE_FEATURE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R30
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R30 R2 APBCTRL R0
R R R/W R
0 0 0 0

Access Types Legend

Table 12-2370 I_CORE_FEATURE_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 3 R30 R 0h Reserved
2 R2 R 0h Reserved
1 APBCTRL R/W 0h When set the Core will return SLVERR on the APB bus for Read or Writes to Configuration or Local Management registers
0 R0 R 0h Reserved

2.5.1.449 PCIE0_I_RX_INVERT_POLARITY_REG Register (Offset = 100E88h) [reset = 0]

Short Description:

Long Description:

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Table 12-2371 Instance Table
Instance Name Base Address
PCIE0 0D10 0E88h
Figure 12-1202 PCIE0_LM_I_REGF_LM_PCIE_BASE_I_RX_INVERT_POLARITY_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R30
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R30 RIPR
R R
0 0

Access Types Legend

Table 12-2372 I_RX_INVERT_POLARITY_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 1 R30 R 0h Reserved
0 RIPR R 0h shows the polarity inversion status of each lane

2.5.1.450 PCIE0_REVID Register (Offset = 0h) [reset = 1746147584]

Short Description:

Long Description:

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Table 12-2373 Instance Table
Instance Name Base Address
PCIE0 0F10 0000h
Figure 12-1203 PCIE0_REVID Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODID
R
110100000010100
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVRTL REVMAJ CUSTOM REVMIN
R R R R
11 1 0 0

Access Types Legend

Table 12-2374 REVID Register Field Descriptions
Bit Field Type Reset Description
31 - 16 MODID R 6814h Module ID field
15 - 11 REVRTL R 3h RTL revision. Will vary depending on release
10 - 8 REVMAJ R 1h Major revision
7 - 6 CUSTOM R 0h Custom
5 - 0 REVMIN R 0h Minor revision

2.5.1.451 PCIE0_CMD_STATUS Register (Offset = 4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2375 Instance Table
Instance Name Base Address
PCIE0 0F10 0004h
Figure 12-1204 PCIE0_CMD_STATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LINK_TRAINING_ENABLE
NONE R/W
0

Access Types Legend

Table 12-2376 CMD_STATUS Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 LINK_TRAINING_ENABLE R/W 0h This bit must be set to 1 to enable the LTSSM to bring up the link. Setting it to 0 forces the LTSSM to stay in the Detect.Quiet state.

2.5.1.452 PCIE0_RSTCMD Register (Offset = 8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2377 Instance Table
Instance Name Base Address
PCIE0 0F10 0008h
Figure 12-1205 PCIE0_RSTCMD Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED INIT_HOT_RESET
NONE R/W
0

Access Types Legend

Table 12-2378 RSTCMD Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 INIT_HOT_RESET R/W 0h When this bit is set to 1'b1 in the RP mode, the core initiates a Hot Reset sequence on the PCIe link. The controller will keep the PCIe link in hot reset when this bit is asserted. When de-asserted, controller will bring the PCIe link out of hot reset and initiate link training. Valid in RP mode only

2.5.1.453 PCIE0_INITCFG Register (Offset = Ch) [reset = 29630461]

Short Description:

Long Description:

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Table 12-2379 Instance Table
Instance Name Base Address
PCIE0 0F10 000Ch
Figure 12-1206 PCIE0_INITCFG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CONFIG_ENABLE VC_COUNT MAX_EVAL_ITERATION
NONE R/W R/W R/W
1 11 1000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_EVAL_ITERATION BYPASS_PHASE23 BYPASS_REMOTE_TX_EQUALIZATION SUPPORTED_PRESET DISABLE_GEN3_DC_BALANCE SRIS_ENABLE
R/W R/W R/W R/W R/W R/W
1000 0 0 11111111111 0 1

Access Types Legend

Table 12-2380 INITCFG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
24 CONFIG_ENABLE R/W 1h When this bit is set to 0 in the EP mode, the Controller will generate a CRS Completion in response to Configuration Requests. When this bit is set to 1 in the EP mode, the Controller will generate SC/UR Completion in response to Configuration Requests based on the target function. In systems where the Controller configuration registers are loaded from RAM on power-up, this prevents the Controller from responding to Configuration Requests before all the registers are loaded. This bit is unused in RP Mode. The default value of this bit will be 1 in EP mode and 0 in RP mode
23 - 22 VC_COUNT R/W 3h Number of VCs configured.
00 = 1 VC
01 = 2 VCs,
10 = 3 VCs,
11 = 4 VCs, .. and so on
21 - 15 MAX_EVAL_ITERATION R/W 8h Denotes the maximum number of iterations to be performed during the Direction Change Feedback Link Equalization in case the direction change feedback does not converge to 00. Supported values are 8-63. Recommended Value is from 8-16 to avoid the 24ms timeout as defined in PCIe spec.
14 BYPASS_PHASE23 R/W 0h This MMR should be programmed during system boot or initialization. This is used only in Root Port Mode of the PCIe Core.
If BYPASS_PHASE23 == 1: * Phase 2 AND Phase 3 of Link Equalization are bypassed during link equalization.
If BYPASS_PHASE23 == 0: * Phase 2 AND Phase 3 of Link Equalization are performed during link equalization.
13 BYPASS_REMOTE_TX_EQUALIZATION R/W 0h This MMR should be programmed during system boot or initialization. IF BYPASS_REMOTE_TX_EQUALIZATION == 1: * In End-Point mode, Phase 2 of link equalization is bypassed * In Root-Port mode, Phase 3 of link equalization is bypassed IF BYPASS_REMOTE_TX_EQUALIZATION == 0: * Remote TX Equalization is performed during link equalization
12 - 2 SUPPORTED_PRESET R/W 7FFh This MMR should be programmed during system boot or initialization. SUPPORTED_PRESET[i]=1. Indicates Preset #i supported by PHY. SUPPORTED_PRESET[i]=0. Indicates Preset #i is not supported by PHY. * For Full Swing, all presets [P0 - P10] must be supported. * For Reduced Swing, [P4, P1, P9, P5, P6, P3] must be supported, others are optional as per PCIe spec.
1 DISABLE_GEN3_DC_BALANCE R/W 0h This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed. This feature was introduced in the 0.71 version of the Gen3 spec. Setting this input to 1 disables the transmission of the special DC Balance symbols by the Controller. Note that the Controller can decode received training sequences with the special DC balance symbols in them correctly regardless of the setting of this input.
0 SRIS_ENABLE R/W 1h Should be set as per the System Reference Clocking Implementation.
0 = Separate Tx and Rx Reference Clocks with No Spread Spectum Clocking - SRNS Mode
1 = Separate Tx and Rx Reference Clocks with Spread Spectum Clocking - SRIS Mode. This is the default setting. Note that the common Refclk architecture utilizes the same Refclk for Tx and Rx and so does not introduce any difference between the Tx and Rx Refclk rates. SRIS_ENABLE should be tied to 0 in this case also.

2.5.1.454 PCIE0_PMCMD Register (Offset = 10h) [reset = 0]

Short Description:

Long Description:

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Table 12-2381 Instance Table
Instance Name Base Address
PCIE0 0F10 0010h
Figure 12-1207 PCIE0_PMCMD Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED POWER_STATE_CHANGE_ACK CLIENT_REQ_EXIT_L1_SUBSTATE CLIENT_REQ_EXIT_L1
NONE R/W R/W R/W
0 0 0

Access Types Legend

Table 12-2382 PMCMD Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
2 POWER_STATE_CHANGE_ACK R/W 0h Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT, when it is ready to transition to the low-power state requested by the configuration write request. Software may maintain this input high if it does not need to delay the return of the completions for the configuration write transactions causing power-state changes.
Note: No PCIe completion is generated as long as POWER_STATE_CHANGE_ACK is ‘0’
Note1: Configuring POWER_STATE_CHANGE_ACK to ‘1’ for generating PCIe completion.
1 CLIENT_REQ_EXIT_L1_SUBSTATE R/W 0h Client logic can trigger an explicit L1-substate exit by setting this bit. This bit triggers an exit from L1-substates to L0 if controller is already in L1- substates. Controller waits in L1 state for this signal to become de-asserted before entering L1-substate. Controller will respond to normal L1-exit triggers while it waits for de-assertion of this bit.
0 CLIENT_REQ_EXIT_L1 R/W 0h Client logic can trigger an explicit L1 exit by setting this bit. This bit triggers an exit to L0 from L1 or from L1-substates. This bit can also be used to block L1 entry in End point controllers.

2.5.1.455 PCIE0_LINKSTATUS Register (Offset = 14h) [reset = 0]

Short Description:

Long Description:

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Table 12-2383 Instance Table
Instance Name Base Address
PCIE0 0F10 0014h
Figure 12-1208 PCIE0_LINKSTATUS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED LTSSM_STATE RESERVED
NONE R NONE
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED L1_PM_SUBSTATE LINK_POWER_STATE RESERVED NEGOTIATED_SPEED NEGOTIATED_LINK_WIDTH LINK_STATUS
NONE R R NONE R R R
0 0 0 0 0

Access Types Legend

Table 12-2384 LINKSTATUS Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
29 - 24 LTSSM_STATE R 0h Current state of the Link Training and Status State Machine within the core. The encodings of this output are described below: 00h - Detect.Quiet 01h - Detect.Active 02h - Polling.Active 03h - Polling.Compliance 04h - Polling.Configuration05h - Configuration.Linkwidth.Start06h - Configuration.Linkwidth.Accept07h - Configuration.Lanenum.Accept08h - Configuration.Lanenum.Wait09h - Configuration.Complete0Ah - Configuration.Idle0Bh - Recovery.RcvrLock0Ch - Recovery.Speed0Dh - Recovery.RcvrCfg0Eh - Recovery.Idle10h - L0 11h - Rx_L0s.Entry12h - Rx_L0s.Idle 13h - Rx_L0s.FTS 14h - Tx_L0s.Entry 15h - Tx_L0s.Idle 16h - Tx_L0s.FTS 17h - L1.Entry 18h - L1.Idle 19h - L2.Idle 1Ah - L2.TransmitWake 20h- Disabled 21h - Loopback.Entry (Master) 22h - Loopback.Active (Master) 23h - Loopback.Exit (Master) 24h - Loopback.Entry (Slave) 25h - Loopback.Active (Slave)
RESERVED NONE Reserved
14 - 12 L1_PM_SUBSTATE R 0h This register provides the current state of the L1 PM substates state machine. Its encodings are:
000 = L1-substate machine not active
001 = L1.0 substate. L1_PM_SUBSTATE shows "L1.0" after the delay programmed in L1 substate entry delay in reg:low_power_debug_control0
010 = L1.1 substate
011 = Reserved
100 = L1.2.Entry substate
101 = L1.2.Idle substate
110 = L1.2.Exit substate
111 = Reserved
11 - 8 LINK_POWER_STATE R 0h Current power state of the PCIe link.
0001 = L0
0010 = L0s
0100 = L1
1000 = L2
RESERVED NONE Reserved
5 - 4 NEGOTIATED_SPEED R 0h Current operating speed of the link is as follows:
11: 16 GT/s
10: 8GT/s
01: 5GT/s
00: 2.5GT/s
3 - 2 NEGOTIATED_LINK_WIDTH R 0h Current link width are as follows: 10: x4 01: x2 00: x1 Others: Reserved
1 - 0 LINK_STATUS R 0h Status of the PCI Express link.
00 = No receivers detected.
01 = Link training in progress.
10 = Link up, DL initialization in progress.
11 = Link up, DL initialization completed.

2.5.1.456 PCIE0_LEGACY_INTR_SET Register (Offset = 18h) [reset = 0]

Short Description:

Long Description:

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Table 12-2385 Instance Table
Instance Name Base Address
PCIE0 0F10 0018h
Figure 12-1209 PCIE0_LEGACY_INTR_SET Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED INTA_IN
NONE R/W
0

Access Types Legend

Table 12-2386 LEGACY_INTR_SET Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 INTA_IN R/W 0h When the core is configured as EP, this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. This bit corresponds to INTA of the PCI bus. Asserting this bit causes the core to send out an Assert_INTx message, and de-asserting this bit causes the core to transmit a Deassert_INTx message.

2.5.1.457 PCIE0_LEGACY_INT_PENDING Register (Offset = 1Ch) [reset = 0]

Short Description:

Long Description:

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Table 12-2387 Instance Table
Instance Name Base Address
PCIE0 0F10 001Ch
Figure 12-1210 PCIE0_LEGACY_INT_PENDING Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED INT_ACK RESERVED INT_PENDING_STATUS
NONE R/W1TC NONE R/W
0 0

Access Types Legend

Table 12-2388 LEGACY_INT_PENDING Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
8 INT_ACK R/W1TC 0h When using legacy interrupts, this bit indicates that the core has sent an INTx Assert or De-assert message in response to a change in the state of one of the INTx inputs.
RESERVED NONE Reserved
0 INT_PENDING_STATUS R/W 0h When using legacy interrupts, this input is used to indicate the interrupt pending status of the Physical Functions. The bit i must be set when an interrupt is pending in Function i.

2.5.1.458 PCIE0_MSI_STAT Register (Offset = 20h) [reset = 0]

Short Description:

Long Description:

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Table 12-2389 Instance Table
Instance Name Base Address
PCIE0 0F10 0020h
Figure 12-1211 PCIE0_MSI_STAT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MSI_ENABLE
NONE R
0

Access Types Legend

Table 12-2390 MSI_STAT Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 MSI_ENABLE R 0h When the core is configured in the EndPoint mode to support MSI interrupts, this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions. 0 represents the MSI Enable for Physical Function0 1 represents the MSI Enable for Physical Function 1

2.5.1.459 PCIE0_MSI_VECTOR Register (Offset = 24h) [reset = 0]

Short Description:

Long Description:

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Table 12-2391 Instance Table
Instance Name Base Address
PCIE0 0F10 0024h
Figure 12-1212 PCIE0_MSI_VECTOR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MSI_VECTOR_COUNT
NONE R
0

Access Types Legend

Table 12-2392 MSI_VECTOR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
2 - 0 MSI_VECTOR_COUNT R 0h When the core is configured in the EndPoint mode to support MSI interrupts, these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions. These bits encode the number of allocated MSI interrupt vectors for the corresponding Function. Bits[2:0] represents Physical Function0 and Bits[5:3] represents Physical Function 1

2.5.1.460 PCIE0_MSI_MASK_PF0 Register (Offset = 28h) [reset = 0]

Short Description:

Long Description:

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Table 12-2393 Instance Table
Instance Name Base Address
PCIE0 0F10 0028h
Figure 12-1213 PCIE0_MSI_MASK_PF0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSI_MASK_PF0
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSI_MASK_PF0
R
0

Access Types Legend

Table 12-2394 MSI_MASK_PF0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 MSI_MASK_PF0 R 0h These bits provide the setting of the MSI Mask registers of the Physical Function0.

2.5.1.461 PCIE0_MSI_PENDING_STATUS_PF0 Register (Offset = 40h) [reset = 0]

Short Description:

Long Description:

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Table 12-2395 Instance Table
Instance Name Base Address
PCIE0 0F10 0040h
Figure 12-1214 PCIE0_MSI_PENDING_STATUS_PF0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSI_PENDING_STATUS_PF0
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSI_PENDING_STATUS_PF0
R/W
0

Access Types Legend

Table 12-2396 MSI_PENDING_STATUS_PF0 Register Field Descriptions
Bit Field Type Reset Description
31 - 0 MSI_PENDING_STATUS_PF0 R/W 0h These inputs provide the status of the MSI pending interrupts for the Physical Function0 from the client to the core. If MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF0.

2.5.1.462 PCIE0_MSIX_STAT Register (Offset = A4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2397 Instance Table
Instance Name Base Address
PCIE0 0F10 00A4h
Figure 12-1215 PCIE0_MSIX_STAT Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MSIX_ENABLE
NONE R
0

Access Types Legend

Table 12-2398 MSIX_STAT Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 MSIX_ENABLE R 0h These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions. 0 represents the MSIX Enable for Physical Function0 1 represents the MSIX Enable for Physical Function 1

2.5.1.463 PCIE0_MSIX_MASK Register (Offset = A8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2399 Instance Table
Instance Name Base Address
PCIE0 0F10 00A8h
Figure 12-1216 PCIE0_MSIX_MASK Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED MSIX_MASK
NONE R
0

Access Types Legend

Table 12-2400 MSIX_MASK Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 MSIX_MASK R 0h These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions. 0 represents Physical Function0 1 represents Physical Function1

2.5.1.464 PCIE0_FLR_DONE Register (Offset = B4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2401 Instance Table
Instance Name Base Address
PCIE0 0F10 00B4h
Figure 12-1217 PCIE0_FLR_DONE Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED FLR_DONE
NONE W
0

Access Types Legend

Table 12-2402 FLR_DONE Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 FLR_DONE W 0h These bits are connected to the FLR_DONE bits on the PCIe controller core. In EP mode, software needs to write a 1 to bit0 within 100ms after PF0 function-level reset interrupt is asserted. The FLR_DONE[0] input of the PCIe controller is pulsed for one cycle to acknowledge to the core that the application level function level reset processing is complete. This bit will self-clear once the FLR_DONE[0] is pulsed. The PCIe controller will maintain FLR_IN_PROGRESS[0] output high until it is acknowledged by asserting FLR_DONE. Bit 1 is used to acknowledge FLR_DONE for PF1. These bits are not used in RP mode

2.5.1.465 PCIE0_PTM_CFG Register (Offset = BCh) [reset = 256]

Short Description:

Long Description:

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Table 12-2403 Instance Table
Instance Name Base Address
PCIE0 0F10 00BCh
Figure 12-1218 PCIE0_PTM_CFG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PTM_EP_TIMER_ADJ RESERVED PTM_CLK_SEL
NONE R/W NONE R/W
1 0

Access Types Legend

Table 12-2404 PTM_CFG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
10 - 8 PTM_EP_TIMER_ADJ R/W 1h PTM EP Timer tick adjust value. 1 will increment ptm_ep_timer by 1 each clock cycle, 2 will increment the timer by 2 .. 7 will increment the timer by 7. The adjust value should be set prior to enabling PTM operation in the PCIe controller.
RESERVED NONE Reserved
6 - 0 PTM_CLK_SEL R/W 0h Select CPTS HW1 push input. 0 will select ptm_local_timer[0], 1 will select ptm_local_timer[1] ... 63 will select ptm_local_timer[63] and 64 will select ptm_local_timer_out_valid. The values 65 to 127 are unused. The PTM clock select bit should be set prior to enabling the PTM operation in the PCIe controller

2.5.1.466 PCIE0_PTM_TIMER_LOW Register (Offset = C0h) [reset = 0]

Short Description:

Long Description:

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Table 12-2405 Instance Table
Instance Name Base Address
PCIE0 0F10 00C0h
Figure 12-1219 PCIE0_PTM_TIMER_LOW Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTM_TIMER_OUT_LOW
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTM_TIMER_OUT_LOW
R
0

Access Types Legend

Table 12-2406 PTM_TIMER_LOW Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTM_TIMER_OUT_LOW R 0h ptm_timer_out[31:0] value from PCIe core. Valid in EP mode only

2.5.1.467 PCIE0_PTM_TIMER_HIGH Register (Offset = C4h) [reset = 0]

Short Description:

Long Description:

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Table 12-2407 Instance Table
Instance Name Base Address
PCIE0 0F10 00C4h
Figure 12-1220 PCIE0_PTM_TIMER_HIGH Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTM_TIMER_OUT_HIGH
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTM_TIMER_OUT_HIGH
R
0

Access Types Legend

Table 12-2408 PTM_TIMER_HIGH Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PTM_TIMER_OUT_HIGH R 0h ptm_timer_out[63:32] value from PCIe core. Valid in EP mode only

2.5.1.468 PCIE0_EOI_VECTOR Register (Offset = C8h) [reset = 0]

Short Description:

Long Description:

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Table 12-2409 Instance Table
Instance Name Base Address
PCIE0 0F10 00C8h
Figure 12-1221 PCIE0_EOI_VECTOR Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EOI_VECTOR
NONE R/W
0

Access Types Legend

Table 12-2410 EOI_VECTOR Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 EOI_VECTOR R/W 0h EOI vector for level interrupts. Writing the EOI value as specfied to this register will re-trigger a pending interrupt.
0 - Downstream interrupt 1 - FLR interrupt
2 - Legacy interrupt
3 - Power state interrupt

2.5.1.469 PCIE0_OB_VIRTID_MATCH Register (Offset = 400h) [reset = 0]

Short Description:

Long Description:

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Table 12-2411 Instance Table
Instance Name Base Address
PCIE0 0F10 1400h
Figure 12-1222 PCIE0_OB_VIRTID_MATCH Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED VAL RESERVED
NONE R/W NONE
0

Access Types Legend

Table 12-2412 OB_VIRTID_MATCH Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
11 - 5 VAL R/W 0h Outbound virtid[11:5] match value. When outbound VBUSM slave interface virtid[11:5] matches the value in this register and the ASEL value is non-zero, the PCIe controller address translation unit (ATU) is bypassed. The PCIe TLP descriptor values are taken from the ext_desc registers.
RESERVED NONE Reserved

2.5.1.470 PCIE0_DESC Register (Offset = 300h) [reset = 0]

Short Description:

Long Description:

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Offset = 300h + (j * 4h); where j = 0h to 1Fh

Table 12-2413 Instance Table
Instance Name Base Address
PCIE0 0F10 1300h
Figure 12-1223 PCIE0_EXT_DESC_J Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRAFFIC_CLASS RESERVED BD_EN
R/W NONE R/W
0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUS_NUM DEV_FUNC_NUM
R/W R/W
0 0

Access Types Legend

Table 12-2414 DESC Register Field Descriptions
Bit Field Type Reset Description
31 - 29 TRAFFIC_CLASS R/W 0h PCIe Traffic Class (TC) associated with the non-zero ASEL request.
RESERVED NONE Reserved
16 BD_EN R/W 0h External bus and device number enable. This bit enables the client to supply the bus and device numbers to be used in the requester ID. If this bit is 0, the core uses the captured values of the bus and device numbers to form the Requester ID. If this bit is 1, the core uses the bus and device numbers supplied by the client on dev_func_num[7:4] and bus_num[15:8] to form the Requester ID. This bit must always be set while originating requests in the RP mode, and the corresponding Requester ID must be placed on dev_func_num[7:4] and bus_num[15:8].
15 - 8 BUS_NUM R/W 0h PCI Bus Number associated with the request. When descriptor bit[16] is set, this field must specify the bus number to be used for the Requester ID. Otherwise, this field is ignored by the core.
7 - 0 DEV_FUNC_NUM R/W 0h PCI Function and Device Number associated with the request. In ARI mode, all 8 bits are used to indicate the requesting function number. In legacy mode, dev_func_num[2:0] are used to specified the function number and dev_func_num[7:3] are used to specify the device number to be used within the Requester ID, if the descriptor bit[16] is set. If the descriptor bit[16] is not set, then bits dev_func_num[7:3] are ignored.

2.5.1.471 PCIE0_REVISION Register (Offset = 0h) [reset = 1720754688]

Short Description:

Long Description:

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Table 12-2415 Instance Table
Instance Name Base Address
PCIE0 0F10 2000h
Figure 12-1224 PCIE0_REVISION Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCHEME BU FUNCTION
R R R
1 10 11010010000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTLVER MAJREV CUSTOM MINREV
R R R R
10100 10 0 0

Access Types Legend

Table 12-2416 REVISION Register Field Descriptions
Bit Field Type Reset Description
31 - 30 SCHEME R 1h Scheme
29 - 28 BU R 2h BU
27 - 16 FUNCTION R 690h Module ID
15 - 11 RTLVER R 14h RTL revisions
10 - 8 MAJREV R 2h Major revision
7 - 6 CUSTOM R 0h Custom revision
5 - 0 MINREV R 0h Minor revision

2.5.1.472 PCIE0_ENABLE_REG_SYS_0 Register (Offset = 100h) [reset = 0]

Short Description:

Long Description:

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Table 12-2417 Instance Table
Instance Name Base Address
PCIE0 0F10 2100h
Figure 12-1225 PCIE0_ENABLE_REG_SYS_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_DOWNSTREAM
NONE R/W1TS
0

Access Types Legend

Table 12-2418 ENABLE_REG_SYS_0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_DOWNSTREAM R/W1TS 0h Enable Set for sys_en_pcie_downstream

2.5.1.473 PCIE0_ENABLE_REG_SYS_1 Register (Offset = 104h) [reset = 0]

Short Description:

Long Description:

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Table 12-2419 Instance Table
Instance Name Base Address
PCIE0 0F10 2104h
Figure 12-1226 PCIE0_ENABLE_REG_SYS_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED ENABLE_SYS_EN_PCIE_PWR_STATE ENABLE_SYS_EN_PCIE_LEGACY_3 ENABLE_SYS_EN_PCIE_LEGACY_2 ENABLE_SYS_EN_PCIE_LEGACY_1 ENABLE_SYS_EN_PCIE_LEGACY_0 RESERVED
NONE R/W1TS R/W1TS R/W1TS R/W1TS R/W1TS NONE
0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_FLR
NONE R/W1TS
0

Access Types Legend

Table 12-2420 ENABLE_REG_SYS_1 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
26 ENABLE_SYS_EN_PCIE_PWR_STATE R/W1TS 0h Enable Set for sys_en_pcie_pwr_state
25 ENABLE_SYS_EN_PCIE_LEGACY_3 R/W1TS 0h Enable Set for sys_en_pcie_legacy_3
24 ENABLE_SYS_EN_PCIE_LEGACY_2 R/W1TS 0h Enable Set for sys_en_pcie_legacy_2
23 ENABLE_SYS_EN_PCIE_LEGACY_1 R/W1TS 0h Enable Set for sys_en_pcie_legacy_1
22 ENABLE_SYS_EN_PCIE_LEGACY_0 R/W1TS 0h Enable Set for sys_en_pcie_legacy_0
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_FLR R/W1TS 0h Enable Set for sys_en_pcie_flr

2.5.1.474 PCIE0_ENABLE_REG_SYS_2 Register (Offset = 108h) [reset = 0]

Short Description:

Long Description:

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Table 12-2421 Instance Table
Instance Name Base Address
PCIE0 0F10 2108h
Figure 12-1227 PCIE0_ENABLE_REG_SYS_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_PTM ENABLE_SYS_EN_PCIE_LINK_STATE ENABLE_SYS_EN_PCIE_HOT_RESET ENABLE_SYS_EN_PCIE_ERROR_2 ENABLE_SYS_EN_PCIE_ERROR_1 ENABLE_SYS_EN_PCIE_ERROR_0 RESERVED ENABLE_SYS_EN_PCIE_DPA
NONE R/W1TS R/W1TS R/W1TS R/W1TS R/W1TS R/W1TS NONE R/W1TS
0 0 0 0 0 0 0

Access Types Legend

Table 12-2422 ENABLE_REG_SYS_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
11 ENABLE_SYS_EN_PCIE_PTM R/W1TS 0h Enable Set for sys_en_pcie_ptm
10 ENABLE_SYS_EN_PCIE_LINK_STATE R/W1TS 0h Enable Set for sys_en_pcie_link_state
9 ENABLE_SYS_EN_PCIE_HOT_RESET R/W1TS 0h Enable Set for sys_en_pcie_hot_reset
8 ENABLE_SYS_EN_PCIE_ERROR_2 R/W1TS 0h Enable Set for sys_en_pcie_error_2
7 ENABLE_SYS_EN_PCIE_ERROR_1 R/W1TS 0h Enable Set for sys_en_pcie_error_1
6 ENABLE_SYS_EN_PCIE_ERROR_0 R/W1TS 0h Enable Set for sys_en_pcie_error_0
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_DPA R/W1TS 0h Enable Set for sys_en_pcie_dpa

2.5.1.475 PCIE0_ENABLE_CLR_REG_SYS_0 Register (Offset = 300h) [reset = 0]

Short Description:

Long Description:

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Table 12-2423 Instance Table
Instance Name Base Address
PCIE0 0F10 2300h
Figure 12-1228 PCIE0_ENABLE_CLR_REG_SYS_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_DOWNSTREAM_CLR
NONE R/W1TC
0

Access Types Legend

Table 12-2424 ENABLE_CLR_REG_SYS_0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_DOWNSTREAM_CLR R/W1TC 0h Enable Clear for sys_en_pcie_downstream

2.5.1.476 PCIE0_ENABLE_CLR_REG_SYS_1 Register (Offset = 304h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2425 Instance Table
Instance Name Base Address
PCIE0 0F10 2304h
Figure 12-1229 PCIE0_ENABLE_CLR_REG_SYS_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED ENABLE_SYS_EN_PCIE_PWR_STATE_CLR ENABLE_SYS_EN_PCIE_LEGACY_3_CLR ENABLE_SYS_EN_PCIE_LEGACY_2_CLR ENABLE_SYS_EN_PCIE_LEGACY_1_CLR ENABLE_SYS_EN_PCIE_LEGACY_0_CLR RESERVED
NONE R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC NONE
0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_FLR_CLR
NONE R/W1TC
0

Access Types Legend

Table 12-2426 ENABLE_CLR_REG_SYS_1 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
26 ENABLE_SYS_EN_PCIE_PWR_STATE_CLR R/W1TC 0h Enable Clear for sys_en_pcie_pwr_state
25 ENABLE_SYS_EN_PCIE_LEGACY_3_CLR R/W1TC 0h Enable Clear for sys_en_pcie_legacy_3
24 ENABLE_SYS_EN_PCIE_LEGACY_2_CLR R/W1TC 0h Enable Clear for sys_en_pcie_legacy_2
23 ENABLE_SYS_EN_PCIE_LEGACY_1_CLR R/W1TC 0h Enable Clear for sys_en_pcie_legacy_1
22 ENABLE_SYS_EN_PCIE_LEGACY_0_CLR R/W1TC 0h Enable Clear for sys_en_pcie_legacy_0
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_FLR_CLR R/W1TC 0h Enable Clear for sys_en_pcie_flr

2.5.1.477 PCIE0_ENABLE_CLR_REG_SYS_2 Register (Offset = 308h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2427 Instance Table
Instance Name Base Address
PCIE0 0F10 2308h
Figure 12-1230 PCIE0_ENABLE_CLR_REG_SYS_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ENABLE_SYS_EN_PCIE_PTM_CLR ENABLE_SYS_EN_PCIE_LINK_STATE_CLR ENABLE_SYS_EN_PCIE_HOT_RESET_CLR ENABLE_SYS_EN_PCIE_ERROR_2_CLR ENABLE_SYS_EN_PCIE_ERROR_1_CLR ENABLE_SYS_EN_PCIE_ERROR_0_CLR RESERVED ENABLE_SYS_EN_PCIE_DPA_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC NONE R/W1TC
0 0 0 0 0 0 0

Access Types Legend

Table 12-2428 ENABLE_CLR_REG_SYS_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
11 ENABLE_SYS_EN_PCIE_PTM_CLR R/W1TC 0h Enable Clear for sys_en_pcie_ptm
10 ENABLE_SYS_EN_PCIE_LINK_STATE_CLR R/W1TC 0h Enable Clear for sys_en_pcie_link_state
9 ENABLE_SYS_EN_PCIE_HOT_RESET_CLR R/W1TC 0h Enable Clear for sys_en_pcie_hot_reset
8 ENABLE_SYS_EN_PCIE_ERROR_2_CLR R/W1TC 0h Enable Clear for sys_en_pcie_error_2
7 ENABLE_SYS_EN_PCIE_ERROR_1_CLR R/W1TC 0h Enable Clear for sys_en_pcie_error_1
6 ENABLE_SYS_EN_PCIE_ERROR_0_CLR R/W1TC 0h Enable Clear for sys_en_pcie_error_0
RESERVED NONE Reserved
0 ENABLE_SYS_EN_PCIE_DPA_CLR R/W1TC 0h Enable Clear for sys_en_pcie_dpa

2.5.1.478 PCIE0_STATUS_REG_SYS_0 Register (Offset = 500h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2429 Instance Table
Instance Name Base Address
PCIE0 0F10 2500h
Figure 12-1231 PCIE0_STATUS_REG_SYS_0 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STATUS_SYS_PCIE_DOWNSTREAM
NONE R
0

Access Types Legend

Table 12-2430 STATUS_REG_SYS_0 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 STATUS_SYS_PCIE_DOWNSTREAM R 0h Status for sys_en_pcie_downstream

2.5.1.479 PCIE0_STATUS_REG_SYS_1 Register (Offset = 504h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2431 Instance Table
Instance Name Base Address
PCIE0 0F10 2504h
Figure 12-1232 PCIE0_STATUS_REG_SYS_1 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED STATUS_SYS_PCIE_PWR_STATE STATUS_SYS_PCIE_LEGACY_3 STATUS_SYS_PCIE_LEGACY_2 STATUS_SYS_PCIE_LEGACY_1 STATUS_SYS_PCIE_LEGACY_0 RESERVED
NONE R R R R R NONE
0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STATUS_SYS_PCIE_FLR
NONE R
0

Access Types Legend

Table 12-2432 STATUS_REG_SYS_1 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
26 STATUS_SYS_PCIE_PWR_STATE R 0h Status for sys_en_pcie_pwr_state
25 STATUS_SYS_PCIE_LEGACY_3 R 0h Status for sys_en_pcie_legacy_3
24 STATUS_SYS_PCIE_LEGACY_2 R 0h Status for sys_en_pcie_legacy_2
23 STATUS_SYS_PCIE_LEGACY_1 R 0h Status for sys_en_pcie_legacy_1
22 STATUS_SYS_PCIE_LEGACY_0 R 0h Status for sys_en_pcie_legacy_0
RESERVED NONE Reserved
0 STATUS_SYS_PCIE_FLR R 0h Status for sys_en_pcie_flr

2.5.1.480 PCIE0_STATUS_REG_SYS_2 Register (Offset = 508h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2433 Instance Table
Instance Name Base Address
PCIE0 0F10 2508h
Figure 12-1233 PCIE0_STATUS_REG_SYS_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STATUS_SYS_PCIE_PTM STATUS_SYS_PCIE_LINK_STATE STATUS_SYS_PCIE_HOT_RESET STATUS_SYS_PCIE_ERROR_2 STATUS_SYS_PCIE_ERROR_1 STATUS_SYS_PCIE_ERROR_0 RESERVED STATUS_SYS_PCIE_DPA
NONE R/W1TS R/W1TS R/W1TS R/W1TS R/W1TS R/W1TS NONE R/W1TS
0 0 0 0 0 0 0

Access Types Legend

Table 12-2434 STATUS_REG_SYS_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
11 STATUS_SYS_PCIE_PTM R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_ptm
10 STATUS_SYS_PCIE_LINK_STATE R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_link_state
9 STATUS_SYS_PCIE_HOT_RESET R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_hot_reset
8 STATUS_SYS_PCIE_ERROR_2 R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_error_2
7 STATUS_SYS_PCIE_ERROR_1 R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_error_1
6 STATUS_SYS_PCIE_ERROR_0 R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_error_0
RESERVED NONE Reserved
0 STATUS_SYS_PCIE_DPA R/W1TS 0h Status ,write 1 to set, for sys_en_pcie_dpa

2.5.1.481 PCIE0_STATUS_CLR_REG_SYS_2 Register (Offset = 708h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2435 Instance Table
Instance Name Base Address
PCIE0 0F10 2708h
Figure 12-1234 PCIE0_STATUS_CLR_REG_SYS_2 Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STATUS_SYS_PCIE_PTM_CLR STATUS_SYS_PCIE_LINK_STATE_CLR STATUS_SYS_PCIE_HOT_RESET_CLR STATUS_SYS_PCIE_ERROR_2_CLR STATUS_SYS_PCIE_ERROR_1_CLR STATUS_SYS_PCIE_ERROR_0_CLR RESERVED STATUS_SYS_PCIE_DPA_CLR
NONE R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC R/W1TC NONE R/W1TC
0 0 0 0 0 0 0

Access Types Legend

Table 12-2436 STATUS_CLR_REG_SYS_2 Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
11 STATUS_SYS_PCIE_PTM_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_ptm
10 STATUS_SYS_PCIE_LINK_STATE_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_link_state
9 STATUS_SYS_PCIE_HOT_RESET_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_hot_reset
8 STATUS_SYS_PCIE_ERROR_2_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_error_2
7 STATUS_SYS_PCIE_ERROR_1_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_error_1
6 STATUS_SYS_PCIE_ERROR_0_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_error_0
RESERVED NONE Reserved
0 STATUS_SYS_PCIE_DPA_CLR R/W1TC 0h Status ,write 1 to clear, for sys_en_pcie_dpa

2.5.1.482 PCIE0_INTR_VECTOR_REG_SYS Register (Offset = A80h) [reset = 0]

Short Description:

Long Description:

Return to Summary Table

Table 12-2437 Instance Table
Instance Name Base Address
PCIE0 0F10 2A80h
Figure 12-1235 PCIE0_INTR_VECTOR_REG_SYS Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTR_VECTOR_SYS
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTR_VECTOR_SYS
R
0

Access Types Legend

Table 12-2438 INTR_VECTOR_REG_SYS Register Field Descriptions
Bit Field Type Reset Description
31 - 0 INTR_VECTOR_SYS R 0h Interrupt Vector

2.5.1.483 PCIE0_CPTS_IDVER_REG Register (Offset = 0h) [reset = 1317667084]

Short Description: idver_reg

Long Description:

Return to Summary Table

Table 12-2439 Instance Table
Instance Name Base Address
PCIE0 0F10 3000h
Figure 12-1236 PCIE0_IDVER_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TX_IDENT
R
100111010001010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTL_VER MAJOR_VER MINOR_VER
R R R
0 1 1100

Access Types Legend

Table 12-2440 CPTS_IDVER_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 16 TX_IDENT R 4E8Ah Identification value
15 - 11 RTL_VER R 0h RTL version value
10 - 8 MAJOR_VER R 1h Major version value
7 - 0 MINOR_VER R Ch Minor version value

2.5.1.484 PCIE0_CONTROL_REG Register (Offset = 4h) [reset = 4]

Short Description: control_reg

Long Description:

Return to Summary Table

Table 12-2441 Instance Table
Instance Name Base Address
PCIE0 0F10 3004h
Figure 12-1237 PCIE0_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_SYNC_SEL RESERVED TS_GENF_CLR_EN TS_RX_NO_EVENT
R/W NONE R/W R/W
0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HW8_TS_PUSH_EN HW7_TS_PUSH_EN HW6_TS_PUSH_EN HW5_TS_PUSH_EN HW4_TS_PUSH_EN HW3_TS_PUSH_EN HW2_TS_PUSH_EN HW1_TS_PUSH_EN TS_PPM_DIR TS_COMP_TOG MODE SEQUENCE_EN TSTAMP_EN TS_COMP_POLARITY INT_TEST CPTS_EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Access Types Legend

Table 12-2442 CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 28 TS_SYNC_SEL R/W 0h TS_SYNC output Timestamp counter bit select
RESERVED NONE Reserved
17 TS_GENF_CLR_EN R/W 0h Enable for GENF clear when length is zero
16 TS_RX_NO_EVENT R/W 0h Receive Produces no Events
15 HW8_TS_PUSH_EN R/W 0h Hardware push 8 enable
14 HW7_TS_PUSH_EN R/W 0h Hardware push 7 enable
13 HW6_TS_PUSH_EN R/W 0h Hardware push 6 enable
12 HW5_TS_PUSH_EN R/W 0h Hardware push 5 enable
11 HW4_TS_PUSH_EN R/W 0h Hardware push 4 enable
10 HW3_TS_PUSH_EN R/W 0h Hardware push 3 enable
9 HW2_TS_PUSH_EN R/W 0h Hardware push 2 enable
8 HW1_TS_PUSH_EN R/W 0h Hardware push 1 enable
7 TS_PPM_DIR R/W 0h Timestamp PPM Direction
6 TS_COMP_TOG R/W 0h Timestamp Compare Toggle mode: 0=TS_COMP is in non-toggle mode, 1=TS_COMP is in toggle mode
5 MODE R/W 0h Timestamp mode
4 SEQUENCE_EN R/W 0h Sequence Enable
3 TSTAMP_EN R/W 0h Host Receive Timestamp Enable
2 TS_COMP_POLARITY R/W 1h TS_COMP polarity
1 INT_TEST R/W 0h Interrupt test
0 CPTS_EN R/W 0h Time sync enable

2.5.1.485 PCIE0_RFTCLK_SEL_REG Register (Offset = 8h) [reset = 0]

Short Description: rftclk_sel_reg

Long Description:

Return to Summary Table

Table 12-2443 Instance Table
Instance Name Base Address
PCIE0 0F10 3008h
Figure 12-1238 PCIE0_RFTCLK_SEL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RFTCLK_SEL
NONE R/W
0

Access Types Legend

Table 12-2444 RFTCLK_SEL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
4 - 0 RFTCLK_SEL R/W 0h Reference clock select

2.5.1.486 PCIE0_TS_PUSH_REG Register (Offset = Ch) [reset = 0]

Short Description: ts_push_reg

Long Description:

Return to Summary Table

Table 12-2445 Instance Table
Instance Name Base Address
PCIE0 0F10 300Ch
Figure 12-1239 PCIE0_TS_PUSH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_PUSH
NONE W
0

Access Types Legend

Table 12-2446 TS_PUSH_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 TS_PUSH W 0h Time stamp event push

2.5.1.487 PCIE0_TS_LOAD_LOW_VAL_REG Register (Offset = 10h) [reset = 0]

Short Description: ts_load_low_val_reg

Long Description:

Return to Summary Table

Table 12-2447 Instance Table
Instance Name Base Address
PCIE0 0F10 3010h
Figure 12-1240 PCIE0_TS_LOAD_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_LOAD_VAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_LOAD_VAL
R/W
0

Access Types Legend

Table 12-2448 TS_LOAD_LOW_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_LOAD_VAL R/W 0h Time stamp load low value

2.5.1.488 PCIE0_TS_LOAD_EN_REG Register (Offset = 14h) [reset = 0]

Short Description: ts_load_en_reg

Long Description:

Return to Summary Table

Table 12-2449 Instance Table
Instance Name Base Address
PCIE0 0F10 3014h
Figure 12-1241 PCIE0_TS_LOAD_EN_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_LOAD_EN
NONE W
0

Access Types Legend

Table 12-2450 TS_LOAD_EN_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 TS_LOAD_EN W 0h Time stamp load enable

2.5.1.489 PCIE0_TS_COMP_LOW_VAL_REG Register (Offset = 18h) [reset = 0]

Short Description: ts_comp_low_val_reg

Long Description:

Return to Summary Table

Table 12-2451 Instance Table
Instance Name Base Address
PCIE0 0F10 3018h
Figure 12-1242 PCIE0_TS_COMP_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_COMP_VAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_COMP_VAL
R/W
0

Access Types Legend

Table 12-2452 TS_COMP_LOW_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_COMP_VAL R/W 0h Time stamp comparison low value

2.5.1.490 PCIE0_TS_COMP_LEN_REG Register (Offset = 1Ch) [reset = 0]

Short Description: ts_comp_len_reg

Long Description:

Return to Summary Table

Table 12-2453 Instance Table
Instance Name Base Address
PCIE0 0F10 301Ch
Figure 12-1243 PCIE0_TS_COMP_LEN_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_COMP_LENGTH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_COMP_LENGTH
R/W
0

Access Types Legend

Table 12-2454 TS_COMP_LEN_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_COMP_LENGTH R/W 0h Time stamp comparison length

2.5.1.491 PCIE0_INTSTAT_RAW_REG Register (Offset = 20h) [reset = 0]

Short Description: intstat_raw_reg

Long Description:

Return to Summary Table

Table 12-2455 Instance Table
Instance Name Base Address
PCIE0 0F10 3020h
Figure 12-1244 PCIE0_INTSTAT_RAW_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_PEND_RAW
NONE R/W
0

Access Types Legend

Table 12-2456 INTSTAT_RAW_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 TS_PEND_RAW R/W 0h TS_PEND_RAW int read (before enable)

2.5.1.492 PCIE0_INTSTAT_MASKED_REG Register (Offset = 24h) [reset = 0]

Short Description: intstat_masked_reg

Long Description:

Return to Summary Table

Table 12-2457 Instance Table
Instance Name Base Address
PCIE0 0F10 3024h
Figure 12-1245 PCIE0_INTSTAT_MASKED_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_PEND
NONE R
0

Access Types Legend

Table 12-2458 INTSTAT_MASKED_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 TS_PEND R 0h TS_PEND masked interrupt read (after enable)

2.5.1.493 PCIE0_INT_ENABLE_REG Register (Offset = 28h) [reset = 0]

Short Description: int_enable_reg

Long Description:

Return to Summary Table

Table 12-2459 Instance Table
Instance Name Base Address
PCIE0 0F10 3028h
Figure 12-1246 PCIE0_INT_ENABLE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_PEND_EN
NONE R/W
0

Access Types Legend

Table 12-2460 INT_ENABLE_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 TS_PEND_EN R/W 0h TS_PEND masked interrupt enable

2.5.1.494 PCIE0_TS_COMP_NUDGE_REG Register (Offset = 2Ch) [reset = 0]

Short Description: ts_comp_nudge_reg

Long Description:

Return to Summary Table

Table 12-2461 Instance Table
Instance Name Base Address
PCIE0 0F10 302Ch
Figure 12-1247 PCIE0_TS_COMP_NUDGE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUDGE
NONE R/W
0

Access Types Legend

Table 12-2462 TS_COMP_NUDGE_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 NUDGE R/W 0h This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount

2.5.1.495 PCIE0_EVENT_POP_REG Register (Offset = 30h) [reset = 0]

Short Description: event_pop_reg

Long Description:

Return to Summary Table

Table 12-2463 Instance Table
Instance Name Base Address
PCIE0 0F10 3030h
Figure 12-1248 PCIE0_EVENT_POP_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED EVENT_POP
NONE W
0

Access Types Legend

Table 12-2464 EVENT_POP_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
0 EVENT_POP W 0h Event pop

2.5.1.496 PCIE0_EVENT_0_REG Register (Offset = 34h) [reset = 0]

Short Description: event_0_reg

Long Description:

Return to Summary Table

Table 12-2465 Instance Table
Instance Name Base Address
PCIE0 0F10 3034h
Figure 12-1249 PCIE0_EVENT_0_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME_STAMP
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME_STAMP
R
0

Access Types Legend

Table 12-2466 EVENT_0_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TIME_STAMP R 0h Time Stamp

2.5.1.497 PCIE0_EVENT_1_REG Register (Offset = 38h) [reset = 0]

Short Description: event_1_reg

Long Description:

Return to Summary Table

Table 12-2467 Instance Table
Instance Name Base Address
PCIE0 0F10 3038h
Figure 12-1250 PCIE0_EVENT_1_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED PREMPT_QUEUE PORT_NUMBER EVENT_TYPE MESSAGE_TYPE
NONE R R R R
0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEQUENCE_ID
R
0

Access Types Legend

Table 12-2468 EVENT_1_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
29 PREMPT_QUEUE R 0h Prempt QUEUE
28 - 24 PORT_NUMBER R 0h Port number
23 - 20 EVENT_TYPE R 0h Event type
19 - 16 MESSAGE_TYPE R 0h Message type
15 - 0 SEQUENCE_ID R 0h Sequence ID

2.5.1.498 PCIE0_EVENT_2_REG Register (Offset = 3Ch) [reset = 0]

Short Description: event_2_reg

Long Description:

Return to Summary Table

Table 12-2469 Instance Table
Instance Name Base Address
PCIE0 0F10 303Ch
Figure 12-1251 PCIE0_EVENT_2_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DOMAIN
NONE R
0

Access Types Legend

Table 12-2470 EVENT_2_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 DOMAIN R 0h Domain

2.5.1.499 PCIE0_EVENT_3_REG Register (Offset = 40h) [reset = 0]

Short Description: event_3_reg

Long Description:

Return to Summary Table

Table 12-2471 Instance Table
Instance Name Base Address
PCIE0 0F10 3040h
Figure 12-1252 PCIE0_EVENT_3_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIME_STAMP
R
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME_STAMP
R
0

Access Types Legend

Table 12-2472 EVENT_3_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TIME_STAMP R 0h Time Stamp

2.5.1.500 PCIE0_TS_LOAD_HIGH_VAL_REG Register (Offset = 44h) [reset = 0]

Short Description: ts_load_high_val_reg

Long Description:

Return to Summary Table

Table 12-2473 Instance Table
Instance Name Base Address
PCIE0 0F10 3044h
Figure 12-1253 PCIE0_TS_LOAD_HIGH_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_LOAD_VAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_LOAD_VAL
R/W
0

Access Types Legend

Table 12-2474 TS_LOAD_HIGH_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_LOAD_VAL R/W 0h Time stamp load high value

2.5.1.501 PCIE0_TS_COMP_HIGH_VAL_REG Register (Offset = 48h) [reset = 0]

Short Description: ts_comp_high_val_reg

Long Description:

Return to Summary Table

Table 12-2475 Instance Table
Instance Name Base Address
PCIE0 0F10 3048h
Figure 12-1254 PCIE0_TS_COMP_HIGH_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_COMP_HIGH_VAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_COMP_HIGH_VAL
R/W
0

Access Types Legend

Table 12-2476 TS_COMP_HIGH_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_COMP_HIGH_VAL R/W 0h Time stamp comparison high value

2.5.1.502 PCIE0_TS_ADD_VAL_REG Register (Offset = 4Ch) [reset = 0]

Short Description: ts_add_val

Long Description:

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Table 12-2477 Instance Table
Instance Name Base Address
PCIE0 0F10 304Ch
Figure 12-1255 PCIE0_TS_ADD_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED ADD_VAL
NONE R/W
0

Access Types Legend

Table 12-2478 TS_ADD_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
2 - 0 ADD_VAL R/W 0h Add Value

2.5.1.503 PCIE0_TS_PPM_LOW_VAL_REG Register (Offset = 50h) [reset = 0]

Short Description: ts_ppm_low_val_reg

Long Description:

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Table 12-2479 Instance Table
Instance Name Base Address
PCIE0 0F10 3050h
Figure 12-1256 PCIE0_TS_PPM_LOW_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_PPM_LOW_VAL
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_PPM_LOW_VAL
R/W
0

Access Types Legend

Table 12-2480 TS_PPM_LOW_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 TS_PPM_LOW_VAL R/W 0h Time stamp PPM Low value

2.5.1.504 PCIE0_TS_PPM_HIGH_VAL_REG Register (Offset = 54h) [reset = 0]

Short Description: ts_ppm_high_val_reg

Long Description:

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Table 12-2481 Instance Table
Instance Name Base Address
PCIE0 0F10 3054h
Figure 12-1257 PCIE0_TS_PPM_HIGH_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_PPM_HIGH_VAL
NONE R/W
0

Access Types Legend

Table 12-2482 TS_PPM_HIGH_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
9 - 0 TS_PPM_HIGH_VAL R/W 0h Time stamp PPM High value

2.5.1.505 PCIE0_TS_NUDGE_VAL_REG Register (Offset = 58h) [reset = 0]

Short Description: ts_nudge_val_reg

Long Description:

Return to Summary Table

Table 12-2483 Instance Table
Instance Name Base Address
PCIE0 0F10 3058h
Figure 12-1258 PCIE0_TS_NUDGE_VAL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TS_NUDGE_VAL
NONE R/W
0

Access Types Legend

Table 12-2484 TS_NUDGE_VAL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 TS_NUDGE_VAL R/W 0h Time stamp Nudge value

2.5.1.506 PCIE0_TS_CONFIG Register (Offset = D0h) [reset = 8193]

Short Description: ts_config

Long Description:

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Table 12-2485 Instance Table
Instance Name Base Address
PCIE0 0F10 30D0h
Figure 12-1259 PCIE0_TS_CONFIG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVNT_FIFO_DEPTH NUM_GENF
R R
100000 1

Access Types Legend

Table 12-2486 TS_CONFIG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
15 - 8 EVNT_FIFO_DEPTH R 20h The Event FIFO Depth
7 - 0 NUM_GENF R 1h The number of CPTS GENF outputs

2.5.1.507 PCIE0_COMP_LOW_REG Register (Offset = E0h) [reset = 0]

Short Description: comp_low_reg

Long Description:

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Table 12-2487 Instance Table
Instance Name Base Address
PCIE0 0F10 30E0h
Figure 12-1260 PCIE0_TS_GENF_COMP_LOW_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP_LOW
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_LOW
R/W
0

Access Types Legend

Table 12-2488 COMP_LOW_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 COMP_LOW R/W 0h Time Stamp Generate Function Comparison Low Value

2.5.1.508 PCIE0_COMP_HIGH_REG Register (Offset = E4h) [reset = 0]

Short Description: comp_high_reg

Long Description:

Return to Summary Table

Table 12-2489 Instance Table
Instance Name Base Address
PCIE0 0F10 30E4h
Figure 12-1261 PCIE0_TS_GENF_COMP_HIGH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP_HIGH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_HIGH
R/W
0

Access Types Legend

Table 12-2490 COMP_HIGH_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 COMP_HIGH R/W 0h Time Stamp Generate Function Comparison High Value

2.5.1.509 PCIE0_CONTROL_REG Register (Offset = E8h) [reset = 0]

Short Description: control_reg

Long Description:

Return to Summary Table

Table 12-2491 Instance Table
Instance Name Base Address
PCIE0 0F10 30E8h
Figure 12-1262 PCIE0_TS_GENF_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED POLARITY_INV PPM_DIR
NONE R/W R/W
0 0

Access Types Legend

Table 12-2492 CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 POLARITY_INV R/W 0h Time Stamp Generate Function Polarity Invert
0 PPM_DIR R/W 0h Time Stamp Generate Function PPM Direction

2.5.1.510 PCIE0_LENGTH_REG Register (Offset = ECh) [reset = 0]

Short Description: length_reg

Long Description:

Return to Summary Table

Table 12-2493 Instance Table
Instance Name Base Address
PCIE0 0F10 30ECh
Figure 12-1263 PCIE0_TS_GENF_LENGTH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENGTH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENGTH
R/W
0

Access Types Legend

Table 12-2494 LENGTH_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 LENGTH R/W 0h Time Stamp Generate Function Length Value

2.5.1.511 PCIE0_PPM_LOW_REG Register (Offset = F0h) [reset = 0]

Short Description: ppm_low_reg

Long Description:

Return to Summary Table

Table 12-2495 Instance Table
Instance Name Base Address
PCIE0 0F10 30F0h
Figure 12-1264 PCIE0_TS_GENF_PPM_LOW_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPM_LOW
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPM_LOW
R/W
0

Access Types Legend

Table 12-2496 PPM_LOW_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PPM_LOW R/W 0h Time Stamp Generate Function PPM Low Value

2.5.1.512 PCIE0_PPM_HIGH_REG Register (Offset = F4h) [reset = 0]

Short Description: ppm_high_reg

Long Description:

Return to Summary Table

Table 12-2497 Instance Table
Instance Name Base Address
PCIE0 0F10 30F4h
Figure 12-1265 PCIE0_TS_GENF_PPM_HIGH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PPM_HIGH
NONE R/W
0

Access Types Legend

Table 12-2498 PPM_HIGH_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
9 - 0 PPM_HIGH R/W 0h Time Stamp Generate Function PPM High Value

2.5.1.513 PCIE0_NUDGE_REG Register (Offset = F8h) [reset = 0]

Short Description: nudge_reg

Long Description:

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Table 12-2499 Instance Table
Instance Name Base Address
PCIE0 0F10 30F8h
Figure 12-1266 PCIE0_TS_GENF_NUDGE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUDGE
NONE R/W
0

Access Types Legend

Table 12-2500 NUDGE_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 NUDGE R/W 0h Time Stamp Generate Function Nudge Value

2.5.1.514 PCIE0_COMP_LOW_REG Register (Offset = 200h) [reset = 0]

Short Description: comp_low_reg

Long Description:

Return to Summary Table

Table 12-2501 Instance Table
Instance Name Base Address
PCIE0 0F10 3200h
Figure 12-1267 PCIE0_TS_ESTF_COMP_LOW_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP_LOW
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_LOW
R/W
0

Access Types Legend

Table 12-2502 COMP_LOW_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 COMP_LOW R/W 0h Time Stamp ESTF Generate Function Comparison Low Value

2.5.1.515 PCIE0_COMP_HIGH_REG Register (Offset = 204h) [reset = 0]

Short Description: comp_high_reg

Long Description:

Return to Summary Table

Table 12-2503 Instance Table
Instance Name Base Address
PCIE0 0F10 3204h
Figure 12-1268 PCIE0_TS_ESTF_COMP_HIGH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP_HIGH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_HIGH
R/W
0

Access Types Legend

Table 12-2504 COMP_HIGH_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 COMP_HIGH R/W 0h Time Stamp ESTF Generate Function Comparison High Value

2.5.1.516 PCIE0_CONTROL_REG Register (Offset = 208h) [reset = 0]

Short Description: control_reg

Long Description:

Return to Summary Table

Table 12-2505 Instance Table
Instance Name Base Address
PCIE0 0F10 3208h
Figure 12-1269 PCIE0_TS_ESTF_CONTROL_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED POLARITY_INV PPM_DIR
NONE R/W R/W
0 0

Access Types Legend

Table 12-2506 CONTROL_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
1 POLARITY_INV R/W 0h Time Stamp ESTF Generate Function Polarity Invert
0 PPM_DIR R/W 0h Time Stamp ESTF Generate Function PPM Direction

2.5.1.517 PCIE0_LENGTH_REG Register (Offset = 20Ch) [reset = 0]

Short Description: length_reg

Long Description:

Return to Summary Table

Table 12-2507 Instance Table
Instance Name Base Address
PCIE0 0F10 320Ch
Figure 12-1270 PCIE0_TS_ESTF_LENGTH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENGTH
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENGTH
R/W
0

Access Types Legend

Table 12-2508 LENGTH_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 LENGTH R/W 0h Time Stamp ESTF Generate Function Length Value

2.5.1.518 PCIE0_PPM_LOW_REG Register (Offset = 210h) [reset = 0]

Short Description: ppm_low_reg

Long Description:

Return to Summary Table

Table 12-2509 Instance Table
Instance Name Base Address
PCIE0 0F10 3210h
Figure 12-1271 PCIE0_TS_ESTF_PPM_LOW_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPM_LOW
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPM_LOW
R/W
0

Access Types Legend

Table 12-2510 PPM_LOW_REG Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PPM_LOW R/W 0h Time Stamp ESTF Generate Function PPM Low Value

2.5.1.519 PCIE0_PPM_HIGH_REG Register (Offset = 214h) [reset = 0]

Short Description: ppm_high_reg

Long Description:

Return to Summary Table

Table 12-2511 Instance Table
Instance Name Base Address
PCIE0 0F10 3214h
Figure 12-1272 PCIE0_TS_ESTF_PPM_HIGH_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PPM_HIGH
NONE R/W
0

Access Types Legend

Table 12-2512 PPM_HIGH_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
9 - 0 PPM_HIGH R/W 0h Time Stamp ESTF Generate Function PPM High Value

2.5.1.520 PCIE0_NUDGE_REG Register (Offset = 218h) [reset = 0]

Short Description: nudge_reg

Long Description:

Return to Summary Table

Table 12-2513 Instance Table
Instance Name Base Address
PCIE0 0F10 3218h
Figure 12-1273 PCIE0_TS_ESTF_NUDGE_REG Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
NONE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NUDGE
NONE R/W
0

Access Types Legend

Table 12-2514 NUDGE_REG Register Field Descriptions
Bit Field Type Reset Description
RESERVED NONE Reserved
7 - 0 NUDGE R/W 0h Time Stamp ESTF Generate Function Nudge Value

2.5.1.521 PCIE0_PCIE_DATA_MEM Register (Offset = 0h) [reset = 0]

Short Description: PCIe data region0

Long Description:

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Table 12-2515 Instance Table
Instance Name Base Address
PCIE0 6800 0000h
Figure 12-1274 PCIE0_PCIE_DATA_MEM Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_DATA
R/W
0

Access Types Legend

Table 12-2516 PCIE_DATA_MEM Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PCIE_DATA R/W 0h PCIE data region0

2.5.1.522 PCIE0_PCIE_DATA_MEM Register (Offset = 0h) [reset = 0]

Short Description: PCIe data region1

Long Description:

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Table 12-2517 Instance Table
Instance Name Base Address
PCIE0 0006 0000 0000h
Figure 12-1275 PCIE0_PCIE_DATA_MEM Name Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_DATA
R/W
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_DATA
R/W
0

Access Types Legend

Table 12-2518 PCIE_DATA_MEM Register Field Descriptions
Bit Field Type Reset Description
31 - 0 PCIE_DATA R/W 0h PCIE data region1
Table 12-2519 Access Type Codes
Access Type Code Description
R R Read
R/W1TC R/W1TC Read/Write 1 To Clear
R/W R/W Read / Write
R/W1TS R/W1TS Read/Write 1 To Set
R/WI R/WI Read/Write Increment. A write to this bit field increments the specified register bit field by the amount written.
R/WD R/WD Read/Write Decrement. A write to this bit field decrements the specified register bit field by the amount written.
W W Write