SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-1370 lists the memory-mapped registers for the PRU_MII_G_RT_MII_G_RT registers. All register offset addresses not listed in Table 6-1370 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3000h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3000h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G Physical Address | PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G Physical Address |
---|---|---|---|---|
0h | MII_G_RT_ICSS_G_CFG | ICSSG Configuration Register | 3003 3000h | 300B 3000h |
4h | MII_G_RT_RGMII_CFG | RGMII Configuration Register | 3003 3004h | 300B 3004h |
8h | MII_G_RT_MAC_PRU0_0 | PRU0 MAC (DA3:DA0) | 3003 3008h | 300B 3008h |
Ch | MII_G_RT_MAC_PRU0_1 | PRU0 MAC (DA5:DA4) | 3003 300Ch | 300B 300Ch |
10h | MII_G_RT_MAC_PRU1_0 | PRU1 MAC (DA3:DA0) | 3003 3010h | 300B 3010h |
14h | MII_G_RT_MAC_PRU1_1 | PRU0 MAC (DA5:DA4) | 3003 3014h | 300B 3014h |
18h | MII_G_RT_MAC_INTERFACE_0 | MAC Host Interface (DA3:DA0) | 3003 3018h | 300B 3018h |
1Ch | MII_G_RT_MAC_INTERFACE_1 | MAC Host Interface (DA5:DA4) | 3003 301Ch | 300B 301Ch |
20h | MII_G_RT_PREEMPT_CFG | Preempt Configuration Register | 3003 3020h | 300B 3020h |
24h | MII_G_RT_SMDT1S_CFG | SMD Type1S Preemptable Frame Start Configuration | 3003 3024h | 300B 3024h |
28h | MII_G_RT_SMDT1C_CFG | SMD Type1C None Initial Frag Configuration | 3003 3028h | 300B 3028h |
34h | MII_G_RT_FRAG_CNT_CFG | Frag Count Configuration | 3003 3034h | 300B 3034h |
40h | MII_G_RT_PA_STAT_PUSH0 | Pa Stat Push0 | 3003 3040h | 300B 3040h |
44h | MII_G_RT_PA_STAT_PUSH1 | Pa Stat Push1 | 3003 3044h | 300B 3044h |
48h | MII_G_RT_PA_STAT_PUSH2 | Pa Stat Push2 | 3003 3048h | 300B 3048h |
4Ch | MII_G_RT_PA_STAT_PUSH3 | Pa Stat Push3 | 3003 304Ch | 300B 304Ch |
60h | MII_G_RT_FDB_GEN_CFG1 | FDB Configuration1 | 3003 3060h | 300B 3060h |
64h | MII_G_RT_FDB_GEN_CFG2 | FDB Configuration2 | 3003 3064h | 300B 3064h |
6Ch | MII_G_RT_FDB_DF_VLAN | FDB Default PRU VLAN | 3003 306Ch | 300B 306Ch |
70h | MII_G_RT_FDB_HOST_DA0 | FDB HOST DA3:0 Configuration | 3003 3070h | 300B 3070h |
74h | MII_G_RT_FDB_HOST_DA1 | FDB HOST DA5:4 Configuration | 3003 3074h | 300B 3074h |
78h | MII_G_RT_FDB_HOST_SA0 | FDB HOST SA3:0 Configuration | 3003 3078h | 300B 3078h |
7Ch | MII_G_RT_FDB_HOST_VLAN_SA1 | FDB HOST VLAN SA5:4 Configuration | 3003 307Ch | 300B 307Ch |
80h | MII_G_RT_FT1_START_LEN_PRU0 | Filter1 Start and Length (PRU0) | 3003 3080h | 300B 3080h |
84h | MII_G_RT_FT1_CFG_PRU0 | Filter1 Configuration (PRU0) | 3003 3084h | 300B 3084h |
88h + formula | MII_G_RT_FT1_k_DA0_PRU0 | Filter1<k> DA0 (PRU0) | 3003 3088h + formula | 300B 3088h + formula |
8Ch + formula | MII_G_RT_FT1_k_DA1_PRU0 | Filter1<k> DA1 (PRU0) | 3003 308Ch + formula | 300B 308Ch + formula |
90h + formula | MII_G_RT_FT1_k_DA_MASK0_PRU0 | Filter1<k> DA0 Mask (PRU0) | 3003 3090h + formula | 300B 3090h + formula |
94h + formula | MII_G_RT_FT1_k_DA_MASK1_PRU0 | Filter1<k> DA1 Mask (PRU0) | 3003 3094h + formula | 300B 3094h + formula |
108h + formula | MII_G_RT_FT3_m_START_PRU0 | Filter3 Byte Count Start for PRU0 | 3003 3108h + formula | 300B 3108h + formula |
10Ch + formula | MII_G_RT_FT3_m_START_AUTO_PRU0 | Filter3 Byte Count Start for Auto Skip mode | 3003 310Ch + formula | 300B 310Ch + formula |
110h + formula | MII_G_RT_FT3_m_START_LEN_PRU0 | Filter3 Start Offset for PRU0 | 3003 3110h + formula | 300B 3110h + formula |
114h + formula | MII_G_RT_FT3_m_JMP_OFFSET_PRU0 | Filter3 Jump Offset for PRU0for PRU0 | 3003 3114h + formula | 300B 3114h + formula |
118h + formula | MII_G_RT_FT3_m_LEN_PRU0 | Filter3 Length Offset for PRU0 | 3003 3118h + formula | 300B 3118h + formula |
11Ch + formula | MII_G_RT_FT3_m_CFG_PRU0 | Filter3 Configuration for PRU0 | 3003 311Ch + formula | 300B 311Ch + formula |
120h + formula | MII_G_RT_FT3_m_T_PRU0 | Filter3 Type for PRU0 | 3003 3120h + formula | 300B 3120h + formula |
124h + formula | MII_G_RT_FT3_m_T_MASK_PRU0 | Filter3 Mask for PRU0 | 3003 3124h + formula | 300B 3124h + formula |
308h + formula | MII_G_RT_FT3_m_P0_PRU0 | Filter3 PRU0 (P4:P1) | 3003 3308h + formula | 300B 3308h + formula |
30Ch + formula | MII_G_RT_FT3_m_P1_PRU0 | Filter3 PRU0 (P8:P5) | 3003 330Ch + formula | 300B 330Ch + formula |
310h + formula | MII_G_RT_FT3_n_P_MASK0_PRU0 | Filter3 Mask0 (MP4:MP1) | 3003 3310h + formula | 300B 3310h + formula |
314h + formula | MII_G_RT_FT3_n_P_MASK1_PRU0 | Filter3 Mask1 (MP8:MP5) | 3003 3314h + formula | 300B 3314h + formula |
408h | MII_G_RT_FT_RX_PTR_PRU0 | RX Current Filter Byte Count (PRU0) | 3003 3408h | 300B 3408h |
40Ch + formula | MII_G_RT_RX_CLASSm_AND_EN_PRU0 | RX Class AND Enable Register | 3003 340Ch + formula | 300B 340Ch + formula |
410h + formula | MII_G_RT_RX_CLASSm_OR_EN_PRU0 | RX Class OR Enable Register | 3003 3410h | 300B 3410h |
48Ch | MII_G_RT_RX_CLASS_CFG1_PRU0 | RX Class Configuration 1 Register | 3003 348Ch | 300B 348Ch |
490h | MII_G_RT_RX_CLASS_CFG2_PRU0 | RX Class Configuration 2 Register | 3003 3490h | 300B 3490h |
494h + formula | MII_G_RT_RX_CLASS_GATESm_PRU0 | RX Class Gate Configuration PRU0 Register | 3003 3494h + formula | 300B 3494h + formula |
4D4h | MII_G_RT_RX_GREEN_PRU0 | RX Green Status PRU0 | 3003 34D4h | 300B 34D4h |
4D8h | MII_G_RT_SA_HASH_PRU0 | SA Hash Seed PRU0 | 3003 34D8h | 300B 34D8h |
4DCh | MII_G_RT_CONN_HASH_PRU0 | Connection Hash Seed PRU0 | 3003 34DCh | 300B 34DCh |
4E0h | MII_G_RT_CONN_HASH_START_PRU0 | Connection Hash Start PRU0 | 3003 34E0h | 300B 34E0h |
4E4h + formula | MII_G_RT_RX_RATE_CFGn_PRU0 | RX Rate Configuration Register | 3003 34E4h + formula | 300B 34E4h + formula |
504h | MII_G_RT_RX_RATE_SRC_SEL0_PRU0 | RX Rate Source Select0 | 3003 3504h | 300B 3504h |
508h | MII_G_RT_RX_RATE_SRC_SEL1_PRU0 | RX Rate Source Select1 | 3003 3508h | 300B 3508h |
50Ch + formula | MII_G_RT_TX_RATE_CFG1_n_PRU0 | TX Rate Configuration1 Register | 3003 350Ch + formula | 300B 350Ch + formula |
510h + formula | MII_G_RT_TX_RATE_CFG2_n_PRU0 | TX Rate Configuration2 Register | 3003 3510h + formula | 300B 3510h + formula |
54Ch | MII_G_RT_RX_STAT_GOOD_PRU0 | RX Good Frame Count (PRU0) | 3003 354Ch | 300B 354Ch |
550h | MII_G_RT_RX_STAT_BC_PRU0 | RX BC Frame Count (PRU0) | 3003 3550h | 300B 3550h |
554h | MII_G_RT_RX_STAT_MC_PRU0 | RX MC Frame Count (PRU0) | 3003 3554h | 300B 3554h |
558h | MII_G_RT_RX_STAT_CRC_ERR_PRU0 | RX CRC Error Frame Count (PRU0) | 3003 3558h | 300B 3558h |
55Ch | MII_G_RT_RX_STAT_MII_ERR_PRU0 | RX MII Error Frame Count (PRU0) | 3003 355Ch | 300B 355Ch |
560h | MII_G_RT_RX_STAT_ODD_ERR_PRU0 | RX Odd Nibble Frame Count (PRU0) | 3003 3560h | 300B 3560h |
564h | MII_G_RT_RX_STAT_MAX_SIZE_PRU0 | RX Max Size Frame Count (PRU0) | 3003 3564h | 300B 3564h |
568h | MII_G_RT_RX_STAT_MAX_ERR_PRU0 | RX Max Size Error Frame Count (PRU0) | 3003 3568h | 300B 3568h |
56Ch | MII_G_RT_RX_STAT_MIN_SIZE_PRU0 | RX Min Size Frame Count (PRU0) | 3003 356Ch | 300B 356Ch |
570h | MII_G_RT_RX_STAT_MIN_ERR_PRU0 | RX Min Size Error Frame Count (PRU0) | 3003 3570h | 300B 3570h |
574h | MII_G_RT_RX_STAT_OVERRUN_ERR_PRU0 | RX Overrun Frame Count (PRU0) | 3003 3574h | 300B 3574h |
578h + formula | MII_G_RT_RX_STAT_CLASSm_HIT_PRU0 | RX Class<m> Hit | 3003 3578h + formula | 300B 3578h + formula |
5B8h | MII_G_RT_RX_STAT_SMD_FRAG_ERR_PRU0 | RX SMD Frag Error Count (PRU0) | 3003 35B8h | 300B 35B8h |
5BCh | MII_G_RT_RX_STAT_BKT1_SIZE_PRU0 | RX Bucket1 Size Configuration (PRU0) | 3003 35BCh | 300B 35BCh |
5C0h | MII_G_RT_RX_STAT_BKT2_SIZE_PRU0 | RX Bucket2 Size Configuration (PRU0) | 3003 35C0h | 300B 35C0h |
5C4h | MII_G_RT_RX_STAT_BKT3_SIZE_PRU0 | RX Bucket3 Size Configuration (PRU0) | 3003 35C4h | 300B 35C4h |
5C8h | MII_G_RT_RX_STAT_BKT4_SIZE_PRU0 | RX Bucket4 Size Configuration (PRU0) | 3003 35C8h | 300B 35C8h |
5CCh | MII_G_RT_RX_STAT_64_PRU0 | RX 64B Sized Frame Count (PRU0) | 3003 35CCh | 300B 35CCh |
5D0h | MII_G_RT_RX_STAT_BKT1_PRU0 | RX Bucket1 Sized Frame Count (PRU0) | 3003 35D0h | 300B 35D0h |
5D4h | MII_G_RT_RX_STAT_BKT2_PRU0 | RX Bucket2 Sized Frame Count (PRU0) | 3003 35D4h | 300B 35D4h |
5D8h | MII_G_RT_RX_STAT_BKT3_PRU0 | RX Bucket3 Sized Frame Count (PRU0) | 3003 35D8h | 300B 35D8h |
5DCh | MII_G_RT_RX_STAT_BKT4_PRU0 | RX Bucket4 Sized Frame Count (PRU0) | 3003 35DCh | 300B 35DCh |
5E0h | MII_G_RT_RX_STAT_BKT5_PRU0 | RX Bucket5 Sized Frame Count (PRU0) | 3003 35E0h | 300B 35E0h |
5E4h | MII_G_RT_RX_STAT_TOTAL_BYTES_PRU0 | RX Total Byte Count (PRU0) | 3003 35E4h | 300B 35E4h |
5E8h | MII_G_RT_RXTX_STAT_TOTAL_BYTES_PRU0 | RX TX Total Byte Count (PRU0) | 3003 35E8h | 300B 35E8h |
5ECh | MII_G_RT_TX_STAT_GOOD_PORT0 | TX Good Frame Count Port0 | 3003 35ECh | 300B 35ECh |
5F0h | MII_G_RT_TX_STAT_BC_PORT0 | TX BC Frame Count Port0 | 3003 35F0h | 300B 35F0h |
5F4h | MII_G_RT_TX_STAT_MC_PORT0 | TX MC Frame Count Port0 | 3003 35F4h | 300B 35F4h |
5F8h | MII_G_RT_TX_STAT_ODD_ERR_PORT0 | TX Odd Nibble Frame Count Port0 | 3003 35F8h | 300B 35F8h |
5FCh | MII_G_RT_TX_STAT_UNDERFLOW_ERR_PORT0 | TX Under Flow Error Count Port0 | 3003 35FCh | 300B 35FCh |
600h | MII_G_RT_TX_STAT_MAX_SIZE_PORT0 | TX Max Size Frame Port0 | 3003 3600h | 300B 3600h |
604h | MII_G_RT_TX_STAT_MAX_ERR_PORT0 | TX Max Size Error Frame Count Port0 | 3003 3604h | 300B 3604h |
608h | MII_G_RT_TX_STAT_MIN_SIZE_PORT0 | TX Min Size Frame Port0 | 3003 3608h | 300B 3608h |
60Ch | MII_G_RT_TX_STAT_MIN_ERR_PORT0 | TX Min Size ErrorFrame Count Port0 | 3003 360Ch | 300B 360Ch |
610h | MII_G_RT_TX_STAT_BKT1_SIZE_PORT0 | TX Bucket1 Size Configuration Port0 | 3003 3610h | 300B 3610h |
614h | MII_G_RT_TX_STAT_BKT2_SIZE_PORT0 | TX Bucket2 Size Configuration Port0 | 3003 3614h | 300B 3614h |
618h | MII_G_RT_TX_STAT_BKT3_SIZE_PORT0 | TX Bucket3 Size Configuration Port0 | 3003 3618h | 300B 3618h |
61Ch | MII_G_RT_TX_STAT_BKT4_SIZE_PORT0 | TX Bucket4 Size Configuration Port0 | 3003 361Ch | 300B 361Ch |
620h | MII_G_RT_TX_STAT_64_PORT0 | TX 64B Sized Frame Count Port0 | 3003 3620h | 300B 3620h |
624h | MII_G_RT_TX_STAT_BKT1_PORT0 | TX Bucket1 Sized Frame Count Port0 | 3003 3624h | 300B 3624h |
628h | MII_G_RT_TX_STAT_BKT2_PORT0 | TX Bucket2 Sized Frame Count Port0 | 3003 3628h | 300B 3628h |
62Ch | MII_G_RT_TX_STAT_BKT3_PORT0 | TX Bucket3 Sized Frame Count Port0 | 3003 362Ch | 300B 362Ch |
630h | MII_G_RT_TX_STAT_BKT4_PORT0 | TX Bucket4 Sized Frame Count Port0 | 3003 3630h | 300B 3630h |
634h | MII_G_RT_TX_STAT_BKT5_PORT0 | TX Bucket5 Sized Frame Count Port0 | 3003 3634h | 300B 3634h |
638h | MII_G_RT_TX_STAT_TOTAL_BYTES_PORT0 | TX Total Byte Count Port0 | 3003 3638h | 300B 3638h |
63Ch | MII_G_RT_TX_HSR_TAG_PORT0 | TX HSR TAG Port0 | 3003 363Ch | 300B 363Ch |
640h | MII_G_RT_TX_HSR_SEQ_PORT0 | TX HSR Seq Port0 | 3003 3640h | 300B 3640h |
644h | MII_G_RT_TX_VLAN_TYPE_TAG_PORT0 | TX VLAN Type TAG Port0 | 3003 3644h | 300B 3644h |
648h | MII_G_RT_TX_VLAN_INS_TAG_PORT0 | TX VLAN Insertion TAG Port0 | 3003 3648h | 300B 3648h |
64Ch | MII_G_RT_FT1_START_LEN_PRU1 | Filter1 Start and Length (PRU1) | 3003 364Ch | 300B 364Ch |
650h | MII_G_RT_FT1_CFG_PRU1 | Filter1 Configuration (PRU1) | 3003 3650h | 300B 3650h |
654h + formula | MII_G_RT_FT1_k_DA0_PRU1 | Filter1<k> DA0 (PRU1) | 3003 3654h + formula | 300B 3654h + formula |
658h + formula | MII_G_RT_FT1_k_DA1_PRU1 | Filter1<k> DA1 (PRU1) | 3003 3658h + formula | 300B 3658h + formula |
65Ch + formula | MII_G_RT_FT1_k_DA_MASK0_PRU1 | Filter1<k> DA0 Mask (PRU1) | 3003 365Ch + formula | 300B 365Ch + formula |
660h + formula | MII_G_RT_FT1_k_DA_MASK1_PRU1 | Filter1<k> DA1 Mask (PRU1) | 3003 3660h + formula | 300B 3660h + formula |
6D4h + formula | MII_G_RT_FT3_m_START_PRU1 | Filter3<m> Start (PRU1) | 3003 36D4h + formula | 300B 36D4h + formula |
6D8h + formula | MII_G_RT_FT3_m_START_AUTO_PRU1 | Filter3<m> Start Auto (PRU1) | 3003 36D8h + formula | 300B 36D8h + formula |
6DCh + formula | MII_G_RT_FT3_m_START_LEN_PRU1 | Filter3<m> Start offset (PRU1) | 3003 36DCh + formula | 300B 36DCh + formula |
6E0h + formula | MII_G_RT_FT3_m_JMP_OFFSET_PRU1 | Filter3<m> Jmp offset (PRU1) | 3003 36E0h + formula | 300B 36E0h + formula |
6E4h + formula | MII_G_RT_FT3_m_LEN_PRU1 | Filter3 Length Offset for (PRU1) | 3003 36E4h + formula | 300B 36E4h + formula |
6E8h + formula | MII_G_RT_FT3_m_CFG_PRU1 | Filter3<m> Configuration (PRU1) | 3003 36E8h + formula | 300B 36E8h + formula |
6ECh + formula | MII_G_RT_FT3_m_T_PRU1 | Filter3<m> T (PRU1) | 3003 36ECh + formula | 300B 36ECh + formula |
6F0h + formula | MII_G_RT_FT3_m_T_MASK_PRU1 | Filter3<m> T Mask (PRU1) | 3003 36F0h + formula | 300B 36F0h + formula |
8D4h + formula | MII_G_RT_FT3_m_P0_PRU1 | Filter3<m>P0 (PRU1) | 3003 38D4h + formula | 300B 38D4h + formula |
8D8h + formula | MII_G_RT_FT3_m_P1_PRU1 | Filter3<m>P1 (PRU1) | 3003 38D8h + formula | 300B 38D8h + formula |
8DCh + formula | MII_G_RT_FT3_m_P_MASK0_PRU1 | Filter3 P Mask0 (PRU1) | 3003 38DCh + formula | 300B 38DCh + formula |
8E0h + formula | MII_G_RT_FT3_m_P_MASK1_PRU1 | Filter3 P Mask1 (PRU1) | 3003 38E0h + formula | 300B 38E0h + formula |
9D4h | MII_G_RT_FT_RX_PTR_PRU1 | Filter Byte Count (PRU1) | 3003 39D4h | 300B 39D4h |
9D8h + formula | MII_G_RT_RX_CLASSm_AND_EN_PRU1 | RX Class<m> AND Enable (PRU1) | 3003 39D8h + formula | 300B 39D8h + formula |
9DCh + formula | MII_G_RT_RX_CLASSm_OR_EN_PRU1 | RX Class<m> OR Enable (PRU1) | 3003 39DCh + formula | 300B 39DCh + formula |
A58h | MII_G_RT_RX_CLASS_CFG1_PRU1 | RX Class Configuration 1 Register | 3003 3A58h | 300B 3A58h |
A5Ch | MII_G_RT_RX_CLASS_CFG2_PRU1 | RX Class Configuration 2 Register | 3003 3A5Ch | 300B 3A5Ch |
A60h + formula | MII_G_RT_RX_CLASS_GATESm_PRU1 | RX Class Gate Configuration PRU1 Register | 3003 3A60h + formula | 300B 3A60h + formula |
AA0h | MII_G_RT_RX_GREEN_PRU1 | RX Green Status PRU1 | 3003 3AA0h | 300B 3AA0h |
AA4h | MII_G_RT_SA_HASH_PRU1 | SA Hash Seed PRU1 | 3003 3AA4h | 300B 3AA4h |
AA8h | MII_G_RT_CONN_HASH_PRU1 | Connection Hash Seed PRU1 | 3003 3AA8h | 300B 3AA8h |
AACh | MII_G_RT_CONN_HASH_START_PRU1 | Connection Hash Start PRU1 | 3003 3AACh | 300B 3AACh |
AB0h + formula | MII_G_RT_RX_RATE_CFGn_PRU1 | RX Rate Configuration Register | 3003 3AB0h + formula | 300B 3AB0h + formula |
AD0h | MII_G_RT_RX_RATE_SRC_SEL0_PRU1 | RX Rate Source Select0 | 3003 3AD0h | 300B 3AD0h |
AD4h | MII_G_RT_RX_RATE_SRC_SEL1_PRU1 | RX Rate Source Select1 | 3003 3AD4h | 300B 3AD4h |
AD8h + formula | MII_G_RT_TX_RATE_CFG1_n_PRU1 | TX Rate Configuration1 Register | 3003 3AD8h + formula | 300B 3AD8h + formula |
ADCh + formula | MII_G_RT_TX_RATE_CFG2_n_PRU1 | TX Rate Configuration2 Register | 3003 3ADCh + formula | 300B 3ADCh + formula |
B18h | MII_G_RT_RX_STAT_GOOD_PRU1 | RX Good Frame Count (PRU1) | 3003 3B18h | 300B 3B18h |
B1Ch | MII_G_RT_RX_STAT_BC_PRU1 | RX BC Frame Count (PRU1) | 3003 3B1Ch | 300B 3B1Ch |
B20h | MII_G_RT_RX_STAT_MC_PRU1 | RX MC Frame Count (PRU1) | 3003 3B20h | 300B 3B20h |
B24h | MII_G_RT_RX_STAT_CRC_ERR_PRU1 | RX CRC Error Frame Count (PRU1) | 3003 3B24h | 300B 3B24h |
B28h | MII_G_RT_RX_STAT_MII_ERR_PRU1 | RX MII Error Frame Count (PRU1) | 3003 3B28h | 300B 3B28h |
B2Ch | MII_G_RT_RX_STAT_ODD_ERR_PRU1 | RX Odd Nibble Frame Count (PRU1) | 3003 3B2Ch | 300B 3B2Ch |
B30h | MII_G_RT_RX_STAT_MAX_SIZE_PRU1 | RX Max Size Frame (PRU1) | 3003 3B30h | 300B 3B30h |
B34h | MII_G_RT_RX_STAT_MAX_ERR_PRU1 | RX Max Size Error Frame Count (PRU1) | 3003 3B34h | 300B 3B34h |
B38h | MII_G_RT_RX_STAT_MIN_SIZE_PRU1 | RX Min Size Frame (PRU1) | 3003 3B38h | 300B 3B38h |
B3Ch | MII_G_RT_RX_STAT_MIN_ERR_PRU1 | RX Min Size Error Frame Count (PRU1) | 3003 3B3Ch | 300B 3B3Ch |
B40h | MII_G_RT_RX_STAT_OVERRUN_ERR_PRU1 | RX Overrun Frame Count (PRU1) | 3003 3B40h | 300B 3B40h |
B44h + formula | MII_G_RT_RX_STAT_CLASSm_HIT_PRU1 | RX Class<m> | 3003 3B44h + formula | 300B 3B44h + formula |
B84h | MII_G_RT_RX_STAT_SMD_FRAG_ERR_PRU1 | RX SMD Frag Error Count (PRU1) | 3003 3B84h | 300B 3B84h |
B88h | MII_G_RT_RX_STAT_BKT1_SIZE_PRU1 | RX Bucket1 Size Configuration (PRU1) | 3003 3B88h | 300B 3B88h |
B8Ch | MII_G_RT_RX_STAT_BKT2_SIZE_PRU1 | RX Bucket2 Size Configuration (PRU1) | 3003 3B8Ch | 300B 3B8Ch |
B90h | MII_G_RT_RX_STAT_BKT3_SIZE_PRU1 | RX Bucket3 Size Configuration (PRU1) | 3003 3B90h | 300B 3B90h |
B94h | MII_G_RT_RX_STAT_BKT4_SIZE_PRU1 | RX Bucket4 Size Configuration (PRU1) | 3003 3B94h | 300B 3B94h |
B98h | MII_G_RT_RX_STAT_64_PRU1 | RX 64B Sized Frame Count (PRU1) | 3003 3B98h | 300B 3B98h |
B9Ch | MII_G_RT_RX_STAT_BKT1_PRU1 | RX Bucket1 Sized Frame Count (PRU1) | 3003 3B9Ch | 300B 3B9Ch |
BA0h | MII_G_RT_RX_STAT_BKT2_PRU1 | RX Bucket2 Sized Frame Count (PRU1) | 3003 3BA0h | 300B 3BA0h |
BA4h | MII_G_RT_RX_STAT_BKT3_PRU1 | RX Bucket3 Sized Frame Count (PRU1) | 3003 3BA4h | 300B 3BA4h |
BA8h | MII_G_RT_RX_STAT_BKT4_PRU1 | RX Bucket4 Sized Frame Count (PRU1) | 3003 3BA8h | 300B 3BA8h |
BACh | MII_G_RT_RX_STAT_BKT5_PRU1 | RX Bucket5 Sized Frame Count (PRU1) | 3003 3BACh | 300B 3BACh |
BB0h | MII_G_RT_RX_STAT_TOTAL_BYTES_PRU1 | RX Total Byte Count (PRU1) | 3003 3BB0h | 300B 3BB0h |
BB4h | MII_G_RT_RXTX_STAT_TOTAL_BYTES_PRU1 | RX TX Total Byte Count (PRU1) | 3003 3BB4h | 300B 3BB4h |
BB8h | MII_G_RT_TX_STAT_GOOD_PORT1 | TX Good Frame Count Port1 | 3003 3BB8h | 300B 3BB8h |
BBCh | MII_G_RT_TX_STAT_BC_PORT1 | TX BC Frame Count Port1 | 3003 3BBCh | 300B 3BBCh |
BC0h | MII_G_RT_TX_STAT_MC_PORT1 | TX MC Frame Count Port1 | 3003 3BC0h | 300B 3BC0h |
BC4h | MII_G_RT_TX_STAT_ODD_ERR_PORT1 | TX Odd Nibble Frame Count Port1 | 3003 3BC4h | 300B 3BC4h |
BC8h | MII_G_RT_TX_STAT_UNDERFLOW_ERR_PORT1 | TX Under Flow Error Count Port1 | 3003 3BC8h | 300B 3BC8h |
BCCh | MII_G_RT_TX_STAT_MAX_SIZE_PORT1 | TX Max Size Frame Port1 | 3003 3BCCh | 300B 3BCCh |
BD0h | MII_G_RT_TX_STAT_MAX_ERR_PORT1 | TX Max Size Error Frame Count Port1 | 3003 3BD0h | 300B 3BD0h |
BD4h | MII_G_RT_TX_STAT_MIN_SIZE_PORT1 | TX Min Size Frame Port1 | 3003 3BD4h | 300B 3BD4h |
BD8h | MII_G_RT_TX_STAT_MIN_ERR_PORT1 | TX Min Size Error Frame Count Port1 | 3003 3BD8h | 300B 3BD8h |
BDCh | MII_G_RT_TX_STAT_BKT1_SIZE_PORT1 | TX Bucket1 Size Configuration Port1 | 3003 3BDCh | 300B 3BDCh |
BE0h | MII_G_RT_TX_STAT_BKT2_SIZE_PORT1 | TX Bucket2 Size Configuration Port1 | 3003 3BE0h | 300B 3BE0h |
BE4h | MII_G_RT_TX_STAT_BKT3_SIZE_PORT1 | TX Bucket3 Size Configuration Port1 | 3003 3BE4h | 300B 3BE4h |
BE8h | MII_G_RT_TX_STAT_BKT4_SIZE_PORT1 | TX Bucket4 Size Configuration Port1 | 3003 3BE8h | 300B 3BE8h |
BECh | MII_G_RT_TX_STAT_64_PORT1 | TX 64B Sized Frame Count Port1 | 3003 3BECh | 300B 3BECh |
BF0h | MII_G_RT_TX_STAT_BKT1_PORT1 | TX Bucket1 Sized Frame Count Port1 | 3003 3BF0h | 300B 3BF0h |
BF4h | MII_G_RT_TX_STAT_BKT2_PORT1 | TX Bucket2 Sized Frame Count Port1 | 3003 3BF4h | 300B 3BF4h |
BF8h | MII_G_RT_TX_STAT_BKT3_PORT1 | TX Bucket3 Sized Frame Count Port1 | 3003 3BF8h | 300B 3BF8h |
BFCh | MII_G_RT_TX_STAT_BKT4_PORT1 | TX Bucket4 Sized Frame Count Port1 | 3003 3BFCh | 300B 3BFCh |
C00h | MII_G_RT_TX_STAT_BKT5_PORT1 | TX Bucket5 Sized Frame Count Port1 | 3003 3C00h | 300B 3C00h |
C04h | MII_G_RT_TX_STAT_TOTAL_BYTES_PORT1 | TX Total Byte Count Port1 | 3003 3C04h | 300B 3C04h |
C08h | MII_G_RT_TX_HSR_TAG_PORT1 | TX HSR TAG Port1 | 3003 3C08h | 300B 3C08h |
C0Ch | MII_G_RT_TX_HSR_SEQ_PORT1 | TX HSR Seq Port1 | 3003 3C0Ch | 300B 3C0Ch |
C10h | MII_G_RT_TX_VLAN_TYPE_TAG_PORT1 | TX VLAN Type TAG Port1 | 3003 3C10h | 300B 3C10h |
C14h | MII_G_RT_TX_VLAN_INS_TAG_PORT1 | TX VLAN Insertion TAG Port1 | 3003 3C14h | 300B 3C14h |
D00h + formula | MII_G_RT_QUEUEk | Queue<k> | 3003 3D00h + formula | 300B 3D00h + formula |
E00h + formula | MII_G_RT_QUEUE_PEEKm | Queue Peek<m> | 3003 3E00h + formula | 300B 3E00h + formula |
E40h + formula | MII_G_RT_QUEUE_CNTk | Queue Count<k> | 3003 3E40h + formula | 300B 3E40h + formula |
F40h | MII_G_RT_QUEUE_RESET | Queue Reset | 3003 3F40h | 300B 3F40h |
MII_G_RT_ICSS_G_CFG is shown in Figure 6-690 and described in Table 6-1372.
Return to Summary Table.
ICSS_G Config
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3000h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SGMII_MODE | ||||||
R/W-X | R/W-1h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TX_PRU_EN | RX_SFD_TX_SOF_EN | RTU_PRU_PSI_SHARE_EN | IEP1_TX_EN | |||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MII1_MODE | MII0_MODE | RX_L2_G_EN | TX_L2_EN | TX_L1_EN | ||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R/W | X | |
16 | SGMII_MODE | R/W | 1h | SGMII MODE 0: Fiber MODE 1: SGMII MODE |
15-12 | RESERVED | R/W | X | |
11 | TX_PRU_EN | R/W | 0h | Enable TX_PRU to gain control of MII TXL2 |
10 | RX_SFD_TX_SOF_EN | R/W | 0h | Enable the remaping of tx_sof to rx_sfd if auto fwd is enable |
9 | RTU_PRU_PSI_SHARE_EN | R/W | 0h | Enable the sharing of xfr2psi attached to PRU for PRU RTU AND HW FIFO |
8 | IEP1_TX_EN | R/W | 0h | Enable IEP1 for TX Enable 0: Use IEP0 CMP3_4 1: Use IEP1 CMP3_4 |
7 | RESERVED | R/W | X | |
6-5 | MII1_MODE | R/W | 0h | MII1 MODE 0: MII 1: RGMII 2: SGMII SGMII mode is supported only for PRU_ICSSG instance. |
4-3 | MII0_MODE | R/W | 0h | MII0 MODE 0: MII 1: RGMII 2: SGMII SGMII mode is supported only for PRU_ICSSG instance. |
2 | RX_L2_G_EN | R/W | 0h | Enable new RX L2 mode of
operation for non-EtherCAT Target protocols. 0: Disabled 1: Enabled Disable for EtherCAT Target protocols, enable for all other protocols. |
1 | TX_L2_EN | R/W | 0h | Enable the TX L2 FIFO 0: Disabled 1: Enabled |
0 | TX_L1_EN | R/W | 1h | Enable the TX L1 FIFO 0: Disabled 1: Enabled |
MII_G_RT_RGMII_CFG is shown in Figure 6-691 and described in Table 6-1374.
Return to Summary Table.
RGMII
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3004h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RGMII1_FULLDUPLEX_IN | RGMII1_GIG_IN | RGMII1_INBAND | RESERVED | RGMII0_FULLDUPLEX_IN | RGMII0_GIG_IN | RGMII0_INBAND |
R/W-X | R/W-1h | R/W-1h | R/W-0h | R/W-X | R/W-1h | R/W-1h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RGMII_EEE_PHY_ONLY | RGMII_EEE_EN | |||||
R/W-X | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RGMII1_FULLDUPLEX | RGMII1_SPEED | RGMII1_LINK | RGMII0_FULLDUPLEX | RGMII0_SPEED | RGMII0_LINK | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W | X | |
22 | RGMII1_FULLDUPLEX_IN | R/W | 1h | RGMII Fullduplex overide 0: half 1: full |
21 | RGMII1_GIG_IN | R/W | 1h | RGMII GigBit Enable 0: 100 Mbs 1: 1000 Mbs |
20 | RGMII1_INBAND | R/W | 0h | RGMII In BandEnable or Force 0: InBAND is Disabled 1: InBAND Enable |
19 | RESERVED | R/W | X | |
18 | RGMII0_FULLDUPLEX_IN | R/W | 1h | RGMII Fullduplex overide 0: half 1: full |
17 | RGMII0_GIG_IN | R/W | 1h | RGMII GigBit Enable 0: 100 Mbs 1: 1000 Mbs |
16 | RGMII0_INBAND | R/W | 0h | RGMII In BandEnable or Force 0: InBAND is Disabled 1: InBAND Enable |
15-10 | RESERVED | R/W | X | |
9 | RGMII_EEE_PHY_ONLY | R/W | 0h | RGMII Phy Only Low Power 0: disable 1: enable |
8 | RGMII_EEE_EN | R/W | 0h | RGMII Energy Efficient Enable
0: disable 1: enable |
7 | RGMII1_FULLDUPLEX | R | 0h | RGMII Fullduplex 0: half duplex 1: full duplex |
6-5 | RGMII1_SPEED | R | 0h | RGMII Speed 00: 10 Mpbs 01: 100 Mpbs 10: 1000 Mpbs |
4 | RGMII1_LINK | R | 0h | RGMII Link Status 0: link is down 1: link is up |
3 | RGMII0_FULLDUPLEX | R | 0h | RGMII Fullduplex 0: half duplex 1: full duplex |
2-1 | RGMII0_SPEED | R | 0h | RGMII Speed 00: 10 Mpbs 01: 100 Mpbs 10: 1000 Mpbs |
0 | RGMII0_LINK | R | 0h | RGMII Link Status 0: link is down 1: link is up |
MII_G_RT_MAC_PRU0_0 is shown in Figure 6-692 and described in Table 6-1376.
Return to Summary Table.
PRU0 MAC (DA3:DA0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3008h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAC_PRU0_0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAC_PRU0_0 | R/W | 0h | MAC PRU0 DA3:DA0 Used for SAV and DA match |
MII_G_RT_MAC_PRU0_1 is shown in Figure 6-693 and described in Table 6-1378.
Return to Summary Table.
PRU0 MAC (DA5:DA4).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 300Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 300Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_PRU0_1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | MAC_PRU0_1 | R/W | 0h | MAC PRU0 DA5:DA4 Used for SAV and DA match |
MII_G_RT_MAC_PRU1_0 is shown in Figure 6-694 and described in Table 6-1380.
Return to Summary Table.
PRU1 MAC (DA3:DA0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3010h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAC_PRU1_0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAC_PRU1_0 | R/W | 0h | MAC PRU1 DA3:DA0 Used for SAV and DA match |
MII_G_RT_MAC_PRU1_1 is shown in Figure 6-695 and described in Table 6-1382.
Return to Summary Table.
PRU1 MAC (DA5:DA4).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3014h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_PRU1_1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | MAC_PRU1_1 | R/W | 0h | MAC PRU1 DA5:DA4 Used for SAV and DA match |
MII_G_RT_MAC_INTERFACE_0 is shown in Figure 6-696 and described in Table 6-1384.
Return to Summary Table.
MAC Host Interface (DA3:DA0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3018h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAC_INF_0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAC_INF_0 | R/W | 0h | MAC Host interface DA3:DA0 Used for SAV and DA match |
MII_G_RT_MAC_INTERFACE_1 is shown in Figure 6-697 and described in Table 6-1386.
Return to Summary Table.
MAC Host Interface (DA5:DA4).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 301Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 301Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_INF_1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | MAC_INF_1 | R/W | 0h | MAC Host interface DA 5:DA4 Used for SAV and DA match |
MII_G_RT_PREEMPT_CFG is shown in Figure 6-698 and described in Table 6-1388.
Return to Summary Table.
Preempt Configuration Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3020h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMD_R | SMD_V | EXP_SMD | RESERVED | ||||||||||||||||||||||||||||
R/W-19h | R/W-7h | R/W-D5h | R/W-X | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SMD_R | R/W | 19h | Response frame TAG |
23-16 | SMD_V | R/W | 7h | Verification frame TAG |
15-8 | EXP_SMD | R/W | D5h | None pre-emptable frame start, or express frame |
7-0 | RESERVED | R/W | X |
MII_G_RT_SMDT1S_CFG is shown in Figure 6-699 and described in Table 6-1390.
Return to Summary Table.
SMD Type1S Preemptable Frame Start Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3024h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMDT1S_3 | SMDT1S_2 | SMDT1S_1 | SMDT1S_0 | ||||||||||||||||||||||||||||
R/W-B3h | R/W-7Fh | R/W-4Ch | R/W-E6h | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SMDT1S_3 | R/W | B3h | SMDT1S3 pattern |
23-16 | SMDT1S_2 | R/W | 7Fh | SMDT1S2 pattern |
15-8 | SMDT1S_1 | R/W | 4Ch | SMDT1S1 pattern |
7-0 | SMDT1S_0 | R/W | E6h | SMDT1S0 pattern |
MII_G_RT_SMDT1C_CFG is shown in Figure 6-700 and described in Table 6-1392.
Return to Summary Table.
SMD Type1C None Initial Frag Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3028h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMDT1C_3 | SMDT1C_2 | SMDT1C_1 | SMDT1C_0 | ||||||||||||||||||||||||||||
R/W-2Ah | R/W-9Eh | R/W-52h | R/W-61h | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SMDT1C_3 | R/W | 2Ah | SMDT1C3 pattern |
23-16 | SMDT1C_2 | R/W | 9Eh | SMDT1C2 pattern |
15-8 | SMDT1C_1 | R/W | 52h | SMDT1C1 pattern |
7-0 | SMDT1C_0 | R/W | 61h | SMDT1C0 pattern |
MII_G_RT_FRAG_CNT_CFG is shown in Figure 6-701 and described in Table 6-1394.
Return to Summary Table.
Frag Count Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3034h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FRAG_CNT_3 | FRAG_CNT_2 | ||||||||||||||
R/W-B3h | R/W-7Fh | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAG_CNT_1 | FRAG_CNT_0 | ||||||||||||||
R/W-4Ch | R/W-E6h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | FRAG_CNT_3 | R/W | B3h | FRAG Cnt3 pattern |
23-16 | FRAG_CNT_2 | R/W | 7Fh | FRAG Cnt2 pattern |
15-8 | FRAG_CNT_1 | R/W | 4Ch | FRAG Cnt1 pattern |
7-0 | FRAG_CNT_0 | R/W | E6h | FRAG Cnt0 pattern |
MII_G_RT_PA_STAT_PUSH0 is shown in Figure 6-702 and described in Table 6-1396.
Return to Summary Table.
Pa Stat Push0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3040h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PA_STAT_PUSH3_0 | PA_STAT_PUSH2_0 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PA_STAT_PUSH1_0 | PA_STAT_PUSH0_0 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PA_STAT_PUSH3_0 | R/W | 0h | pa stat push3 |
23-16 | PA_STAT_PUSH2_0 | R/W | 0h | pa stat push2 |
15-8 | PA_STAT_PUSH1_0 | R/W | 0h | pa stat push1 |
7-0 | PA_STAT_PUSH0_0 | R/W | 0h | pa stat push0 |
MII_G_RT_PA_STAT_PUSH1 is shown in Figure 6-703 and described in Table 6-1398.
Return to Summary Table.
Pa Stat Push1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3044h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PA_STAT_PUSH3_1 | PA_STAT_PUSH2_1 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PA_STAT_PUSH1_1 | PA_STAT_PUSH0_1 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PA_STAT_PUSH3_1 | R/W | 0h | pa stat push3 |
23-16 | PA_STAT_PUSH2_1 | R/W | 0h | pa stat push2 |
15-8 | PA_STAT_PUSH1_1 | R/W | 0h | pa stat push1 |
7-0 | PA_STAT_PUSH0_1 | R/W | 0h | pa stat push0 |
MII_G_RT_PA_STAT_PUSH2 is shown in Figure 6-704 and described in Table 6-1400.
Return to Summary Table.
Pa Stat Push2.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3048h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PA_STAT_PUSH3_2 | PA_STAT_PUSH2_2 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PA_STAT_PUSH1_2 | PA_STAT_PUSH0_2 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PA_STAT_PUSH3_2 | R/W | 0h | pa stat push3 |
23-16 | PA_STAT_PUSH2_2 | R/W | 0h | pa stat push2 |
15-8 | PA_STAT_PUSH1_2 | R/W | 0h | pa stat push1 |
7-0 | PA_STAT_PUSH0_2 | R/W | 0h | pa stat push0 |
MII_G_RT_PA_STAT_PUSH3 is shown in Figure 6-705 and described in Table 6-1402.
Return to Summary Table.
Pa Stat Push3.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 304Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 304Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PA_STAT_PUSH3_3 | PA_STAT_PUSH2_3 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PA_STAT_PUSH1_3 | PA_STAT_PUSH0_3 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PA_STAT_PUSH3_3 | R/W | 0h | pa stat push3 |
23-16 | PA_STAT_PUSH2_3 | R/W | 0h | pa stat push2 |
15-8 | PA_STAT_PUSH1_3 | R/W | 0h | pa stat push1 |
7-0 | PA_STAT_PUSH0_3 | R/W | 0h | pa stat push0 |
MII_G_RT_FDB_GEN_CFG1 is shown in Figure 6-706 and described in Table 6-1404.
Return to Summary Table.
FDB Configuration1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3060h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | SMEM_VLAN_OFFSET | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SMEM_VLAN_OFFSET | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SMEM_VLAN_OFFSET | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FDB_HASH_SIZE | RESERVED | FDB_BUCKET_SIZE | ||||
R/W-X | R/W-4h | R/W-X | R/W-2h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-8 | SMEM_VLAN_OFFSET | R/W | 0h | SMEM VLAN FID table base address |
7 | RESERVED | R/W | X | |
6-3 | FDB_HASH_SIZE | R/W | 4h | FDB hash size (Slots) 0: 64 1: 128 2: 256 3: 512 4: 1024 5: 2048 |
2 | RESERVED | R/W | X | |
1-0 | FDB_BUCKET_SIZE | R/W | 2h | FDB bucket size 0: 1 1: 2 2: 4 3: 8 |
MII_G_RT_FDB_GEN_CFG2 is shown in Figure 6-707 and described in Table 6-1406.
Return to Summary Table.
FDB Configuration2.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3064h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FDB_GEN_MODE_BYTE_EN | FDB_GEN_MODE_EN_BK1 | |||||
R/W-X | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDB_GEN_MODE_EN_BK0 | FDB_VLAN_EN | FDB_HSR_EN | RESERVED | FDB_HOST_EN | FDB_PRU1_EN | FDB_PRU0_EN | |
R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | X | |
12-9 | FDB_GEN_MODE_BYTE_EN | R/W | 0h | FDB General Mode Byte compare
size 0 = 1 Byte, 15 = 16 Bytes |
8 | FDB_GEN_MODE_EN_BK1 | R/W | 0h | FDB General Mode Enable Bank1 if set PRU0/PRU1/HOST will get disabled |
7 | FDB_GEN_MODE_EN_BK0 | R/W | 0h | FDB General Mode Enable Bank0 if set PRU0/PRU1/HOST will get disabled |
6 | FDB_VLAN_EN | R/W | 0h | FDB Global VLAN Enable |
5 | FDB_HSR_EN | R/W | 0h | FDB Global HSR Enable Note: VLAN must be disabled |
4-3 | RESERVED | R/W | X | |
2 | FDB_HOST_EN | R/W | 0h | FDB HOST Enable |
1 | FDB_PRU1_EN | R/W | 0h | FDB PRU1 Enable |
0 | FDB_PRU0_EN | R/W | 0h | FDB PRU0 Enable |
MII_G_RT_FDB_DF_VLAN is shown in Figure 6-708 and described in Table 6-1408.
Return to Summary Table.
FDB Default PRU VLAN.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 306Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 306Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FDB_PRU1_DF_VLAN | ||||||||||||||
R/W-X | R/W-1h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FDB_PRU0_DF_VLAN | ||||||||||||||
R/W-X | R/W-1h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | X | |
27-16 | FDB_PRU1_DF_VLAN | R/W | 1h | FDB Default VLAN for PRU1 |
15-12 | RESERVED | R/W | X | |
11-0 | FDB_PRU0_DF_VLAN | R/W | 1h | FDB Default VLAN for PRU0 |
MII_G_RT_FDB_HOST_DA0 is shown in Figure 6-709 and described in Table 6-1410.
Return to Summary Table.
FDB HOST DA3:0 Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3070h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDB_HOST_DA0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FDB_HOST_DA0 | R/W | 0h | FDB HOST DA3:0 |
MII_G_RT_FDB_HOST_DA1 is shown in Figure 6-710 and described in Table 6-1412.
Return to Summary Table.
FDB HOST DA5:4 Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3074h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FDB_HOST_DA1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | FDB_HOST_DA1 | R/W | 0h | FDB HOST DA 5:4 |
MII_G_RT_FDB_HOST_SA0 is shown in Figure 6-711 and described in Table 6-1414.
Return to Summary Table.
FDB HOST SA3:0 Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3078h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDB_HOST_SA0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FDB_HOST_SA0 | R/W | 0h | FDB HOST SA3:0 |
MII_G_RT_FDB_HOST_VLAN_SA1 is shown in Figure 6-712 and described in Table 6-1416.
Return to Summary Table.
FDB HOST VLAN SA5:4 Configuration.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 307Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 307Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FDB_HOST_VLAN_HSR | |||||||||||||||
R/W-1h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDB_HOST_SA1 | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FDB_HOST_VLAN_HSR | R/W | 1h | FDB HOST VLAN[11:0] OR HSR [15:0] |
15-0 | FDB_HOST_SA1 | R/W | 0h | FDB HOST SA 5:4 |
MII_G_RT_FT1_START_LEN_PRU0 is shown in Figure 6-713 and described in Table 6-1418.
Return to Summary Table.
Filter1 Start and Length (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3080h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT1_LEN | ||||||
R/W-X | R/W-6h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT1_START | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_START | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-16 | FT1_LEN | R/W | 6h | Defines the total number of Bytes Filter1 will check before Valid bit is set |
15 | RESERVED | R/W | X | |
14-0 | FT1_START | R/W | 0h | Byte count start for Filter1.
Any write will clear all Filter1 Status Bits |
MII_G_RT_FT1_CFG_PRU0 is shown in Figure 6-714 and described in Table 6-1420.
Return to Summary Table.
Filter1 Configuration (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3084h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FT1_7CFG | FT1_6CFG | FT1_5CFG | FT1_4CFG | ||||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_3CFG | FT1_2CFG | FT1_1CFG | FT1_0CFG | ||||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-14 | FT1_7CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
13-12 | FT1_6CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
11-10 | FT1_5CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
9-8 | FT1_4CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
7-6 | FT1_3CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
5-4 | FT1_2CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
3-2 | FT1_1CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
1-0 | FT1_0CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
MII_G_RT_FT1_k_DA0_PRU0 is shown in Figure 6-715 and described in Table 6-1422.
Return to Summary Table.
Filter1<k> DA0 (Pru0).
Offset = 88h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3088h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3088h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_k_DA0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT1_k_DA0 | R/W | 0h | Filter1 DA4:DA1 |
MII_G_RT_FT1_k_DA1_PRU0 is shown in Figure 6-716 and described in Table 6-1424.
Return to Summary Table.
Filter1<k> DA1 (PRU0).
Offset = 8Ch + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 308Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 308Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT1_k_DA1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | FT1_k_DA1 | R/W | 0h | Filter1 DA6:DA5 |
MII_G_RT_FT1_k_DA_MASK0_PRU0 is shown in Figure 6-717 and described in Table 6-1426.
Return to Summary Table.
Filter1<k> DA0 Mask (PRU0).
Offset = 90h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3090h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3090h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_k_DA_MASK0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT1_k_DA_MASK0 | R/W | 0h | Filter1 MDA4:MDA1 set to 1 to mask corresponding bit |
MII_G_RT_FT1_k_DA_MASK1_PRU0 is shown in Figure 6-718 and described in Table 6-1428.
Return to Summary Table.
Filter1<k> DA1 Mask (PRU0).
Offset = 94h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3094h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3094h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT1_k_DA_MASK1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | FT1_k_DA_MASK1 | R/W | 0h | Filter1 MDA6:MDA5 set to 1 to mask corresponding bit |
MII_G_RT_FT3_m_START_PRU0 is shown in Figure 6-719 and described in Table 6-1430.
Return to Summary Table.
Filter3 Byte Count Start.
Offset = 108h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3108h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3108h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_START | ||||||||||||||||||||||||||||||
R/W-X | R/W-Ch | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | X | |
14-0 | FT3_START | R/W | Ch | Byte count start for Filter3.
Any write will clear all Filter3 Status Bits SW can read to determine next start during Auto |
MII_G_RT_FT3_m_START_AUTO_PRU0 is shown in Figure 6-720 and described in Table 6-1432.
Return to Summary Table.
Filter3 Byte Count Start for Auto Skip mode.
Offset = 10Ch + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 310Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 310Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_START_AUTO | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | X | |
14-0 | FT3_START_AUTO | R | 0h | Byte count start for Auto skip mode |
MII_G_RT_FT3_m_START_LEN_PRU0 is shown in Figure 6-721 and described in Table 6-1434.
Return to Summary Table.
Filter3 Start Offset for PRU0.
Offset = 110h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3110h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3110h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT3_OFFSET_END | RESERVED | FT3_OFFSET_START | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_OFFSET | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_OFFSET | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W | X | |
22-20 | FT3_OFFSET_END | R/W | 0h | Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero |
19 | RESERVED | R/W | X | |
18-16 | FT3_OFFSET_START | R/W | 0h | Defines which byte within FT3_[N]P[63:0] to start the compare |
15 | RESERVED | R/W | X | |
14-0 | FT3_OFFSET | R/W | 0h | Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero |
MII_G_RT_FT3_m_JMP_OFFSET_PRU0 is shown in Figure 6-722 and described in Table 6-1436.
Return to Summary Table.
Filter3 Jump Offset for PRU0.
Offset = 114h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3114h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3114h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FT3_m_NJMP_OFFSET_PRU0 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FT3_m_NJMP_OFFSET_PRU0 | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_m_IJMP_OFFSET_PRU0 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_IJMP_OFFSET_PRU0 | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-16 | FT3_m_NJMP_OFFSET_PRU0 | R/W | 0h | Defines the Next Offset to compare when auto arm jump is enabled |
15 | RESERVED | R/W | X | |
14-0 | FT3_m_IJMP_OFFSET_PRU0 | R/W | 0h | Defines the Initial Offset to compare when auto arm jump is enabled |
MII_G_RT_FT3_m_LEN_PRU0 is shown in Figure 6-723 and described in Table 6-1438.
Return to Summary Table.
Filter3 Length Offset for PRU0.
Offset = 118h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3118h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3118h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FT3_m_LEN_BIG_EN_PRU0 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT3_m_LEN_SIZE_BIT_PRU0 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_m_LEN_START_BIT_PRU0 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_LEN_START_BIT_PRU0 | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | FT3_m_LEN_BIG_EN_PRU0 | R/W | 0h | Enable Big Indian on Length |
23-20 | RESERVED | R/W | X | |
19-16 | FT3_m_LEN_SIZE_BIT_PRU0 | R/W | 0h | Defines number of bits to extract the length for the auto skip function |
15-9 | RESERVED | R/W | X | |
8-0 | FT3_m_LEN_START_BIT_PRU0 | R/W | 0h | Defines relative bit offset from the HIT byte location upto 512 bit offset the extraction to determine the on the fly length byte offset |
MII_G_RT_FT3_m_CFG_PRU0 is shown in Figure 6-724 and described in Table 6-1440.
Return to Summary Table.
Filter3 Configuration for PRU0.
Offset = 11Ch + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 311Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 311Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FT3_m_TRIG_OR_EN | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FT3_m_TRIG_OR_EN | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_m_VLAN_SKIP_EN | FT3_mCFG | |||||
R/W-X | R/W-1h | R/W-1h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FT3_m_TRIG_OR_EN | R/W | 0h | Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not select the same ft3 only others |
15-3 | RESERVED | R/W | X | |
2 | FT3_m_VLAN_SKIP_EN | R/W | 1h | 0: Disabled 1: Enable |
1-0 | FT3_mCFG | R/W | 1h | 0: Disabled 1: EQ 2: GT 3: LT |
MII_G_RT_FT3_m_T_PRU0 is shown in Figure 6-725 and described in Table 6-1442.
Return to Summary Table.
Filter3 Type for PRU0.
Offset = 120h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3120h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3120h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_T | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_T | R/W | 0h | Filter3 T4:T1 Note if Auto Skip is enabled then Type filter is not enabled |
MII_G_RT_FT3_m_T_MASK_PRU0 is shown in Figure 6-726 and described in Table 6-1444.
Return to Summary Table.
Filter3 Mask for PRU0.
Offset = 124h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3124h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3124h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_T_MASK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_T_MASK | R/W | 0h | Filter3 MT4:MT1 Note: if Auto Skip is enabled then Type filter is not enabled set to 1 to mask corresponding bit |
MII_G_RT_FT3_m_P0_PRU0 is shown in Figure 6-727 and described in Table 6-1446.
Return to Summary Table.
Filter3 PRU0 (P4:P1).
Offset = 308h + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3308h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3308h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P0 | R/W | 0h | Filter3 P4:P1 |
MII_G_RT_FT3_m_P1_PRU0 is shown in Figure 6-728 and described in Table 6-1448.
Return to Summary Table.
Filter3 PRU0 (P8:P5).
Offset = 30Ch + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 330Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 330Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P1 | R/W | 0h | Filter3 P8:P5 |
MII_G_RT_FT3_n_P_MASK0_PRU0 is shown in Figure 6-729 and described in Table 6-1450.
Return to Summary Table.
Filter3 Mask0 (MP4:MP1).
Offset = 310h + (n * 10h); where n = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3310h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3310h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_n_P_MASK0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_n_P_MASK0 | R/W | 0h | Filter3 MP4:MP1 set to 1 to mask corresponding bit |
MII_G_RT_FT3_n_P_MASK1_PRU0 is shown in Figure 6-730 and described in Table 6-1452.
Return to Summary Table.
Filter3 Mask1 (MP8:MP5).
Offset = 314h + (n * 10h); where n = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3314h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3314h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_n_P_MASK1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_n_P_MASK1 | R/W | 0h | Filter3 MP8:MP5 set to 1 to mask corresponding bit |
MII_G_RT_FT_RX_PTR_PRU0 is shown in Figure 6-731 and described in Table 6-1454.
Return to Summary Table.
RX Current Filter Byte Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3408h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3408h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT_RX_PTR_PRU0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT_RX_PTR_PRU0 | R/W | 0h | RX current filter Byte Count |
MII_G_RT_RX_CLASSm_AND_EN_PRU0 is shown in Figure 6-732 and described in Table 6-1456.
Return to Summary Table.
RX Class<m> AND Enable Register.
Offset = 40Ch + (m * 8h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 340Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 340Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASSm_AND_EN | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_CLASSm_AND_EN | R/W | 0h | rx class AND enable |
MII_G_RT_RX_CLASSm_OR_EN_PRU0 is shown in Figure 6-733 and described in Table 6-1458.
Return to Summary Table.
RX Class<m> OR Enable Register.
Offset = 410h + (m * 8h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3410h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3410h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASSm_OR_EN | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_CLASSm_OR_EN | R/W | 0h | rx class OR enable |
MII_G_RT_RX_CLASS_CFG1_PRU0 is shown in Figure 6-734 and described in Table 6-1460.
Return to Summary Table.
RX Class Configuration 1 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 348Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 348Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RX_CLASS15_SEL | RX_CLASS14_SEL | RX_CLASS13_SEL | RX_CLASS12_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_CLASS11_SEL | RX_CLASS10_SEL | RX_CLASS9_SEL | RX_CLASS8_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_CLASS7_SEL | RX_CLASS6_SEL | RX_CLASS5_SEL | RX_CLASS4_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASS3_SEL | RX_CLASS2_SEL | RX_CLASS1_SEL | RX_CLASS0_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RX_CLASS15_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
29-28 | RX_CLASS14_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
27-26 | RX_CLASS13_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
25-24 | RX_CLASS12_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
23-22 | RX_CLASS11_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
21-20 | RX_CLASS10_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
19-18 | RX_CLASS9_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
17-16 | RX_CLASS8_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
15-14 | RX_CLASS7_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
13-12 | RX_CLASS6_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
11-10 | RX_CLASS5_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
9-8 | RX_CLASS4_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
7-6 | RX_CLASS3_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
5-4 | RX_CLASS2_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
3-2 | RX_CLASS1_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
1-0 | RX_CLASS0_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
MII_G_RT_RX_CLASS_CFG2_PRU0 is shown in Figure 6-735 and described in Table 6-1462.
Return to Summary Table.
RX Class Configuration 2 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3490h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3490h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASS_OR_NV | RX_CLASS_AND_NV | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RX_CLASS_OR_NV | R/W | 0h | RX class invert OR not invert enable |
15-0 | RX_CLASS_AND_NV | R/W | 0h | RX class invert AND not invert enable |
MII_G_RT_RX_CLASS_GATESm_PRU0 is shown in Figure 6-736 and described in Table 6-1464.
Return to Summary Table.
RX Class Gate<m> Configuration PRU0 Register.
Offset = 494h + (m * 4h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3494h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3494h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RED_PHASE_ENm | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_ALLOW_MASKm | RX_CLASS_RAW_MASKm | RX_PHASE_MASKm | RESERVED | RX_RATE_GATE_SELm | ||
R/W-X | R/W-1h | R/W-1h | R/W-1h | R/W-X | R/W-0h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | RX_RED_PHASE_ENm | R/W | 0h | red phase enable 0: disable 1: enable |
7 | RESERVED | R/W | X | |
6 | RX_ALLOW_MASKm | R/W | 1h | allow mask 0: unmask 1: mask |
5 | RX_CLASS_RAW_MASKm | R/W | 1h | class raw mask 0: unmask 1: mask |
4 | RX_PHASE_MASKm | R/W | 1h | time phase mask 0: unmask 1: mask |
3 | RESERVED | R/W | X | |
2-0 | RX_RATE_GATE_SELm | R/W | 0h | defines which rx_rate will gate rx_class |
MII_G_RT_RX_GREEN_PRU0 is shown in Figure 6-737 and described in Table 6-1466.
Return to Summary Table.
RX Green Status PRU0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 34D4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 34D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_GREEN_VAL | RX_GREEN_CMP_SEL | |||||
R/W-X | R-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | RX_GREEN_VAL | R | 0h | 0: RED, 1: GREEN status |
3-0 | RX_GREEN_CMP_SEL | R/W | 0h | define which IEP CMP start green |
MII_G_RT_SA_HASH_PRU0 is shown in Figure 6-738 and described in Table 6-1468.
Return to Summary Table.
SA Hash Seed PRU0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 34D8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 34D8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA_HASH_SEED | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | SA_HASH_SEED | R/W | 0h | SA Hash Seed |
MII_G_RT_CONN_HASH_PRU0 is shown in Figure 6-739 and described in Table 6-1470.
Return to Summary Table.
Connection Hash Seed PRU0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 34DCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 34DCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONN_HASH_SEED | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | CONN_HASH_SEED | R/W | 0h | Connection Hash Seed |
MII_G_RT_CONN_HASH_START_PRU0 is shown in Figure 6-740 and described in Table 6-1472.
Return to Summary Table.
Connection Hash Start PRU0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 34E0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 34E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONN_HASH_START | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | X | |
14-0 | CONN_HASH_START | R/W | 0h | Connection Hash Start which 4 Bytes to hash |
MII_G_RT_RX_RATE_CFGn_PRU0 is shown in Figure 6-741 and described in Table 6-1474.
Return to Summary Table.
RX Rate Configuration<n> Register.
Offset = 4E4h + (n * 4h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 34E4h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 34E4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_RATE_CIR_IDLEn | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_RATE_CIR_IDLEn | R/W | 0h | RX Rate Peak Information Rate
Idle Increment Value - The number added to the PIR
counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED |
MII_G_RT_RX_RATE_SRC_SEL0_PRU0 is shown in Figure 6-742 and described in Table 6-1476.
Return to Summary Table.
RX Rate Source Select0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3504h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3504h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RX_RATE_SRC_SEL3 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_RATE_SRC_SEL2 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RATE_SRC_SEL1 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_RATE_SRC_SEL0 | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | X | |
29-24 | RX_RATE_SRC_SEL3 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
23-22 | RESERVED | R/W | X | |
21-16 | RX_RATE_SRC_SEL2 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
15-14 | RESERVED | R/W | X | |
13-8 | RX_RATE_SRC_SEL1 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
7-6 | RESERVED | R/W | X | |
5-0 | RX_RATE_SRC_SEL0 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
MII_G_RT_RX_RATE_SRC_SEL1_PRU0 is shown in Figure 6-743 and described in Table 6-1478.
Return to Summary Table.
RX Rate Source Select1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3508h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3508h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RX_RATE_SRC_SEL7 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_RATE_SRC_SEL6 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RATE_SRC_SEL5 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_RATE_SRC_SEL4 | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | X | |
29-24 | RX_RATE_SRC_SEL7 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
23-22 | RESERVED | R/W | X | |
21-16 | RX_RATE_SRC_SEL6 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
15-14 | RESERVED | R/W | X | |
13-8 | RX_RATE_SRC_SEL5 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
7-6 | RESERVED | R/W | X | |
5-0 | RX_RATE_SRC_SEL4 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see RX Rate hit Mappingtable for mapping |
MII_G_RT_TX_RATE_CFG1_n_PRU0 is shown in Figure 6-744 and described in Table 6-1480.
Return to Summary Table.
TX Rate Configuration1 Registe.
Offset = 50Ch + (n * 8h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 350Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 350Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_RATE_CIR_IDLEn | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_RATE_CIR_IDLEn | R/W | 0h | TX Rate Peak Information Rate
Idle Increment Value - The number added to the PIR
counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED |
MII_G_RT_TX_RATE_CFG2_n_PRU0 is shown in Figure 6-745 and described in Table 6-1482.
Return to Summary Table.
TX Rate Configuration2 Register.
Offset = 510h + (n * 8h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3510h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3510h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TX_RATE_ALLOWn | TX_RATE_ENn | |||||
R/W-X | R-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TX_RATE_LENn | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_RATE_LENn | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | X | |
17 | TX_RATE_ALLOWn | R | 0h | TX Rate Pkt Enable |
16 | TX_RATE_ENn | R/W | 0h | TX Rate Pkt Enable |
15-0 | TX_RATE_LENn | R/W | 0h | TX Rate Pkt Length |
MII_G_RT_RX_STAT_GOOD_PRU0 is shown in Figure 6-746 and described in Table 6-1484.
Return to Summary Table.
RX Good Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 354Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 354Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_GOOD_FRM_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_GOOD_FRM_CNT | R/W | 0h | RX Good Frame Count Increment on none min err max err CRC err odd err, Write to subtract |
MII_G_RT_RX_STAT_BC_PRU0 is shown in Figure 6-747 and described in Table 6-1486.
Return to Summary Table.
RX BC Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3550h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3550h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_BC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_BC_FRM_CNT | R/W | 0h | RX BC Frame Count Increment on BC type, Write to subtract |
MII_G_RT_RX_STAT_MC_PRU0 is shown in Figure 6-748 and described in Table 6-1488.
Return to Summary Table.
RX MC Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3554h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3554h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MC_FRM_CNT | R/W | 0h | RX MC Frame Count Increment on MC type, Write to subtract |
MII_G_RT_RX_STAT_CRC_ERR_PRU0 is shown in Figure 6-749 and described in Table 6-1490.
Return to Summary Table.
RX CRC Error Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3558h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3558h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CRC_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_CRC_ERR_FRM_CNT | R/W | 0h | RX CRC Err Frame Count Increment on CRC error, Write to subtract |
MII_G_RT_RX_STAT_MII_ERR_PRU0 is shown in Figure 6-750 and described in Table 6-1492.
Return to Summary Table.
RX MII Error Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 355Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 355Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MII_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MII_ERR_FRM_CNT | R/W | 0h | RX MII Err Frame Count Increment on MII, SGMII, RGMII error, Write to subtract |
MII_G_RT_RX_STAT_ODD_ERR_PRU0 is shown in Figure 6-751 and described in Table 6-1494.
Return to Summary Table.
RX Odd Nibble Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3560h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3560h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_ODD_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_ODD_ERR_FRM_CNT | R/W | 0h | RX Odd Nibble Frame Count Increment on odd nibble MII, Write to subtract |
MII_G_RT_RX_STAT_MAX_SIZE_PRU0 is shown in Figure 6-752 and described in Table 6-1496.
Return to Summary Table.
RX Max Size Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3564h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3564h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-7D0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MAX_SIZE_FRM | R/W | 7D0h | RX MAX Size Frame Count Limit |
MII_G_RT_RX_STAT_MAX_ERR_PRU0 is shown in Figure 6-753 and described in Table 6-1498.
Return to Summary Table.
RX Max Size Error Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3568h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3568h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MAX_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MAX_ERR_FRM_CNT | R/W | 0h | RX MAX Size Err Frame Count Increment if > than Limit, Write to subtract |
MII_G_RT_RX_STAT_MIN_SIZE_PRU0 is shown in Figure 6-754 and described in Table 6-1500.
Return to Summary Table.
RX Min Size Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 356Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 356Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MIN_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MIN_SIZE_FRM | R/W | 40h | RX MIN Size Frame Limit |
MII_G_RT_RX_STAT_MIN_ERR_PRU0 is shown in Figure 6-755 and described in Table 6-1502.
Return to Summary Table.
RX Min Size Error Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3570h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3570h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MIN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MIN_ERR_FRM_CNT | R/W | 0h | RX MIN Size Frame Count Increment if < than limit, Write to subtract |
MII_G_RT_RX_STAT_OVERRUN_ERR_PRU0 is shown in Figure 6-756 and described in Table 6-1504.
Return to Summary Table.
RX Overrun Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3574h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3574h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_OVERRUN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_OVERRUN_ERR_FRM_CNT | R/W | 0h | RX L1 FIFO overflow Frame Count. Increment on overflow event, Write to subtract |
MII_G_RT_RX_STAT_CLASSm_HIT_PRU0 is shown in Figure 6-757 and described in Table 6-1506.
Return to Summary Table.
RX Class<m> Hit.
Offset = 578h + (n * 4h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3578h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3578h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_CLASSm_PRU0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_STAT_CLASSm_PRU0 | R/W | 0h | RX Class<m> Hit Count
(where m = 0 to 15). Write to subtract |
MII_G_RT_RX_STAT_SMD_FRAG_ERR_PRU0 is shown in Figure 6-758 and described in Table 6-1508.
Return to Summary Table.
RX SMD Frag Error Count PRU0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35B8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_STAT_SMD_ERR_PRU0 | RX_STAT_FRAG_ERR_PRU0 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_SMDC_ERR_PRU0 | RX_STAT_SMDS_ERR_PRU0 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RX_STAT_SMD_ERR_PRU0 | R/W | 0h | RX SMDS Error Count, Increment when first none 0x55 does not match any valid SMD, Write to subtract |
23-16 | RX_STAT_FRAG_ERR_PRU0 | R/W | 0h | RX Frag_Cnt Seq Error Count, Write to subtract |
15-8 | RX_STAT_SMDC_ERR_PRU0 | R/W | 0h | RX SMDCx Seq Error Count, Write to subtract |
7-0 | RX_STAT_SMDS_ERR_PRU0 | R/W | 0h | RX SMDSx Seq Error Count, Write to subtract |
MII_G_RT_RX_STAT_BKT1_SIZE_PRU0 is shown in Figure 6-759 and described in Table 6-1510.
Return to Summary Table.
RX Bucket1 Size Configuration (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35BCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT1_SIZE | ||||||||||||||
R/W-X | R/W-40h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT1_SIZE | R/W | 40h | RX Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT2_SIZE_PRU0 is shown in Figure 6-760 and described in Table 6-1512.
Return to Summary Table.
RX Bucket2 Size Configuration (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35C0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT2_SIZE | ||||||||||||||
R/W-X | R/W-80h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT2_SIZE | R/W | 80h | RX Bucket2 Byte Size |
MII_G_RT_RX_STAT_BKT3_SIZE_PRU0 is shown in Figure 6-761 and described in Table 6-1514.
Return to Summary Table.
RX Bucket3 Size Configuration (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35C4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT3_SIZE | ||||||||||||||
R/W-X | R/W-100h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT3_SIZE | R/W | 100h | RX Bucket3 Byte Size |
MII_G_RT_RX_STAT_BKT4_SIZE_PRU0 is shown in Figure 6-762 and described in Table 6-1516.
Return to Summary Table.
RX Bucket4 Size Configuration (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35C8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT4_SIZE | ||||||||||||||
R/W-X | R/W-200h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT4_SIZE | R/W | 200h | RX Bucket4 Byte Size |
MII_G_RT_RX_STAT_64_PRU0 is shown in Figure 6-763 and described in Table 6-1518.
Return to Summary Table.
RX 64B Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35CCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_64_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_64_FRM_CNT | R/W | 0h | RX 64 Byte Frame Count Increment if 64 B size |
MII_G_RT_RX_STAT_BKT1_PRU0 is shown in Figure 6-764 and described in Table 6-1520.
Return to Summary Table.
RX Bucket1 Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35D0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT1 | R/W | 0h | RX Bucket1 Frame Count Increment if <= than Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT2_PRU0 is shown in Figure 6-765 and described in Table 6-1522.
Return to Summary Table.
RX Bucket2 Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35D4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT2 | R/W | 0h | RX Bucket2 Frame Count Increment if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT3_PRU0 is shown in Figure 6-766 and described in Table 6-1524.
Return to Summary Table.
RX Bucket3 Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35D8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35D8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT3 | R/W | 0h | RX Bucket3 Frame Count Increment if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size |
MII_G_RT_RX_STAT_BKT4_PRU0 is shown in Figure 6-767 and described in Table 6-1526.
Return to Summary Table.
RX Bucket4 Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35DCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35DCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT4 | R/W | 0h | RX Bucket4 Frame Count Increment if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size |
MII_G_RT_RX_STAT_BKT5_PRU0 is shown in Figure 6-768 and described in Table 6-1528.
Return to Summary Table.
RX Bucket5 Sized Frame Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35E0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT5 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT5 | R/W | 0h | RX Bucket5 Frame Count Increment if > than Bucket4 Byte Size |
MII_G_RT_RX_STAT_TOTAL_BYTES_PRU0 is shown in Figure 6-769 and described in Table 6-1530.
Return to Summary Table.
RX Total Byte Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35E4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_TOTAL_BYTES_PRU | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_STAT_TOTAL_BYTES_PRU | R/W | 0h | RX Total Byte Count |
MII_G_RT_RXTX_STAT_TOTAL_BYTES_PRU0 is shown in Figure 6-770 and described in Table 6-1532.
Return to Summary Table.
RX TX Total Byte Count (PRU0).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35E8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35E8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXTX_STAT_TOTAL_BYTES_PRU | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RXTX_STAT_TOTAL_BYTES_PRU | R/W | 0h | RX and TX Total Byte Count |
MII_G_RT_TX_STAT_GOOD_PORT0 is shown in Figure 6-771 and described in Table 6-1534.
Return to Summary Table.
TX Good Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35ECh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_GOOD_FRM_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_GOOD_FRM_CNT | R/W | 0h | TX Good Frame Count Increment if no min size err max size err or MII odd nibble |
MII_G_RT_TX_STAT_BC_PORT0 is shown in Figure 6-772 and described in Table 6-1536.
Return to Summary Table.
TX BC Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35F0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_BC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_BC_FRM_CNT | R/W | 0h | TX BC Frame Count Increment if BC |
MII_G_RT_TX_STAT_MC_PORT0 is shown in Figure 6-773 and described in Table 6-1538.
Return to Summary Table.
TX MC Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35F4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MC_FRM_CNT | R/W | 0h | TX MC Frame Count. Increment if MC |
MII_G_RT_TX_STAT_ODD_ERR_PORT0 is shown in Figure 6-774 and described in Table 6-1540.
Return to Summary Table.
TX Odd Nibble Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35F8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_ODD_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_ODD_ERR_FRM_CNT | R/W | 0h | TX Odd Nibble Frame Count Increment if MII odd nibble |
MII_G_RT_TX_STAT_UNDERFLOW_ERR_PORT0 is shown in Figure 6-775 and described in Table 6-1542.
Return to Summary Table.
TX Under Flow Error Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 35FCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 35FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_UNDERFLOW_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_UNDERFLOW_CNT | R/W | 0h | TX MAX Underflow Error Cnt |
MII_G_RT_TX_STAT_MAX_SIZE_PORT0 is shown in Figure 6-776 and described in Table 6-1544.
Return to Summary Table.
TX Max Size Frame Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3600h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3600h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MAX_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-7D0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MAX_SIZE_FRM | R/W | 7D0h | TX MAX Size Frame Count Limit |
MII_G_RT_TX_STAT_MAX_ERR_PORT0 is shown in Figure 6-777 and described in Table 6-1546.
Return to Summary Table.
TX Max Size Error Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3604h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3604h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_MAX_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MAX_ERR_FRM_CNT | R/W | 0h | TX MAX Size Err Frame Count Increment if > max Limit |
MII_G_RT_TX_STAT_MIN_SIZE_PORT0 is shown in Figure 6-778 and described in Table 6-1548.
Return to Summary Table.
TX Min Size Frame Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3608h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3608h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MIN_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MIN_SIZE_FRM | R/W | 40h | TX MIN Size Frame Count Limit |
MII_G_RT_TX_STAT_MIN_ERR_PORT0 is shown in Figure 6-779 and described in Table 6-1550.
Return to Summary Table.
TX Min Size ErrorFrame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 360Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 360Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_MIN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MIN_ERR_FRM_CNT | R/W | 0h | TX MIN Size Err Frame Count Increment if < min Limit |
MII_G_RT_TX_STAT_BKT1_SIZE_PORT0 is shown in Figure 6-780 and described in Table 6-1552.
Return to Summary Table.
TX Bucket1 Size Configuration Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3610h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3610h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT1_SIZE | ||||||||||||||
R/W-X | R/W-40h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT1_SIZE | R/W | 40h | TX Bucket1 Byte Size |
MII_G_RT_TX_STAT_BKT2_SIZE_PORT0 is shown in Figure 6-781 and described in Table 6-1554.
Return to Summary Table.
TX Bucket2 Size Configuration Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3614h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3614h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT2_SIZE | ||||||||||||||
R/W-X | R/W-80h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT2_SIZE | R/W | 80h | TX Bucket2 Byte Size |
MII_G_RT_TX_STAT_BKT3_SIZE_PORT0 is shown in Figure 6-782 and described in Table 6-1556.
Return to Summary Table.
TX Bucket3 Size Configuration Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3618h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3618h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT3_SIZE | ||||||||||||||
R/W-X | R/W-100h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT3_SIZE | R/W | 100h | TX Bucket3 Byte Size |
MII_G_RT_TX_STAT_BKT4_SIZE_PORT0 is shown in Figure 6-783 and described in Table 6-1558.
Return to Summary Table.
TX Bucket4 Size Configuration Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 361Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 361Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT4_SIZE | ||||||||||||||
R/W-X | R/W-200h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT4_SIZE | R/W | 200h | TX Bucket4 Byte Size |
MII_G_RT_TX_STAT_64_PORT0 is shown in Figure 6-784 and described in Table 6-1560.
Return to Summary Table.
TX 64B Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3620h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3620h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_64_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_64_FRM_CNT | R/W | 0h | TX 64 Byte Frame Count. Increment if 64 B |
MII_G_RT_TX_STAT_BKT1_PORT0 is shown in Figure 6-785 and described in Table 6-1562.
Return to Summary Table.
TX Bucket1 Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3624h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3624h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT1 | R/W | 0h | TX Bucket1 Increment if <= than Bucket1 |
MII_G_RT_TX_STAT_BKT2_PORT0 is shown in Figure 6-786 and described in Table 6-1564.
Return to Summary Table.
TX Bucket2 Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3628h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3628h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT2 | R/W | 0h | TX Bucket2 Increment if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size |
MII_G_RT_TX_STAT_BKT3_PORT0 is shown in Figure 6-787 and described in Table 6-1566.
Return to Summary Table.
TX Bucket3 Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 362Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 362Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT3 | R/W | 0h | TX Bucket3 Increment if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size |
MII_G_RT_TX_STAT_BKT4_PORT0 is shown in Figure 6-788 and described in Table 6-1568.
Return to Summary Table.
TX Bucket4 Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3630h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3630h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT4 | R/W | 0h | TX Bucket4 Increment if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size |
MII_G_RT_TX_STAT_BKT5_PORT0 is shown in Figure 6-789 and described in Table 6-1570.
Return to Summary Table.
TX Bucket5 Sized Frame Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3634h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3634h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT5 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT5 | R/W | 0h | TX Bucket5 Increment if > than Bucket4 Byte Size |
MII_G_RT_TX_STAT_TOTAL_BYTES_PORT0 is shown in Figure 6-790 and described in Table 6-1572.
Return to Summary Table.
TX Total Byte Count Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3638h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3638h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_TOTAL_STAT_BYTES_PORT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_TOTAL_STAT_BYTES_PORT | R/W | 0h | TX Total Byte Count of all Frames |
MII_G_RT_TX_HSR_TAG_PORT0 is shown in Figure 6-791 and described in Table 6-1574.
Return to Summary Table.
TX HSR TAG Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 363Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 363Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_HSR_TAG | |||||||||||||||||||||||||||||||
R/W-892Fh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_HSR_TAG | R/W | 892Fh | HSR TAG |
MII_G_RT_TX_HSR_SEQ_PORT0 is shown in Figure 6-792 and described in Table 6-1576.
Return to Summary Table.
TX HSR Seq Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3640h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3640h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_HSR_SEQ | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_HSR_SEQ | R/W | 0h | HSR Seq count. It will incr for every HSR type |
MII_G_RT_TX_VLAN_TYPE_TAG_PORT0 is shown in Figure 6-793 and described in Table 6-1578.
Return to Summary Table.
TX VLAN Type TAG Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3644h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3644h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_VLAN_TYPE_TAG | ||||||||||||||||||||||||||||||
R/W-X | R/W-81h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_VLAN_TYPE_TAG | R/W | 81h | TX VLAN Type Tag, match to enable VLAN removal |
MII_G_RT_TX_VLAN_INS_TAG_PORT0 is shown in Figure 6-794 and described in Table 6-1580.
Return to Summary Table.
TX VLAN Insertion TAG Port0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3648h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3648h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_VLAN_INS_TAG | |||||||||||||||||||||||||||||||
R/W-1h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_VLAN_INS_TAG | R/W | 1h | TX VLAN Insertion |
MII_G_RT_FT1_START_LEN_PRU1 is shown in Figure 6-795 and described in Table 6-1582.
Return to Summary Table.
Filter1 Start and Length (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 364Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 364Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT1_LEN | ||||||
R/W-X | R/W-6h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT1_START | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_START | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-16 | FT1_LEN | R/W | 6h | Defines the total number of Bytes Filter1 will check before Valid bit is set |
15 | RESERVED | R/W | X | |
14-0 | FT1_START | R/W | 0h | Byte count start for Filter1.
Any write will clear all Filter1 Status Bits |
MII_G_RT_FT1_CFG_PRU1 is shown in Figure 6-796 and described in Table 6-1584.
Return to Summary Table.
Filter1 Configuration (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3650h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3650h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FT1_7CFG | FT1_6CFG | FT1_5CFG | FT1_4CFG | ||||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_3CFG | FT1_2CFG | FT1_1CFG | FT1_0CFG | ||||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-14 | FT1_7CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
13-12 | FT1_6CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
11-10 | FT1_5CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
9-8 | FT1_4CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
7-6 | FT1_3CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
5-4 | FT1_2CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
3-2 | FT1_1CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
1-0 | FT1_0CFG | R/W | 1h | 0h = Disabled 1h = Equal 2h = Greater Than 3h = Less Than |
MII_G_RT_FT1_k_DA0_PRU1 is shown in Figure 6-797 and described in Table 6-1586.
Return to Summary Table.
Filter1<k> DA0 (PRU1).
Offset = 654h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3654h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3654h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_k_DA0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT1_k_DA0 | R/W | 0h | Filter1 DA4:DA1 |
MII_G_RT_FT1_k_DA1_PRU1 is shown in Figure 6-798 and described in Table 6-1588.
Return to Summary Table.
Filter1<k> DA1 (PRU1).
Offset = 658h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3658h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3658h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT1_k_DA1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | FT1_k_DA1 | R/W | 0h | Filter1 DA6:DA5 |
MII_G_RT_FT1_k_DA_MASK0_PRU1 is shown in Figure 6-799 and described in Table 6-1590.
Return to Summary Table.
Filter1<k> DA0 Mask (PRU1).
Offset = 65Ch + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 365Ch + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 365Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT1_k_DA_MASK0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT1_k_DA_MASK0 | R/W | 0h | Filter1 MDA4:MDA1 set to 1 to mask corresponding bit |
MII_G_RT_FT1_k_DA_MASK1_PRU1 is shown in Figure 6-800 and described in Table 6-1592.
Return to Summary Table.
Filter1<k> DA1 Mask (PRU1).
Offset = 660h + (k * 10h); where k = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3660h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3660h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT1_k_DA_MASK1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | FT1_k_DA_MASK1 | R/W | 0h | Filter1 MDA6:MDA5 set to 1 to mask corresponding bit |
MII_G_RT_FT3_m_START_PRU1 is shown in Figure 6-801 and described in Table 6-1594.
Return to Summary Table.
Filter3<m> Start (PRU1).
Offset = 6D4h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36D4h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36D4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_START | ||||||||||||||||||||||||||||||
R/W-X | R/W-Ch | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | X | |
14-0 | FT3_START | R/W | Ch | Byte count start for Filter3.
Any write will clear all Filter3 Status Bits SW can read to determine next start during Auto |
MII_G_RT_FT3_m_START_AUTO_PRU1 is shown in Figure 6-802 and described in Table 6-1596.
Return to Summary Table.
Filter3<m> Start Auto (PRU1).
Offset = 6D8h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36D8h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36D8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_START_AUTO | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | X | |
14-0 | FT3_START_AUTO | R | 0h | Byte count start for Auto skip mode |
MII_G_RT_FT3_m_START_LEN_PRU1 is shown in Figure 6-803 and described in Table 6-1598.
Return to Summary Table.
Filter3<m> Start offset (PRU1).
Offset = 6DCh + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36DCh + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36DCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT3_OFFSET_END | RESERVED | FT3_OFFSET_START | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_OFFSET | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_OFFSET | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W | X | |
22-20 | FT3_OFFSET_END | R/W | 0h | Defines which byte within FT3_[N]P[63:0] to end the compare at set the Valid flag, rule ft3_offset_end >= ft3_offset_start To disable pattern compare set start and end to zero |
19 | RESERVED | R/W | X | |
18-16 | FT3_OFFSET_START | R/W | 0h | Defines which byte within FT3_[N]P[63:0] to start the compare |
15 | RESERVED | R/W | X | |
14-0 | FT3_OFFSET | R/W | 0h | Determine which byte to start FT3_[N]P[63:0] operation it will start on the next byte after FT3_T completes if set to zero |
MII_G_RT_FT3_m_JMP_OFFSET_PRU1 is shown in Figure 6-804 and described in Table 6-1600.
Return to Summary Table.
Filter3<m> Jmp offset (PRU1).
Offset = 6E0h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36E0h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36E0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FT3_m_NJMP_OFFSET_PRU1 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FT3_m_NJMP_OFFSET_PRU1 | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_m_IJMP_OFFSET_PRU1 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_IJMP_OFFSET_PRU1 | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-16 | FT3_m_NJMP_OFFSET_PRU1 | R/W | 0h | Defines the Next Offset to compare when auto arm jump is enabled |
15 | RESERVED | R/W | X | |
14-0 | FT3_m_IJMP_OFFSET_PRU1 | R/W | 0h | Defines the Initial Offset to compare when auto arm jump is enabled |
MII_G_RT_FT3_m_LEN_PRU1 is shown in Figure 6-805 and described in Table 6-1602.
Return to Summary Table.
Filter3 Length Offset for (PRU1).
Offset = 6E4h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36E4h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36E4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | FT3_m_LEN_BIG_EN_PRU1 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FT3_m_LEN_SIZE_BIT_PRU1 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | FT3_m_LEN_START_BIT_PRU1 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_LEN_START_BIT_PRU1 | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | FT3_m_LEN_BIG_EN_PRU1 | R/W | 0h | Enable Big Indian on Length |
23-20 | RESERVED | R/W | X | |
19-16 | FT3_m_LEN_SIZE_BIT_PRU1 | R/W | 0h | Defines number of bits to extract the length for the auto skip function |
15-9 | RESERVED | R/W | X | |
8-0 | FT3_m_LEN_START_BIT_PRU1 | R/W | 0h | Defines relative bit offset from the HIT byte location upto 512 bit offset the extraction to determine the on the fly length byte offset |
MII_G_RT_FT3_m_CFG_PRU1 is shown in Figure 6-806 and described in Table 6-1604.
Return to Summary Table.
Filter3<m> Configuration (PRU1).
Offset = 6E8h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36E8h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36E8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FT3_m_TRIG_OR_EN | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FT3_m_TRIG_OR_EN | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FT3_m_VLAN_SKIP_EN | FT3_mCFG | |||||
R/W-X | R/W-1h | R/W-1h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FT3_m_TRIG_OR_EN | R/W | 0h | Trigger ft3 select for auto skip enable, if one or more set the function is enabled note you can not select the same ft3 only others |
15-3 | RESERVED | R/W | X | |
2 | FT3_m_VLAN_SKIP_EN | R/W | 1h | 0: Disabled 1: Enable |
1-0 | FT3_mCFG | R/W | 1h | 0: Disabled 1: EQ 2: GT 3: LT |
MII_G_RT_FT3_m_T_PRU1 is shown in Figure 6-807 and described in Table 6-1606.
Return to Summary Table.
Filter3<m> T (PRU1).
Offset = 6ECh + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36ECh + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36ECh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_T | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_T | R/W | 0h | Filter3 T4:T1 Note: if Auto Skip is enabled then Type filter is not enabled |
MII_G_RT_FT3_m_T_MASK_PRU1 is shown in Figure 6-808 and described in Table 6-1608.
Return to Summary Table.
Filter3<m> T Mask (PRU1).
Offset = 6F0h + (m * 20h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 36F0h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 36F0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_T_MASK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_T_MASK | R/W | 0h | Filter3 MT4:MT1 Note: if Auto Skip is enabled then Type filter is not enabled set to 1 to mask corresponding bit |
MII_G_RT_FT3_m_P0_PRU1 is shown in Figure 6-809 and described in Table 6-1610.
Return to Summary Table.
Filter3<m> P0 (PRU1).
Offset = 8D4h + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 38D4h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 38D4h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P0 | R/W | 0h | Filter3 P4:P1 |
MII_G_RT_FT3_m_P1_PRU1 is shown in Figure 6-810 and described in Table 6-1612.
Return to Summary Table.
Filter3<m> P1 (PRU1).
Offset = 8D8h + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 38D8h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 38D8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P1 | R/W | 0h | Filter3 P8:P5 |
MII_G_RT_FT3_m_P_MASK0_PRU1 is shown in Figure 6-811 and described in Table 6-1614.
Return to Summary Table.
Filter3<m> P Mask0 (PRU1).
Offset = 8DCh + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 38DCh + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 38DCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P_MASK0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P_MASK0 | R/W | 0h | Filter3 MP4:MP1 set to 1 to mask corresponding bit |
MII_G_RT_FT3_m_P_MASK1_PRU1 is shown in Figure 6-812 and described in Table 6-1616.
Return to Summary Table.
Filter3<m> P Mask1 (PRU1).
Offset = 8E0h + (m * 10h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 38E0h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 38E0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT3_m_P_MASK1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT3_m_P_MASK1 | R/W | 0h | Filter3 MP8:MP5 set to 1 to mask corresponding bit |
MII_G_RT_FT_RX_PTR_PRU1 is shown in Figure 6-813 and described in Table 6-1618.
Return to Summary Table.
Filter Byte Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 39D4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 39D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FT_RX_PTR_PRU1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | FT_RX_PTR_PRU1 | R/W | 0h | RX current filter Byte Count |
MII_G_RT_RX_CLASSm_AND_EN_PRU1 is shown in Figure 6-814 and described in Table 6-1620.
Return to Summary Table.
RX Class<m> AND Enable (PRU1).
Offset = 9D8h + (m * 8h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 39D8h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 39D8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASSm_AND_EN | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_CLASSm_AND_EN | R/W | 0h | RX class AND enable |
MII_G_RT_RX_CLASSm_OR_EN_PRU1 is shown in Figure 6-815 and described in Table 6-1622.
Return to Summary Table.
RX Class<m> OR Enable (PRU1).
Offset = 9DCh + (m * 8h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 39DCh + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 39DCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASSm_OR_EN | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_CLASSm_OR_EN | R/W | 0h | RX class OR enable. |
MII_G_RT_RX_CLASS_CFG1_PRU1 is shown in Figure 6-816 and described in Table 6-1624.
Return to Summary Table.
RX Class Configuration 1 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3A58h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3A58h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RX_CLASS15_SEL | RX_CLASS14_SEL | RX_CLASS13_SEL | RX_CLASS12_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_CLASS11_SEL | RX_CLASS10_SEL | RX_CLASS9_SEL | RX_CLASS8_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_CLASS7_SEL | RX_CLASS6_SEL | RX_CLASS5_SEL | RX_CLASS4_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASS3_SEL | RX_CLASS2_SEL | RX_CLASS1_SEL | RX_CLASS0_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RX_CLASS15_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
29-28 | RX_CLASS14_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
27-26 | RX_CLASS13_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
25-24 | RX_CLASS12_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
23-22 | RX_CLASS11_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
21-20 | RX_CLASS10_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
19-18 | RX_CLASS9_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
17-16 | RX_CLASS8_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
15-14 | RX_CLASS7_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
13-12 | RX_CLASS6_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
11-10 | RX_CLASS5_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
9-8 | RX_CLASS4_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
7-6 | RX_CLASS3_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
5-4 | RX_CLASS2_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
3-2 | RX_CLASS1_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
1-0 | RX_CLASS0_SEL | R/W | 0h | rx class final term selection
00: OR 01: AND 10: OR AND AND 11: OR OR AND |
MII_G_RT_RX_CLASS_CFG2_PRU1 is shown in Figure 6-817 and described in Table 6-1626.
Return to Summary Table.
RX Class Configuration 2 Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3A5Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3A5Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CLASS_OR_NV | RX_CLASS_AND_NV | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RX_CLASS_OR_NV | R/W | 0h | RX class or nv enable |
15-0 | RX_CLASS_AND_NV | R/W | 0h | RX class AND nv enable |
MII_G_RT_RX_CLASS_GATESm_PRU1 is shown in Figure 6-818 and described in Table 6-1628.
Return to Summary Table.
RX Class Gate Configuration PRU1 Register.
Offset = A60h + (m * 4h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3A60h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3A60h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RED_PHASE_ENm | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_ALLOW_MASKm | RX_CLASS_RAW_MASKm | RX_PHASE_MASKm | RESERVED | RX_RATE_GATE_SELm | ||
R/W-X | R/W-1h | R/W-1h | R/W-1h | R/W-X | R/W-0h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | RX_RED_PHASE_ENm | R/W | 0h | red phase enable 0: disable 1: enable |
7 | RESERVED | R/W | X | |
6 | RX_ALLOW_MASKm | R/W | 1h | allow mask 0: unmask 1: mask |
5 | RX_CLASS_RAW_MASKm | R/W | 1h | class raw mask 0: unmask 1: mask |
4 | RX_PHASE_MASKm | R/W | 1h | time phase mask 0: unmask 1: mask |
3 | RESERVED | R/W | X | |
2-0 | RX_RATE_GATE_SELm | R/W | 0h | defines which rx_rate will gate rx_class |
MII_G_RT_RX_GREEN_PRU1 is shown in Figure 6-819 and described in Table 6-1630.
Return to Summary Table.
RX Green Status PRU1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AA0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AA0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_GREEN_VAL | RX_GREEN_CMP_SEL | |||||
R/W-X | R-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | RX_GREEN_VAL | R | 0h | 0: RED, 1: GREEN status |
3-0 | RX_GREEN_CMP_SEL | R/W | 0h | define which IEP CMP start green |
MII_G_RT_SA_HASH_PRU1 is shown in Figure 6-820 and described in Table 6-1632.
Return to Summary Table.
SA Hash Seed PRU1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AA4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AA4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA_HASH_SEED | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | SA_HASH_SEED | R/W | 0h | SA Hash Seed |
MII_G_RT_CONN_HASH_PRU1 is shown in Figure 6-821 and described in Table 6-1634.
Return to Summary Table.
Connection Hash Seed PRU1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AA8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AA8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONN_HASH_SEED | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | CONN_HASH_SEED | R/W | 0h | Connection Hash Seed |
MII_G_RT_CONN_HASH_START_PRU1 is shown in Figure 6-822 and described in Table 6-1636.
Return to Summary Table.
Connection Hash Start PRU1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AACh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CONN_HASH_START | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W | X | |
14-0 | CONN_HASH_START | R/W | 0h | Connection Hash Start which 4 Bytes to hash |
MII_G_RT_RX_RATE_CFGn_PRU1 is shown in Figure 6-823 and described in Table 6-1638.
Return to Summary Table.
RX Rate Configuration Register.
Offset = AB0h + (n * 4h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AB0h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AB0h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_RATE_CIR_IDLEn | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_RATE_CIR_IDLEn | R/W | 0h | RX Rate Peak Information Rate
Idle Increment Value - The number added to the PIR
counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED |
MII_G_RT_RX_RATE_SRC_SEL0_PRU1 is shown in Figure 6-824 and described in Table 6-1640.
Return to Summary Table.
RX Rate Source Select0.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AD0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AD0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RX_RATE_SRC_SEL3 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_RATE_SRC_SEL2 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RATE_SRC_SEL1 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_RATE_SRC_SEL0 | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | X | |
29-24 | RX_RATE_SRC_SEL3 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
23-22 | RESERVED | R/W | X | |
21-16 | RX_RATE_SRC_SEL2 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
15-14 | RESERVED | R/W | X | |
13-8 | RX_RATE_SRC_SEL1 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
7-6 | RESERVED | R/W | X | |
5-0 | RX_RATE_SRC_SEL0 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
MII_G_RT_RX_RATE_SRC_SEL1_PRU1 is shown in Figure 6-825 and described in Table 6-1642.
Return to Summary Table.
RX Rate Source Select1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AD4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AD4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RX_RATE_SRC_SEL7 | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_RATE_SRC_SEL6 | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_RATE_SRC_SEL5 | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_RATE_SRC_SEL4 | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | X | |
29-24 | RX_RATE_SRC_SEL7 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
23-22 | RESERVED | R/W | X | |
21-16 | RX_RATE_SRC_SEL6 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
15-14 | RESERVED | R/W | X | |
13-8 | RX_RATE_SRC_SEL5 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
7-6 | RESERVED | R/W | X | |
5-0 | RX_RATE_SRC_SEL4 | R/W | 0h | Map which filter/flag/class hit that rate logic uses, see table for mapping |
MII_G_RT_TX_RATE_CFG1_n_PRU1 is shown in Figure 6-826 and described in Table 6-1644.
Return to Summary Table.
TX Rate Configuration 1 Register.
Offset = AD8h + (n * 8h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3AD8h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3AD8h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_RATE_CIR_IDLEn | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_RATE_CIR_IDLEn | R/W | 0h | TX Rate Peak Information Rate
Idle Increment Value - The number added to the PIR
counter every clock cycle including EOF. The PIR counter is disabled with a zero value and packets will not be marked RED |
MII_G_RT_TX_RATE_CFG2_n_PRU1 is shown in Figure 6-827 and described in Table 6-1646.
Return to Summary Table.
TX Rate Configuration 2 Register.
Offset = ADCh + (n * 8h); where n = 0h to 7h
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3ADCh + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3ADCh + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TX_RATE_ALLOWn | TX_RATE_ENn | |||||
R/W-X | R-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TX_RATE_LENn | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_RATE_LENn | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | X | |
17 | TX_RATE_ALLOWn | R | 0h | TX Rate Pkt Enable |
16 | TX_RATE_ENn | R/W | 0h | TX Rate Pkt Enable |
15-0 | TX_RATE_LENn | R/W | 0h | TX Rate Pkt Length |
MII_G_RT_RX_STAT_GOOD_PRU1 is shown in Figure 6-828 and described in Table 6-1648.
Return to Summary Table.
RX Good Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B18h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B18h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_GOOD_FRM_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_GOOD_FRM_CNT | R/W | 0h | RX Good Frame Count. increment on none min err max err CRC err odd err, Write to subtract |
MII_G_RT_RX_STAT_BC_PRU1 is shown in Figure 6-829 and described in Table 6-1650.
Return to Summary Table.
RX BC Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B1Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B1Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_BC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_BC_FRM_CNT | R/W | 0h | RX BC Frame Count increment on BC type, Write to subtract |
MII_G_RT_RX_STAT_MC_PRU1 is shown in Figure 6-830 and described in Table 6-1652.
Return to Summary Table.
RX MC Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B20h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B20h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MC_FRM_CNT | R/W | 0h | RX MC Frame Count increment on MC type, Write to subtract |
MII_G_RT_RX_STAT_CRC_ERR_PRU1 is shown in Figure 6-831 and described in Table 6-1654.
Return to Summary Table.
RX CRC Error Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B24h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B24h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_CRC_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_CRC_ERR_FRM_CNT | R/W | 0h | RX CRC Err Frame Count increment on CRC error, Write to subtract |
MII_G_RT_RX_STAT_MII_ERR_PRU1 is shown in Figure 6-832 and described in Table 6-1656.
Return to Summary Table.
RX MII Error Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B28h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B28h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MII_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MII_ERR_FRM_CNT | R/W | 0h | RX MII Err Frame Count increment on MII, SGMII, RGMII error, Write to subtract |
MII_G_RT_RX_STAT_ODD_ERR_PRU1 is shown in Figure 6-833 and described in Table 6-1658.
Return to Summary Table.
RX Odd Nibble Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B2Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B2Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_ODD_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_ODD_ERR_FRM_CNT | R/W | 0h | RX Odd Nibble Frame Count increment on odd nibble MII, Write to subtract |
MII_G_RT_RX_STAT_MAX_SIZE_PRU1 is shown in Figure 6-834 and described in Table 6-1660.
Return to Summary Table.
RX Max Size Frame (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B30h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B30h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-7D0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MAX_SIZE_FRM | R/W | 7D0h | RX MAX Size Frame Count Limit |
MII_G_RT_RX_STAT_MAX_ERR_PRU1 is shown in Figure 6-835 and described in Table 6-1662.
Return to Summary Table.
RX Max Size Error Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B34h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B34h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MAX_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MAX_ERR_FRM_CNT | R/W | 0h | RX MAX Size Err Frame Count increment if > than Limit, Write to subtract |
MII_G_RT_RX_STAT_MIN_SIZE_PRU1 is shown in Figure 6-836 and described in Table 6-1664.
Return to Summary Table.
RX Min Size Frame (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B38h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B38h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MIN_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MIN_SIZE_FRM | R/W | 40h | RX MIN Size Frame Limit |
MII_G_RT_RX_STAT_MIN_ERR_PRU1 is shown in Figure 6-837 and described in Table 6-1666.
Return to Summary Table.
RX Min Size Error Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B3Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B3Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MIN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_MIN_ERR_FRM_CNT | R/W | 0h | RX MIN Size Frame Count increment if < than limit, Write to subtract |
MII_G_RT_RX_STAT_OVERRUN_ERR_PRU1 is shown in Figure 6-838 and described in Table 6-1668.
Return to Summary Table.
RX Overrun Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B40h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B40h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_OVERRUN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_OVERRUN_ERR_FRM_CNT | R/W | 0h | RX L1 FIFO overflow Frame Count increment on overflow event, Write to subtract |
MII_G_RT_RX_STAT_CLASSm_HIT_PRU1 is shown in Figure 6-839 and described in Table 6-1670.
Return to Summary Table.
RX Class<m>.
Offset = B44h + (m * 4h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B44h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B44h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_CLASSm_PRU1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_STAT_CLASSm_PRU1 | R/W | 0h | RX Class<m> Hit Count
(where m = 0 to 15). Write to subtract |
MII_G_RT_RX_STAT_SMD_FRAG_ERR_PRU1 is shown in Figure 6-840 and described in Table 6-1672.
Return to Summary Table.
RX SMD Frag Error Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B84h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B84h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_STAT_SMD_ERR_PRU1 | RX_STAT_FRAG_ERR_PRU1 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_SMDC_ERR_PRU1 | RX_STAT_SMDS_ERR_PRU1 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RX_STAT_SMD_ERR_PRU1 | R/W | 0h | RX SMDS Error Count, increment when first none 0x55 does not match any valid SMD, Write to subtract |
23-16 | RX_STAT_FRAG_ERR_PRU1 | R/W | 0h | RX Frag_Cnt Seq Error Count, Write to subtract |
15-8 | RX_STAT_SMDC_ERR_PRU1 | R/W | 0h | RX SMDCx Seq Error Count, Write to subtract |
7-0 | RX_STAT_SMDS_ERR_PRU1 | R/W | 0h | RX SMDSx Seq Error Count, Write to subtract |
MII_G_RT_RX_STAT_BKT1_SIZE_PRU1 is shown in Figure 6-841 and described in Table 6-1674.
Return to Summary Table.
RX Bucket1 Size Configuration (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B88h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B88h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT1_SIZE | ||||||||||||||
R/W-X | R/W-40h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT1_SIZE | R/W | 40h | RX Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT2_SIZE_PRU1 is shown in Figure 6-842 and described in Table 6-1676.
Return to Summary Table.
RX Bucket2 Size Configuration (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B8Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B8Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT2_SIZE | ||||||||||||||
R/W-X | R/W-80h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT2_SIZE | R/W | 80h | RX Bucket2 Byte Size |
MII_G_RT_RX_STAT_BKT3_SIZE_PRU1 is shown in Figure 6-843 and described in Table 6-1678.
Return to Summary Table.
RX Bucket3 Size Configuration (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B90h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B90h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT3_SIZE | ||||||||||||||
R/W-X | R/W-100h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT3_SIZE | R/W | 100h | RX Bucket3 Byte Size |
MII_G_RT_RX_STAT_BKT4_SIZE_PRU1 is shown in Figure 6-844 and described in Table 6-1680.
Return to Summary Table.
RX Bucket4 Size Configuration (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B94h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B94h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT4_SIZE | ||||||||||||||
R/W-X | R/W-200h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_STAT_BKT4_SIZE | R/W | 200h | RX Bucket4 Byte Size |
MII_G_RT_RX_STAT_64_PRU1 is shown in Figure 6-845 and described in Table 6-1682.
Return to Summary Table.
RX 64B Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B98h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B98h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_64_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_64_FRM_CNT | R/W | 0h | RX 64 Byte Frame Count increment if 64 B size |
MII_G_RT_RX_STAT_BKT1_PRU1 is shown in Figure 6-846 and described in Table 6-1684.
Return to Summary Table.
RX Bucket1 Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3B9Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3B9Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT1 | R/W | 0h | RX Bucket1 Frame Count increment if <= than Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT2_PRU1 is shown in Figure 6-847 and described in Table 6-1686.
Return to Summary Table.
RX Bucket2 Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BA0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BA0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT2 | R/W | 0h | RX Bucket2 Frame Count increment if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size |
MII_G_RT_RX_STAT_BKT3_PRU1 is shown in Figure 6-848 and described in Table 6-1688.
Return to Summary Table.
RX Bucket3 Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BA4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BA4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT3 | R/W | 0h | RX Bucket3 Frame Count increment if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size |
MII_G_RT_RX_STAT_BKT4_PRU1 is shown in Figure 6-849 and described in Table 6-1690.
Return to Summary Table.
RX Bucket4 Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BA8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BA8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT4 | R/W | 0h | RX Bucket4 Frame Count increment if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size |
MII_G_RT_RX_STAT_BKT5_PRU1 is shown in Figure 6-850 and described in Table 6-1692.
Return to Summary Table.
RX Bucket5 Sized Frame Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BACh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_STAT_BKT5 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_STAT_BKT5 | R/W | 0h | RX Bucket5 Frame Count increment if > than Bucket4 Byte Size |
MII_G_RT_RX_STAT_TOTAL_BYTES_PRU1 is shown in Figure 6-851 and described in Table 6-1694.
Return to Summary Table.
RX Total Byte Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BB0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BB0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_STAT_TOTAL_BYTES_PRU | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RX_STAT_TOTAL_BYTES_PRU | R/W | 0h | RX Total Byte Count |
MII_G_RT_RXTX_STAT_TOTAL_BYTES_PRU1 is shown in Figure 6-852 and described in Table 6-1696.
Return to Summary Table.
RX TX Total Byte Count (PRU1).
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BB4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BB4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXTX_STAT_TOTAL_BYTES_PRU | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RXTX_STAT_TOTAL_BYTES_PRU | R/W | 0h | RX and TX Total Byte Count |
MII_G_RT_TX_STAT_GOOD_PORT1 is shown in Figure 6-853 and described in Table 6-1698.
Return to Summary Table.
TX Good Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BB8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BB8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_GOOD_FRM_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_GOOD_FRM_CNT | R/W | 0h | TX Good Frame Count increment if no min size err max size err or MII odd nibble |
MII_G_RT_TX_STAT_BC_PORT1 is shown in Figure 6-854 and described in Table 6-1700.
Return to Summary Table.
TX BC Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BBCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BBCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_BC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_BC_FRM_CNT | R/W | 0h | TX BC Frame Count increment if BC |
MII_G_RT_TX_STAT_MC_PORT1 is shown in Figure 6-855 and described in Table 6-1702.
Return to Summary Table.
TX MC Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BC0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BC0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MC_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MC_FRM_CNT | R/W | 0h | TX MC Frame Count increment if MC |
MII_G_RT_TX_STAT_ODD_ERR_PORT1 is shown in Figure 6-856 and described in Table 6-1704.
Return to Summary Table.
TX Odd Nibble Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BC4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BC4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_ODD_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_ODD_ERR_FRM_CNT | R/W | 0h | TX Odd Nibble Frame Count increment if MII odd nibble |
MII_G_RT_TX_STAT_UNDERFLOW_ERR_PORT1 is shown in Figure 6-857 and described in Table 6-1706.
Return to Summary Table.
TX Under Flow Error Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BC8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BC8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_UNDERFLOW_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_UNDERFLOW_CNT | R/W | 0h | TX MAX Underflow Error Count |
MII_G_RT_TX_STAT_MAX_SIZE_PORT1 is shown in Figure 6-858 and described in Table 6-1708.
Return to Summary Table.
TX Max Size Frame Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BCCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BCCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MAX_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-7D0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MAX_SIZE_FRM | R/W | 7D0h | TX MAX Size Frame Count Limit |
MII_G_RT_TX_STAT_MAX_ERR_PORT1 is shown in Figure 6-859 and described in Table 6-1710.
Return to Summary Table.
TX Max Size Error Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BD0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BD0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_MAX_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MAX_ERR_FRM_CNT | R/W | 0h | TX MAX Size Err Frame Count increment if > max Limit |
MII_G_RT_TX_STAT_MIN_SIZE_PORT1 is shown in Figure 6-860 and described in Table 6-1712.
Return to Summary Table.
TX Min Size Frame Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BD4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BD4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_MIN_SIZE_FRM | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MIN_SIZE_FRM | R/W | 40h | TX MIN Size Frame Count Limit |
MII_G_RT_TX_STAT_MIN_ERR_PORT1 is shown in Figure 6-861 and described in Table 6-1714.
Return to Summary Table.
TX Min Size Error Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BD8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BD8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_MIN_ERR_FRM_CNT | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_MIN_ERR_FRM_CNT | R/W | 0h | TX MIN Size Err Frame Count increment if < min Limit |
MII_G_RT_TX_STAT_BKT1_SIZE_PORT1 is shown in Figure 6-862 and described in Table 6-1716.
Return to Summary Table.
TX Bucket1 Size Configuration Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BDCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BDCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT1_SIZE | ||||||||||||||
R/W-X | R/W-40h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT1_SIZE | R/W | 40h | TX Bucket1 Byte Size |
MII_G_RT_TX_STAT_BKT2_SIZE_PORT1 is shown in Figure 6-863 and described in Table 6-1718.
Return to Summary Table.
TX Bucket2 Size Configuration Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BE0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BE0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT2_SIZE | ||||||||||||||
R/W-X | R/W-80h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT2_SIZE | R/W | 80h | TX Bucket2 Byte Size |
MII_G_RT_TX_STAT_BKT3_SIZE_PORT1 is shown in Figure 6-864 and described in Table 6-1720.
Return to Summary Table.
TX Bucket3 Size Configuration Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BE4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BE4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT3_SIZE | ||||||||||||||
R/W-X | R/W-100h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT3_SIZE | R/W | 100h | TX Bucket3 Byte Size |
MII_G_RT_TX_STAT_BKT4_SIZE_PORT1 is shown in Figure 6-865 and described in Table 6-1722.
Return to Summary Table.
TX Bucket4 Size Configuration Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BE8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BE8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT4_SIZE | ||||||||||||||
R/W-X | R/W-200h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_STAT_BKT4_SIZE | R/W | 200h | TX Bucket4 Byte Size |
MII_G_RT_TX_STAT_64_PORT1 is shown in Figure 6-866 and described in Table 6-1724.
Return to Summary Table.
TX 64B Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BECh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_64_FRM_CNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_64_FRM_CNT | R/W | 0h | TX 64 Byte Frame Count increment if 64 B |
MII_G_RT_TX_STAT_BKT1_PORT1 is shown in Figure 6-867 and described in Table 6-1726.
Return to Summary Table.
TX Bucket1 Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BF0h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BF0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT1 | R/W | 0h | TX Bucket1 increment if <= than Bucket1 |
MII_G_RT_TX_STAT_BKT2_PORT1 is shown in Figure 6-868 and described in Table 6-1728.
Return to Summary Table.
TX Bucket2 Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BF4h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BF4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT2 | R/W | 0h | TX Bucket2 increment if <= than Bucket2 Byte Size and if > than Bucket1 Byte Size |
MII_G_RT_TX_STAT_BKT3_PORT1 is shown in Figure 6-869 and described in Table 6-1730.
Return to Summary Table.
TX Bucket3 Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BF8h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BF8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT3 | R/W | 0h | TX Bucket3 increment if <= than Bucket3 Byte Size and if > than Bucket2 Byte Size |
MII_G_RT_TX_STAT_BKT4_PORT1 is shown in Figure 6-870 and described in Table 6-1732.
Return to Summary Table.
TX Bucket4 Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3BFCh |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3BFCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT4 | R/W | 0h | TX Bucket4 increment if <= than Bucket4 Byte Size and if > than Bucket3 Byte Size |
MII_G_RT_TX_STAT_BKT5_PORT1 is shown in Figure 6-871 and described in Table 6-1734.
Return to Summary Table.
TX Bucket5 Sized Frame Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C00h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C00h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_STAT_BKT5 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_STAT_BKT5 | R/W | 0h | TX Bucket5 increment if > than Bucket4 Byte Size |
MII_G_RT_TX_STAT_TOTAL_BYTES_PORT1 is shown in Figure 6-872 and described in Table 6-1736.
Return to Summary Table.
TX Total Byte Count Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C04h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C04h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_TOTAL_STAT_BYTES_PORT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_TOTAL_STAT_BYTES_PORT | R/W | 0h | TX Total Byte Count of all Frames |
MII_G_RT_TX_HSR_TAG_PORT1 is shown in Figure 6-873 and described in Table 6-1738.
Return to Summary Table.
TX HSR TAG Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C08h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C08h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_HSR_TAG | |||||||||||||||||||||||||||||||
R/W-892Fh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_HSR_TAG | R/W | 892Fh | HSR TAG |
MII_G_RT_TX_HSR_SEQ_PORT1 is shown in Figure 6-874 and described in Table 6-1740.
Return to Summary Table.
TX HSR Seq Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C0Ch |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C0Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_HSR_SEQ | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_HSR_SEQ | R/W | 0h | HSR Seq count. It will increment for every HSR type |
MII_G_RT_TX_VLAN_TYPE_TAG_PORT1 is shown in Figure 6-875 and described in Table 6-1742.
Return to Summary Table.
TX VLAN Type TAG Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C10h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C10h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_VLAN_TYPE_TAG | ||||||||||||||||||||||||||||||
R/W-X | R/W-81h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_VLAN_TYPE_TAG | R/W | 81h | TX VLAN Type Tag, match to enable VLAN removal |
MII_G_RT_TX_VLAN_INS_TAG_PORT1 is shown in Figure 6-876 and described in Table 6-1744.
Return to Summary Table.
TX VLAN Insertion TAG Port1.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3C14h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3C14h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_VLAN_INS_TAG | |||||||||||||||||||||||||||||||
R/W-1h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TX_VLAN_INS_TAG | R/W | 1h | TX VLAN Insertion |
MII_G_RT_QUEUEk is shown in Figure 6-877 and described in Table 6-1746.
Return to Summary Table.
Queue<k>.
Offset = D00h + (k * 4h); where k = 0h to 3Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3D00h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3D00h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | QUEUE_H_PTRk | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | QUEUE_H_PTRk | R/W | 0h | Queue <k> (where k = 0 to 63). |
MII_G_RT_QUEUE_PEEKm is shown in Figure 6-878 and described in Table 6-1748.
Return to Summary Table.
Queue Peek<m>
Offset = E00h + (m * 4h); where m = 0h to Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3E00h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3E00h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE_H_PEEK_PTRm | |||||||||||||||
R-0h | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | QUEUE_H_PEEK_PTRm | R | 0h | Queue <m> Peek portal (where m = 0 to 15). |
MII_G_RT_QUEUE_CNTk is shown in Figure 6-879 and described in Table 6-1750.
Return to Summary Table.
Queue Count<k>
Offset = E40h + (k * 4h); where k = 0h to 3Fh
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3E40h + formula |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3E40h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE_CNT_ENTRIESk | |||||||||||||||
R-0h | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | QUEUE_CNT_ENTRIESk | R | 0h | Queue Entry Count<k> (where k = 0 to 63). |
MII_G_RT_QUEUE_RESET is shown in Figure 6-880 and described in Table 6-1752.
Return to Summary Table.
Queue Reset
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 3003 3F40h |
PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G | 300B 3F40h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESET_QUEUE_ID | ||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5-0 | RESET_QUEUE_ID | R/W | 0h | Reset Queue ID. |