SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
In controller mode, the baud rate of the MCSPI serial clock is programmable.
An internal reference clock, SPICLKREF, is used as input of a programmable divider (the MCSPI_CHCONF_0/1/2/3[5-2] CLKD bit field) to generate the bit rate of the serial output clock SPICLK. Table 12-335 summarizes the supported divisor values.
Divider | Clock Rate |
---|---|
1 | 50 MHz(1) |
2 | 25 MHz(1) |
4 | 12.5 MHz |
8 | 6.25 MHz |
16 | 3.125 MHz |
32 | 1.5625 MHz |
64 | 781.25 kHz |
128 | 390 kHz(2) |
256 | 195 kHz(2) |
512 | 97.7 kHz(2) |
1024 | 48.8 kHz(2) |
2048 | 24.4 kHz(2) |
4096 | 12.2 kHz(2) |
8192 and higher: Division not supported | – |