SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Offset | Length | Acronym | Register Name | FSITX0 | FSITX1 | Section |
---|---|---|---|---|---|---|
0 h | 1 | TX_MASTER_CTRL | TX_MASTER_CTRL | 2360 0000 h | 2361 0000 h | Go To |
2 h | 1 | RESERVED | Reserved | 2360 0002 h | 2361 0002 h | Go To |
4 h | 1 | TX_CLK_CTRL | TX_CLK_CTRL | 2360 0004 h | 2361 0004 h | Go To |
6 h | 1 | RESERVED | Reserved | 2360 0006 h | 2361 0006 h | Go To |
8 h | 1 | TX_OPER_CTRL_LO_ALT1_ | TX_OPER_CTRL_LO_ALT1_ | 2360 0008 h | 2361 0008 h | Go To |
A h | 1 | TX_OPER_CTRL_HI_ALT1_ | TX_OPER_CTRL_HI_ALT1_ | 2360 000A h | 2361 000A h | Go To |
C h | 1 | TX_FRAME_CTRL | TX_FRAME_CTRL | 2360 000C h | 2361 000C h | Go To |
E h | 1 | TX_FRAME_TAG_UDATA | TX_FRAME_TAG_UDATA | 2360 000E h | 2361 000E h | Go To |
10 h | 1 | TX_BUF_PTR_LOAD | TX_BUF_PTR_LOAD | 2360 0010 h | 2361 0010 h | Go To |
12 h | 1 | TX_BUF_PTR_STS | TX_BUF_PTR_STS | 2360 0012 h | 2361 0012 h | Go To |
14 h | 1 | TX_PING_CTRL_ALT1_ | TX_PING_CTRL_ALT1_ | 2360 0014 h | 2361 0014 h | Go To |
16 h | 1 | TX_PING_TAG | TX_PING_TAG | 2360 0016 h | 2361 0016 h | Go To |
18 h | 1 | TX_PING_TO_REF | TX_PING_TO_REF | 2360 0018 h | 2361 0018 h | Go To |
1C h | 1 | TX_PING_TO_CNT | TX_PING_TO_CNT | 2360 001C h | 2361 001C h | Go To |
20 h | 1 | TX_INT_CTRL | TX_INT_CTRL | 2360 0020 h | 2361 0020 h | Go To |
22 h | 1 | TX_DMA_CTRL | TX_DMA_CTRL | 2360 0022 h | 2361 0022 h | Go To |
24 h | 1 | TX_LOCK_CTRL | TX_LOCK_CTRL | 2360 0024 h | 2361 0024 h | Go To |
26 h | 1 | RESERVED | Reserved | 2360 0026 h | 2361 0026 h | Go To |
28 h | 1 | TX_EVT_STS | TX_EVT_STS | 2360 0028 h | 2361 0028 h | Go To |
2A h | 1 | RESERVED | Reserved | 2360 002A h | 2361 002A h | Go To |
2C h | 1 | TX_EVT_CLR | TX_EVT_CLR | 2360 002C h | 2361 002C h | Go To |
2E h | 1 | TX_EVT_FRC | TX_EVT_FRC | 2360 002E h | 2361 002E h | Go To |
30 h | 1 | TX_USER_CRC | TX_USER_CRC | 2360 0030 h | 2361 0030 h | Go To |
32 h | 1 | RESERVED | Reserved | 2360 0032 h | 2361 0032 h | Go To |
34 h | 1 | RESERVED | Reserved | 2360 0034 h | 2361 0034 h | Go To |
38 h | 1 | RESERVED | Reserved | 2360 0038 h | 2361 0038 h | Go To |
3C h | 1 | RESERVED | Reserved | 2360 003C h | 2361 003C h | Go To |
40 h | 1 | TX_ECC_DATA | TX_ECC_DATA | 2360 0040 h | 2361 0040 h | Go To |
44 h | 1 | TX_ECC_VAL | TX_ECC_VAL | 2360 0044 h | 2361 0044 h | Go To |
46 h | 29 | RESERVED | Reserved | 2360 0046 h | 2361 0046 h | Go To |
80 h | 16 | TX_BUF_BASE | TX_BUF_BASE | 2360 0080 h | 2361 0080 h | Go To |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0000 h |
FSITX1 | 2361 0000 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED_1 | FLUSH | CORE_RST | ||||||||||||
W | R | R/W | R/W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | KEY | W | 0h | Write Key[[br]]In order to write to any bit in this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. |
7 - 2 | RESERVED_1 | R | 0h | Reserved |
1 | FLUSH | R/W | 0h | Flush Operation Start bit[[br]]This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the Transmitter core is turned on. [[br]] [[br]]0h [R/W] = Clear this bit.[[br]]1h [R/W] = Setting this bit will Initiate flush sequence.[[br]] [[br]]To properly execute a flush sequence, Set FLUSH to 1, wait for five TXCLK cycles then clear FLUSH to 0.[[br]] [[br]]Note: The KEY field must contain 0xA5 for any write to this bit to take effect. The software must keep this bit set to 1 for at least five TXCLK cycles before setting it back to 0. |
0 | CORE_RST | R/W | 0h | Transmitter Master Core Reset bit[[br]]This bit controls the transmitter master core reset. In order to send any frame, this bit must be cleared.[[br]] [[br]]0h [R/W] = Transmitter core is not in reset and can transmit frames.[[br]]1h [R/W] = Transmitter core is held in reset. [[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0004 h |
FSITX1 | 2361 0004 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PRESCALE_VAL | CLK_EN | CLK_RST | ||||||||||||
R | R/W | R/W | R/W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 10 | RESERVED_1 | R | 0h | Reserved |
9 - 2 | PRESCALE_VAL | R/W | 0h | Clock Divider Prescale Value[[br]]The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate.[[br]] [[br]]0h [R/W] = Reserved[[br]]1h [R/W] = Input clock /1[[br]]2h [R/W] = Input clock /2[[br]]3h [R/W] = Input clock /3[[br]]4h [R/W] = Input clock /4[[br]]...[[br]]FFh [R/W] = Input clock /255[[br]] [[br]]TXCLKIN = Input clock / PRESCALE_VAL[[br]]In FSI mode: TXCLK = TXCLKIN / 2[[br]]In SPI mode: TXCLK = TXCLKIN |
1 | CLK_EN | R/W | 0h | Clock Divider Enable bit[[br]]This bit will enable and disable the input clock divider and start the clock to the transmitter core.[[br]] [[br]]0h [R/W] = The input clock divider is not enabled and the clock is not connected to the transmitter core.[[br]]1h [R/W] = The input clock to the transmitter core is being divided by the PRESCALE_VAL and enabled. |
0 | CLK_RST | R/W | 0h | Clock Divider Reset bit[[br]]This bit will reset the clock counter in the clock divider. [[br]] [[br]]0h [R/W] = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set.[[br]]1h [R/W] = The clock divider will be reset to 0 and will stay reset until software writes a 0 to this bit. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0008 h |
FSITX1 | 2361 0008 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | TDM_ENABLE | SEL_PLLCLK | PING_TO_MODE | SW_CRC | START_MODE | SPI_MODE | DATA_WIDTH | ||||||||
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 10 | RESERVED_1 | R | 0h | Reserved |
9 | TDM_ENABLE | R/W | 0h | Transmit TDM Mode Enable bit.[[br]]This bit enables the TDM Mode for multi-slave TDM operation.[[br]] [[br]]0h [R/W] Transmit TDM Mode is not enabled.[[br]]1h [R/W] Transmit TDM Mode is enabled. |
8 | SEL_PLLCLK | R/W | 0h | Input Clock Select bit[[br]]This bit selects the input clock source for the transmitter core.[[br]] [[br]]0h [R/W] = SYSCLK is the source of the transmitter clock into the clock prescaler.[[br]]1h [R/W] = PLLRAWCLK is the source of the transmitter core clock into the clock prescaler. |
7 | PING_TO_MODE | R/W | 0h | Ping Counter Reset Mode Select bit[[br]]This bit selects when the ping counter will reset.[[br]] [[br]]0h [R/W] = The ping counter will reset and restart only on hardware initiated ping frames, when ping counter has timed out.[[br]]1h [R/W] = The ping counter will reset and restart on any software initiated frame as well as a ping counter timeout |
6 | SW_CRC | R/W | 0h | CRC Source Select bit[[br]]This bit selects the source of the CRC value that is transmitted. [[br]] [[br]]0h [R/W] = The transmitted CRC value is computed by hardware.[[br]]1h [R/W] = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC register. |
5 - 3 | START_MODE | R/W | 0h | Transmission Start Mode Select bit[[br]]These bits select the method by which a new frame transmission is started.[[br]] [[br]]0h [R/W] = Only a software write to TX_FRAME_CTRL.START initiate a new transmission.[[br]]1h [R/W] = The configured external trigger will initiate a new transmission.[[br]]2h [R/W] = Either writing to TX_FRAME_CTRL.START or the TX_FRAME_TAG_UDATA register will initiate a new transmission.[[br]] [[br]]All other combinations of bits are illegal and reserved for future use. |
2 | SPI_MODE | R/W | 0h | SPI Mode Select bit[[br]]This bit enables and disables SPI compatibility mode.[[br]] [[br]]0h [R/W] = FSI is in normal mode of operation.[[br]]1h [R/W] = FSI is operating in SPI compatibility mode. |
1 - 0 | DATA_WIDTH | R/W | 0h | Transmit Data Width Select bits[[br]]These bits define the number of data lines used by the transmitter.[[br]] [[br]]0h [R/W] = Data will be transmitted on one data line [TXD0][[br]]1h [R/W] = Data will be transmitted on two data lines [TXD0 and TXD1]. The format of the data is described in the preceeding chapter.[[br]]2h, 3h [R/W] = Reserved |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 000A h |
FSITX1 | 2361 000A h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | EXT_TRIG_SEL | ECC_SEL | FORCE_ERR | RESERVED_1 | |||||||||||
R | R/W | R/W | R/W | R | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 13 | RESERVED_2 | R | 0h | Reserved |
12 - 7 | EXT_TRIG_SEL | R/W | 0h | External Trigger Select bit[[br]]These bits define which of the 32 external inputs will be used as the source for the external input trigger.[[br]] [[br]]00h [R/W] = Trigger 1 is the source.[[br]]01h [R/W] = Trigger 2 is the source.[[br]]02h [R/W] = Trigger 3 is the source.[[br]]...[[br]]3Fh [R/W] = Trigger 64 is the source. |
6 | ECC_SEL | R/W | 0h | ECC Data Width Select bit[[br]]This bit selects between 16-bit and 32-bit ECC computation. [[br]] [[br]]0h [R/W] = 32-bit ECC is used.[[br]]1h [R/W] = 16-bit ECC is used. |
5 | FORCE_ERR | R/W | 0h | Error Frame Force bit[[br]]This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The receiver will treat the data as invalid and can handle this as needed.[[br]]Note: DO NOT use FORCE_ERR if using the SW CRC mode [FSI Transmit].[[br]] [[br]]0h [R/W] = The CRC will not be forced to 0.[[br]]1h [R/W] = The CRC will be forced to 0 in a buffer overrun or underrun condition. |
4 - 0 | RESERVED_1 | R | 0h | Reserved |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 000C h |
FSITX1 | 2361 000C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START | RESERVED_1 | N_WORDS | FRAME_TYPE | ||||||||||||
R/W | R | R/W | R/W | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 | START | R/W | 0h | Start Transmission bit[[br]]This bit will cause the FSI to start transmitting the next frame.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit will have no effect.[[br]]1h [R/W] = Start the next transmission. This bit will be cleared by hardware. |
14 - 8 | RESERVED_1 | R | 0h | Reserved |
7 - 4 | N_WORDS | R/W | 0h | Number of Words to be Transmitted[[br]]This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than the number of words to be transmitted.[[br]] [[br]]0h [R/W] = 1 data word frame [16-bit data].[[br]]1h [R/W] = 2 data word frame [32-bit data].[[br]]..[[br]]Fh [R/W] = 16 data word frame [256-bit data]. |
3 - 0 | FRAME_TYPE | R/W | 0h | Transmit Frame Type[[br]]This field determines the type of frame that will be transmitted next.[[br]] [[br]]0000b [R/W] = Ping Frame. This frame can be sent either by software or automatically by hardware.[[br]]0100b [R/W] = DATA_1_WORD Frame. One word data frame [16-bit data].[[br]]0101b [R/W] = DATA_2_WORD Frame. Two word data frame [32-bit data].[[br]]0110b [R/W] = DATA_4_WORD Frame. Four word data frame [64-bit data]. [[br]]0111b [R/W] = DATA_6_WORD Frame. Six word data frame [96-bit data].[[br]]0011b [R/W] = DATA_N_WORD Frame. The N_WORDS field will determine the number of words [1 to 16] to be sent. Both the transmitter and receiver must have the same value programmed.[[br]]1111b [R/W] = Error Frame. This frame can be used during error conditions or any condition where the transmitter wants to notify the receiver of a high priorty status. However, the user software is at liberty to use this for any purpose.[[br]] [[br]]0001b, 0010b, and 1000b through 1110b are Reserved and should not be used. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 000E h |
FSITX1 | 2361 000E h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_DATA | RESERVED_1 | FRAME_TAG | |||||||||||||
R/W | R | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | USER_DATA | R/W | 0h | User Data bits[[br]]This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior. |
7 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | FRAME_TAG | R/W | 0h | This will be used only for software initiated transmissions.[[br]]Frame tag bits[[br]]This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This value will not impact any hardware behavior[[br]] [[br]]For external triggers do not use this register. Use the TX_PING_TAG register instead. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0010 h |
FSITX1 | 2361 0010 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | BUF_PTR_LOAD | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | BUF_PTR_LOAD | R/W | 0h | Buffer Pointer Load bits[[br]]These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be reflected in TX_BUF_PTR_STS only after a minimum 3 SYSCLK cycles + 3 TXCLK cycles.[[br]] [[br]]This value should not be written while there is an active transmission as it may corrupt the ongoing frame or other undefined behavior. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0012 h |
FSITX1 | 2361 0012 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | CURR_WORD_CNT | RESERVED_1 | CURR_BUF_PTR | ||||||||||||
R | R | R | R | ||||||||||||
0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 13 | RESERVED_2 | R | 0h | Reserved |
12 - 8 | CURR_WORD_CNT | R | 0h | Words Remaining in the transmit buffer [[br]]This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission.[[br]] [[br]]Note: This value will not be valid if there is a buffer overrun or underrun condition. |
7 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | CURR_BUF_PTR | R | 0h | Current Buffer Pointer Index[[br]]This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0014 h |
FSITX1 | 2361 0014 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | EXT_TRIG_SEL | EXT_TRIG_EN | TIMER_EN | CNT_RST | |||||||||||
R | R/W | R/W | R/W | R/W | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 9 | RESERVED_1 | R | 0h | Reserved |
8 - 3 | EXT_TRIG_SEL | R/W | 0h | External Trigger Select bits[[br]]This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set.[[br]] [[br]]0h [R/W] = Trigger 1 will be used to generate a ping frame.[[br]]1h [R/W] = Trigger 2 will be used to generate a ping frame.[[br]]..[[br]]3Fh [R/W] = Trigger 64 will be used to generate a ping frame. |
2 | EXT_TRIG_EN | R/W | 0h | External Trigger Enable bit[[br]]This bit will allow the external trigger logic to generate a ping frame.[[br]] [[br]]0h [R/W] = External triggers will not be used to generate ping frames.[[br]]1h [R/W] = The selected external trigger [selected by EXT_TRIG_SEL bits] will be able to generate a ping frame. The ping timer will be ignored if this bit is set. |
1 | TIMER_EN | R/W | 0h | Ping Timer Enable bit[[br]]This bit will enable the ping timer for generating periodic ping frames.[[br]] [[br]]0h [R/W] = The ping timer is disabled and will not generate ping frames.[[br]]1h [R/W] = The ping timer is enabled and can be used to generate ping frames.Once the timer count reaches the value set by the TX_PING_TO_REF register, it will initiate a ping frame transmission. [[br]] [[br]]Note: If the ping timer is used, EXT_TRIG_EN should not be set as it will override this function. |
0 | CNT_RST | R/W | 0h | Ping Counter Reset bit[[br]]This bit will reset the the ping counter to 0. This bit will always be read as 0.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit has no effect.[[br]]1h [R/W] = The ping counter will be reset to 0. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0016 h |
FSITX1 | 2361 0016 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | TAG | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 - 0 | TAG | R/W | 0h | Ping Frame Tag[[br]]This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is generated manually, the transmitted tag will be from TX_FRAME_TAG_UDATA.FRAME_TAG, not this value. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0018 h |
FSITX1 | 2361 0018 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TO_REF | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO_REF | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | TO_REF | R/W | 0h | Ping Timer Reference Value.[[br]]This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached, it will generate a timeout event, triggering a ping frame transmission. The counter will then reset to 0 and continue counting. |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 001C h |
FSITX1 | 2361 001C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TO_CNT | |||||||||||||||
R | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TO_CNT | |||||||||||||||
R | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 0 | TO_CNT | R | 0h | Ping Timer Counter Value[[br]]This register contains the current value of the ping timer counter. After reset, this counter will increment until it reaches the reference value [TX_PING_TO_REF], at which point it generates a ping frame transmission. After this point, the counter will reset to 0 and continue counting. This is a free-running counter |
(None,)
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Instance Name | Base Address |
---|---|
FSITX0 | 2360 0020 h |
FSITX1 | 2361 0020 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | INT2_EN_PING_TO | INT2_EN_BUF_OVERRUN | INT2_EN_BUF_UNDERRUN | INT2_EN_FRAME_DONE | RESERVED_1 | INT1_EN_PING_TO | INT1_EN_BUF_OVERRUN | INT1_EN_BUF_UNDERRUN | INT1_EN_FRAME_DONE | ||||||
R | R/W | R/W | R/W | R/W | R | R/W | R/W | R/W | R/W | ||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 12 | RESERVED_2 | R | 0h | Reserved |
11 | INT2_EN_PING_TO | R/W | 0h | Enable PING Timer Interrupt to INT2[[br]]This bit allows the event to generate an interrupt on the INT2 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT2.[[br]]1h [R/W] = The ping timer event will trigger an interrupt on TX_INT2. |
10 | INT2_EN_BUF_OVERRUN | R/W | 0h | Enable Buffer Overrun Interrupt to INT2[[br]]This bit allows the event to generate an interrupt on the INT2 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT2.[[br]]1h [R/W] = A Buffer Overrun condition will trigger an interrupt on TX_INT2. |
9 | INT2_EN_BUF_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT2[[br]]This bit allows the event to generate an interrupt on the INT2 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT2.[[br]]1h [R/W] = A Buffer Underrun condition will trigger an interrupt on TX_INT2. |
8 | INT2_EN_FRAME_DONE | R/W | 0h | Enable Frame Done interrupt to INT2[[br]]This bit allows the event to generate an interrupt on the INT2 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT2.[[br]]1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT2. |
7 - 4 | RESERVED_1 | R | 0h | Reserved |
3 | INT1_EN_PING_TO | R/W | 0h | Enable Ping Timer Interrupt to INT1[[br]]This bit allows the event to generate an interrupt on the INT1 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT1.[[br]]1h [R/W] = The ping timer event will trigger an interrupt on TX_INT1. |
2 | INT1_EN_BUF_OVERRUN | R/W | 0h | Enable Buffer Overrun Interrupt to INT1[[br]]This bit allows the event to generate an interrupt on the INT1 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT1.[[br]]1h [R/W] = A Buffer Overrun condition will trigger an interrupt on TX_INT1. |
1 | INT1_EN_BUF_UNDERRUN | R/W | 0h | Enable Buffer Underrun Interrupt to INT1[[br]]This bit allows the event to generate an interrupt on the INT1 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT1.[[br]]1h [R/W] = A Buffer Underrun condition will trigger an interrupt on TX_INT1. |
0 | INT1_EN_FRAME_DONE | R/W | 0h | Enable Frame Done interrupt to INT1[[br]]This bit allows the event to generate an interrupt on the INT1 line.[[br]] [[br]]0h [R/W] = This event will not trigger an interrupt on TX_INT1.[[br]]1h [R/W] = A Frame Done event will trigger an interrupt on TX_INT1. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0022 h |
FSITX1 | 2361 0022 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | DMA_EVT_EN | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 1 | RESERVED_1 | R | 0h | Reserved |
0 | DMA_EVT_EN | R/W | 0h | DMA Event Enable bit[[br]]This bit will enable the DMA event to be generated upon the completion of a transmit frame.[[br]] [[br]]0h [R/W] = A DMA event will not be generated.[[br]]1h [R/W] = A DMA event will be generated upon the completion of a transmitted frame. [[br]] [[br]]Note: The DMA event will only be generated for data frames. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0024 h |
FSITX1 | 2361 0024 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED_1 | LOCK | |||||||||||||
W | R | R/W | |||||||||||||
0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | KEY | W | 0h | Write Key[[br]]In order to write to this register, 0xA5 must be written to this field at the same time. Otherwise, writes are ignored. The key is cleared immediately after writing, so it must be written again for every change to this register. |
7 - 1 | RESERVED_1 | R | 0h | Reserved |
0 | LOCK | R/W | 0h | Control Register Lock Enable bit[[br]]This bit locks the contents of all the transmit control registers that support a lock protection. Once locked, further writes will not take effect until a SYSRS has reset this register. Once set, further writes to this bit will be ignored.[[br]] [[br]]0h [R/W] = Transmit control registers can be modified and are not locked.[[br]]1h [R/W] = Transmit control registers are locked and cannot be modified until this bit is cleared by SYSRS. Any further writes to this bit are ignored.[[br]] [[br]]Note: The KEY field must contatin 0xA5 for any write to this bit to take effect. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0028 h |
FSITX1 | 2361 0028 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||||||||||
R | R | R | R | R | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 | PING_TRIGGERED | R | 0h | Ping Frame Triggered Flag Bit[[br]]This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing to the TX_EVT_FRC register. [[br]] [[br]]0h [R] = A ping frame has not been triggered.[[br]]1h [R] = A ping frame has been triggered by either the ping timer or external trigger.[[br]] [[br]]To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
2 | BUF_OVERRUN | R | 0h | Buffer Overrun Flag Bit[[br]]This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. [[br]] [[br]]0h [R] = Buffer Overrun has not occured.[[br]]1h [R] = Buffer Overrun has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
1 | BUF_UNDERRUN | R | 0h | Buffer Underrun Flag Bit[[br]]This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. [[br]] [[br]]0h [R] = Buffer Underrun has not occured.[[br]]1h [R] = Buffer Underrun has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
0 | FRAME_DONE | R | 0h | Frame Done Flag Bit[[br]]This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. [[br]] [[br]]0h [R] = Frame Done condition has not occured.[[br]]1h [R] = Frame Done condition has occured.[[br]] [[br]]To clear this bit, write to the corresponding bit in the TX_EVT_CLR register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 002C h |
FSITX1 | 2361 002C h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||||||||||
R | W | W | W | W | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 | PING_TRIGGERED | W | 0h | Ping Frame Triggered Flag Clear bit[[br]]This bit clears the corresponding bit in the TX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0.[[br]] [[br]]Note: This bit may not always be cleared when writing to the corresponding TX_EVT_CLR bit. If PING_TIMEOUT MODE is configured to be 0, a hardware ping timeout may occur when another frame is actively being transmitted. In this case, if this bit still shows as 1 after the clear bit is written then the ping frame has been triggered but not serviced. This bit does not indicate that the ping frame has been completely sent, only that it has been triggered by the timeout event. |
2 | BUF_OVERRUN | W | 0h | Buffer Overrun Flag Clear bit[[br]]This bit clears the corresponding bit in the TX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. |
1 | BUF_UNDERRUN | W | 0h | Buffer Underrun Flag Clear bit[[br]]This bit clears the corresponding bit in the TX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. |
0 | FRAME_DONE | W | 0h | Frame Done Flag Clear bit[[br]]This bit clears the corresponding bit in the TX_EVT_STS register.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 002E h |
FSITX1 | 2361 002E h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PING_TRIGGERED | BUF_OVERRUN | BUF_UNDERRUN | FRAME_DONE | |||||||||||
R | W | W | W | W | |||||||||||
0 | 0 | 0 | 0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 4 | RESERVED_1 | R | 0h | Reserved |
3 | PING_TRIGGERED | W | 0h | Ping Frame Triggered Flag Force bit[[br]]This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding flag bit in the TX_EVT_STS Register. |
2 | BUF_OVERRUN | W | 0h | Buffer Overrun Flag Force bit[[br]]This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [R/W] = Writing a 0 to this bit will have no effect.[[br]]1h [R/W] = Force the corresponding flag bit in the TX_EVT_STS Register. |
1 | BUF_UNDERRUN | W | 0h | Buffer Underrun Flag Force bit[[br]]This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding flag bit in the TX_EVT_STS Register. |
0 | FRAME_DONE | W | 0h | Frame Done Flag Force bit[[br]]This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR.[[br]] [[br]]0h [W] = Writing a 0 to this bit will have no effect.[[br]]1h [W] = Force the corresponding flag bit in the TX_EVT_STS Register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0030 h |
FSITX1 | 2361 0030 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | USER_CRC | ||||||||||||||
R | R/W | ||||||||||||||
0 | 0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 8 | RESERVED_1 | R | 0h | Reserved |
7 - 0 | USER_CRC | R/W | 0h | User-defined CRC[[br]]This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option [TX_OPER_CTRL_LO.SW_CRC = 1]. This register is ignored if the hardware CRC generation is enabled. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0040 h |
FSITX1 | 2361 0040 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DATA_HIGH | |||||||||||||||
R/W | |||||||||||||||
0 | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_LOW | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 - 16 | DATA_HIGH | R/W | 0h | Upper 16 bits of ECC Data[[br]]Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a 32-bit write when needing to compute ECC for 32-bits for the full TX_ECC_DATA register. |
15 - 0 | DATA_LOW | R/W | 0h | Lower 16 bits of ECC Data[[br]]Writing to this bitfield will cause the ECC logic to compute the ECC[SEC-DED] for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when needing to compute ECC for 16-bits. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0044 h |
FSITX1 | 2361 0044 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | ECC_VAL | ||||||||||||||
R | R | ||||||||||||||
0 | 1100 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 7 | RESERVED_1 | R | 0h | Reserved |
6 - 0 | ECC_VAL | R | 12h | Computed ECC Value[[br]]This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register. |
(None,)
Return to Summary Table
Instance Name | Base Address |
---|---|
FSITX0 | 2360 0080 h |
FSITX1 | 2361 0080 h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
NONE | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASE_ADDRESS | |||||||||||||||
R/W | |||||||||||||||
0 |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
RESERVED | NONE | Reserved | ||
15 - 0 | BASE_ADDRESS | R/W | 0h | Transmit Data Buffer Base Address[[br]]This is the base address of the 16-word data buffer used by the transmitter. |
Access Type | Code | Description |
---|---|---|
W | W | Write |
R | R | Read |
R/W | R/W | Read / Write |