SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The PRU_ICSSGn Interrupt Controller (where n = 0 or 1) lines 0 through 63 are mapped to internal events which are generated by PRU_ICSSG integrated modules. Table 6-456 shows mapping of the different PRU_ICSSG internally sourced IRQ events to PRU_ICSSG0 INTC and PRU_ICSSG1 INTC interrupt lines 0 through 63.
Event Number | PRU_ICSSG Internal Interrupt Signal | Source |
---|---|---|
PRU_ICSSG0 INTC | ||
63 | Any sd_fd_zero/one_max/min(of 72) | |
62 | pr0_iep1_sync0_uint_intr_pend | PRU_ICSSG0 IEP1 |
61 | pr0_iep1_sync1_uint_intr_pend | PRU_ICSSG0 IEP1 |
60 | pr0_iep1_latch0_uint_intr_pend | PRU_ICSSG0 IEP1 |
59 | pr0_iep1_latch1_uint_intr_pend | PRU_ICSSG0 IEP1 |
58 | pr0_iep1_pdi_wd_exp_pend | PRU_ICSSG0 IEP1 |
57 | pr0_iep1_pd_wd_exp_pend | PRU_ICSSG0 IEP1 |
56 | pr0_iep1_any_cmp_cap_pend | PRU_ICSSG0 IEP1 |
55 | pr0_mii1_col and pr0_mii1_txen (external)if rgmii_col_crs_en MMR is set then in RGMII mode rgmii1_col will be mapped | |
54 | PRU1_RX_EOF | |
53 | MDIO_MII_LINK[1] | |
52 | PORT1_TX_OVERFLOW | |
51 | PORT1_TX_UNDERFLOW | |
50 | PRU1_RX_OVERFLOW | |
49 | PRU1_RX_NIBBLE_ODD | |
48 | PRU1_RX_CRC | |
47 | PRU1_RX_SOF | |
46 | PRU1_RX_SFD | |
45 | PRU1_RX_ERR32 | |
44 | PRU1_RX_ERR | |
43 | pr0_mii0_col and pr0_mii0_txen (external)if rgmii_col_crs_en MMR is set then in RGMII mode rgmii0_col will be mapped | |
42 | PRU0_RX_EOF | |
41 | MDIO_MII_LINK[0] | |
40 | PORT0_TX_OVERFLOW | |
39 | PORT0_TX_UNDERFLOW | |
38 | PRU0_RX_OVERFLOW | |
37 | PRU0_RX_NIBBLE_ODD | |
36 | PRU0_RX_CRC | |
35 | PRU0_RX_SOF | |
34 | PRU0_RX_SFD | |
33 | PRU0_RX_ERR32 | PRU_ICSSG0 PRU0 |
32 | PRU0_RX_ERR | PRU_ICSSG0 PRU0 |
31 | pr0_pru_mst_intr[15]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
30 | pr0_pru_mst_intr[14]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
29 | pr0_pru_mst_intr[13]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
28 | pr0_pru_mst_intr[12]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
27 | pr0_pru_mst_intr[11]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
26 | pr0_pru_mst_intr[10]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
25 | pr0_pru_mst_intr[9]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
24 | pr0_pru_mst_intr[8]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
23 | pr0_pru_mst_intr[7]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
22 | pr0_pru_mst_intr[6]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
21 | pr0_pru_mst_intr[5]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
20 | pr0_pru_mst_intr[4]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
19 | pr0_pru_mst_intr[3]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
18 | pr0_pru_mst_intr[2]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
17 | pr0_pru_mst_intr[1]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
16 | pr0_pru_mst_intr[0]_intr_req | PRU_ICSSG0 PRU0, PRU_ICSSG0 PRU1 |
15 | pr0_ecap_intr_req | PRU_ICSSG0 ECAP0 |
14 | pr0_sync0_out_pend | PRU_ICSSG0 IEP0 |
13 | pr0_sync1_out_pend | PRU_ICSSG0 IEP0 |
12 | pr0_latch0_in (input to PRU_ICSSG0) | PRU_ICSSG0 IEP0 |
11 | pr0_latch1_in (input to PRU_ICSSG0) | PRU_ICSSG0 IEP0 |
10 | pr0_pdi_wd_exp_pend | PRU_ICSSG0 IEP0 |
9 | pr0_pd_wd_exp_pend | PRU_ICSSG0 IEP0 |
8 | pr0_digio_event_req | PRU_ICSSG0 IEP0 |
7 | pr0_iep_tim_cap_cmp_pend | PRU_ICSSG0 IEP0 |
6 | pr0_uart0_uint_intr_req | PRU_ICSSG0 UART0 |
5 | pr0_uart0_utxevt_intr_req | PRU_ICSSG0 UART0 |
4 | pr0_uart0_urxevt_intr_req | PRU_ICSSG0 UART0 |
3 | pr0_rst_reset_iso_req | PRU_ICSSG0 Reset Isolation Requested |
2 | pr0_pru1_r31_status_cnt16 | PRU_ICSSG0 PRU1 (Shift Capture) |
1 | pr0_pru0_r31_status_cnt16 | PRU_ICSSG0 PRU0 (Shift Capture) |
0 | pr0_ecc_err_intr | PRU_ICSSG0 ECC Logic |
PRU_ICSSG1 INTC | ||
63 | Any sd_fd_zero/one_max/min(of 72) | |
62 | pr1_iep1_sync0_uint_intr_pend | PRU_ICSSG1 IEP1 |
61 | pr1_iep1_sync1_uint_intr_pend | PRU_ICSSG1 IEP1 |
60 | pr1_iep1_latch0_uint_intr_pend | PRU_ICSSG1 IEP1 |
59 | pr1_iep1_latch1_uint_intr_pend | PRU_ICSSG1 IEP1 |
58 | pr1_iep1_pdi_wd_exp_pend | PRU_ICSSG1 IEP1 |
57 | pr1_iep1_pd_wd_exp_pend | PRU_ICSSG1 IEP1 |
56 | pr1_iep1_any_cmp_cap_pend | PRU_ICSSG1 IEP1 |
55 | pr1_mii1_col and pr1_mii1_txen (external)if rgmii_col_crs_en MMR is set then in RGMII mode rgmii1_col will be mapped | |
54 | PRU1_RX_EOF | |
53 | MDIO_MII_LINK[1] | |
52 | PORT1_TX_OVERFLOW | |
51 | PORT1_TX_UNDERFLOW | |
50 | PRU1_RX_OVERFLOW | |
49 | PRU1_RX_NIBBLE_ODD | |
48 | PRU1_RX_CRC | |
47 | PRU1_RX_SOF | |
46 | PRU1_RX_SFD | |
45 | PRU1_RX_ERR32 | |
44 | PRU1_RX_ERR | |
43 | pr1_mii0_col and pr1_mii0_txen (external)if rgmii_col_crs_en MMR is set then in RGMII mode rgmii0_col will be mapped | |
42 | PRU0_RX_EOF | |
41 | MDIO_MII_LINK[0] | |
40 | PORT0_TX_OVERFLOW | |
39 | PORT0_TX_UNDERFLOW | |
38 | PRU0_RX_OVERFLOW | |
37 | PRU0_RX_NIBBLE_ODD | |
36 | PRU0_RX_CRC | |
35 | PRU0_RX_SOF | |
34 | PRU0_RX_SFD | |
33 | PRU0_RX_ERR32 | PRU_ICSSG1 PRU0 |
32 | PRU0_RX_ERR | PRU_ICSSG1 PRU0 |
31 | pr1_pru_mst_intr[15]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
30 | pr1_pru_mst_intr[14]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
29 | pr1_pru_mst_intr[13]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
28 | pr1_pru_mst_intr[12]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
27 | pr1_pru_mst_intr[11]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
26 | pr1_pru_mst_intr[10]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
25 | pr1_pru_mst_intr[9]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
24 | pr1_pru_mst_intr[8]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
23 | pr1_pru_mst_intr[7]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
22 | pr1_pru_mst_intr[6]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
21 | pr1_pru_mst_intr[5]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
20 | pr1_pru_mst_intr[4]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
19 | pr1_pru_mst_intr[3]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
18 | pr1_pru_mst_intr[2]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
17 | pr1_pru_mst_intr[1]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
16 | pr1_pru_mst_intr[0]_intr_req | PRU_ICSSG1 PRU0, PRU_ICSSG1 PRU1 |
15 | pr1_ecap_intr_req | PRU_ICSSG1 ECAP0 |
14 | pr1_sync0_out_pend | PRU_ICSSG1 IEP0 |
13 | pr1_sync1_out_pend | PRU_ICSSG1 IEP0 |
12 | pr1_latch0_in (input to PRU_ICSSG1) | PRU_ICSSG1 IEP0 |
11 | pr1_latch1_in (input to PRU_ICSSG1) | PRU_ICSSG1 IEP0 |
10 | pr1_pdi_wd_exp_pend | PRU_ICSSG1 IEP0 |
9 | pr1_pd_wd_exp_pend | PRU_ICSSG1 IEP0 |
8 | pr1_digio_event_req | PRU_ICSSG1 IEP0 |
7 | pr1_iep_tim_cap_cmp_pend | PRU_ICSSG1 IEP0 |
6 | pr1_uart0_uint_intr_req | PRU_ICSSG1 UART0 |
5 | pr1_uart0_utxevt_intr_req | PRU_ICSSG1 UART0 |
4 | pr1_uart0_urxevt_intr_req | PRU_ICSSG1 UART0 |
3 | pr1_rst_reset_iso_req | PRU_ICSSG1 Reset Isolation Requested |
2 | pr1_pru1_r31_status_cnt16 | PRU_ICSSG1 PRU1 (Shift Capture) |
1 | pr1_pru0_r31_status_cnt16 | PRU_ICSSG1 PRU0 (Shift Capture) |
0 | pr1_ecc_err_intr | PRU_ICSSG1 ECC Logic |
The IRQ input lines 64 through 159 receive interrupts which come from various device peripherals located outside PRU_ICSSG system. They are delivered on the PRU_ICSSG Interrupt Controller inputs (64 through 159).