Each PRU_ICSSG subsystems includes Spinlock controller/target
interfaces to allow fast signaling and resource sharing within and between PRU_ICSSG
subsystems.
Supported Features:
- 64 ownership flags (shared by SLICE0 and SLICE1 within an PRU_ICSSG subsystem) with support of 14 initiators, including:
- 6 Internal PRU cores:
- PRU0/1, RTU_PRU0/1 and TX_PRU0/1 cores
- 2 clock cycle response of Spinlock status
- 2 External Host register access:
- 6 External PRU cores:
- One External PRU_ICSSG with 6 PRU cores
- With flexible external pipeline for SoC timing closer
- Allows the sharing of flags across PRU_ICSSG systms
- 4 to 6 clock cycle response
- Fixed arbitration
- Flag selection through ICSSG_SPIN_LOCK0/1[13-8] MMR_OWN_REQ_VECTOR_0/1 bit field:
- PRU, RTU_PRU and TX_PRU cores use R1.b0 register, which is snooped or continually monitored by the Spinlock. XOUT of this register is not required. XIN of R1.b0 causes arbitration action.
- Each Host uses one 32-bit addressable space
- Vector write (through ICSSG_SPIN_LOCK0/1[13-8] MMR_OWN_REQ_VECTOR_0/1) or status read (through ICSSG_SPIN_LOCK0/1[0] MMR_OWN_REQ_STATUS_0/1) will cause arbitration action