SPRUIM2H May   2020  – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Glossary
    3.     Related Documentation From Texas Instruments
    4.     6
    5.     Support Resources
    6.     Trademarks
    7.     Export Control Notice
  3. 1 Introduction
    1. 1.1 Device Overview
    2.     12
    3. 1.2 Functional Block Diagram
      1. 1.2.1 Module Allocation and Instances within Device Domains
    4. 1.3 Device MAIN Domain
      1. 1.3.1  Arm Cortex-A53 Subsystem (A53SS)
      2.      Arm Cortex-R5F Processor (R5FSS)
      3. 1.3.2  Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      4. 1.3.3  DDR 16-bit Subsystem (DDR16)
      5. 1.3.4  Region-based Address Translation Module (RAT)
      6. 1.3.5  Data Movement Subsystem (DMSS)
      7. 1.3.6  Mailbox (MAILBOX)
      8. 1.3.7  Spinlock (SPINLOCK)
      9. 1.3.8  Analog-to-Digital Converter (ADC)
      10. 1.3.9  General Purpose Input/Output Interface (GPIO)
      11. 1.3.10 Inter-Integrated Circuit Interface (I2C)
      12. 1.3.11 Serial Peripheral Interface (SPI)
      13. 1.3.12 Universal Asynchronous Receiver/Transmitter (UART)
      14. 1.3.13 3-port Gigabit Ethernet Switch (CPSW3G)
      15. 1.3.14 Peripheral Component Interconnect Express Subsystem (PCIE)
      16. 1.3.15 Serializer/Deserializer (SERDES)
      17. 1.3.16 Universal Serial Bus 3.1 Subsystem (USBSS)
      18. 1.3.17 General Purpose Memory Controller (GPMC)
      19. 1.3.18 Error Location Module (ELM)
      20. 1.3.19 Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
      21. 1.3.20 Multi-Media Card/Secure Digital Interface (MMCSD)
      22. 1.3.21 Enhanced Capture Module (ECAP)
      23. 1.3.22 Enhanced Pulse-Width Modulation Module (EPWM)
      24. 1.3.23 Enhanced Quadrature Encoder Pulse Module (EQEP)
      25. 1.3.24 Controller Area Network (MCAN)
      26. 1.3.25 Fast Serial Interface Receiver (FSI_RX)
      27. 1.3.26 Fast Serial Interface Transmitter (FSI_TX)
      28. 1.3.27 Timers
      29. 1.3.28 Internal Diagnostics Modules
    5. 1.4 Device MCU Domain
      1. 1.4.1 MCU Arm Cortex M4F Subsystem (MCU_M4FSS)
      2. 1.4.2 MCU General Purpose Input/Output Interface (MCU_GPIO)
      3. 1.4.3 MCU Inter-Integrated Circuit Interface (MCU_I2C)
      4. 1.4.4 MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
      5. 1.4.5 MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
      6. 1.4.6 MCU Timers
      7. 1.4.7 MCU Internal Diagnostics Modules
    6. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 Processors View Memory Map
    4. 2.4 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1  Terminology
    2. 3.2  System Interconnect Overview
    3. 3.3  Initiator/Target Connectivity
    4. 3.4  Interrupt Condition for Interconnect
    5. 3.5  IO Coherency Support
    6. 3.6  Quality of Service (QoS) Block
      1.      66
    7. 3.7  Route ID
      1.      68
    8. 3.8  ISC and Firewall
      1. 3.8.1 Initiator-Side Security Controls (ISC)
        1.       71
        2. 3.8.1.1 ISC MMR
      2. 3.8.2 Transaction Attributes for BCDMA and PktDMA Transactions
      3. 3.8.3 Firewall Block
        1.       75
        2. 3.8.3.1 Region Based Firewall Programming
    9. 3.9  System Interconnect Integration
      1. 3.9.1 Interconnect Integration in MAIN/MCU Domain
    10. 3.10 System Interconnect Registers
      1. 3.10.1 CBASS Registers
        1. 3.10.1.1    ERR_PID Registers
        2. 3.10.1.2    ERR_DESTINATION_ID Registers
        3. 3.10.1.3    ERR_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.1.4    ERR_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.1.5    ERR_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.1.6    ERR_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.1.7    ERR_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.1.8    ERR_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.1.9    ERR_ERR_INTR_RAW_STAT Registers
        10. 3.10.1.10   ERR_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.1.11   ERR_ERR_INTR_ENABLE_SET Registers
        12. 3.10.1.12   ERR_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.1.13   ERR_EOI Registers
        14. 3.10.1.14   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_CONTROL Registers
        15. 3.10.1.15   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.1.16   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.1.17   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.1.18   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.1.19   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.1.20   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.1.21   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.1.22   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_CONTROL Registers
        23. 3.10.1.23   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.1.24   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.1.25   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.1.26   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.1.27   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.1.28   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.1.29   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.1.30   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_CONTROL Registers
        31. 3.10.1.31   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.1.32   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.1.33   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.1.34   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.1.35   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.1.36   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.1.37   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.1.38   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_CONTROL Registers
        39. 3.10.1.39   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.1.40   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.1.41   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.1.42   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.1.43   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.1.44   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.1.45   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.1.46   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_CONTROL Registers
        47. 3.10.1.47   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.1.48   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.1.49   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.1.50   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.1.51   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.1.52   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.1.53   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.1.54   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_CONTROL Registers
        55. 3.10.1.55   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.1.56   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.1.57   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.1.58   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.1.59   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.1.60   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.1.61   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.1.62   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_CONTROL Registers
        63. 3.10.1.63   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.1.64   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.1.65   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.1.66   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.1.67   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.1.68   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.1.69   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.1.70   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_CONTROL Registers
        71. 3.10.1.71   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.1.72   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.1.73   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.1.74   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.1.75   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.1.76   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.1.77   FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.1.78   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_CONTROL Registers
        79. 3.10.1.79   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.1.80   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.1.81   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.1.82   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.1.83   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.1.84   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.1.85   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.1.86   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_CONTROL Registers
        87. 3.10.1.87   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.1.88   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.1.89   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.1.90   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.1.91   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.1.92   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.1.93   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.1.94   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_CONTROL Registers
        95. 3.10.1.95   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.1.96   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.1.97   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.1.98   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.1.99   FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.1.100  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.1.101  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.1.102  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_CONTROL Registers
        103. 3.10.1.103  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.1.104  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.1.105  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.1.106  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.1.107  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.1.108  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.1.109  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.1.110  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_CONTROL Registers
        111. 3.10.1.111  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.1.112  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.1.113  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.1.114  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.1.115  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.1.116  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.1.117  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.1.118  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_CONTROL Registers
        119. 3.10.1.119  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.1.120  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.1.121  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.1.122  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.1.123  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.1.124  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.1.125  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.1.126  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_CONTROL Registers
        127. 3.10.1.127  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.1.128  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.1.129  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.1.130  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.1.131  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.1.132  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.1.133  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.1.134  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_CONTROL Registers
        135. 3.10.1.135  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.1.136  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.1.137  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.1.138  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.1.139  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.1.140  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.1.141  FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.1.142  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_CONTROL Registers
        143. 3.10.1.143  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_0 Registers
        144. 3.10.1.144  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_1 Registers
        145. 3.10.1.145  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_2 Registers
        146. 3.10.1.146  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_L Registers
        147. 3.10.1.147  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_H Registers
        148. 3.10.1.148  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_L Registers
        149. 3.10.1.149  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_H Registers
        150. 3.10.1.150  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_CONTROL Registers
        151. 3.10.1.151  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_0 Registers
        152. 3.10.1.152  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_1 Registers
        153. 3.10.1.153  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_2 Registers
        154. 3.10.1.154  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_L Registers
        155. 3.10.1.155  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_H Registers
        156. 3.10.1.156  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_L Registers
        157. 3.10.1.157  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_H Registers
        158. 3.10.1.158  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_CONTROL Registers
        159. 3.10.1.159  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_0 Registers
        160. 3.10.1.160  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_1 Registers
        161. 3.10.1.161  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_2 Registers
        162. 3.10.1.162  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_L Registers
        163. 3.10.1.163  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_H Registers
        164. 3.10.1.164  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_L Registers
        165. 3.10.1.165  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_H Registers
        166. 3.10.1.166  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_CONTROL Registers
        167. 3.10.1.167  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_0 Registers
        168. 3.10.1.168  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_1 Registers
        169. 3.10.1.169  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_2 Registers
        170. 3.10.1.170  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_L Registers
        171. 3.10.1.171  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_H Registers
        172. 3.10.1.172  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_L Registers
        173. 3.10.1.173  FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_H Registers
        174. 3.10.1.174  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_CONTROL Registers
        175. 3.10.1.175  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_0 Registers
        176. 3.10.1.176  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_1 Registers
        177. 3.10.1.177  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_2 Registers
        178. 3.10.1.178  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_L Registers
        179. 3.10.1.179  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_H Registers
        180. 3.10.1.180  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_L Registers
        181. 3.10.1.181  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_H Registers
        182. 3.10.1.182  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_CONTROL Registers
        183. 3.10.1.183  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_0 Registers
        184. 3.10.1.184  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_1 Registers
        185. 3.10.1.185  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_2 Registers
        186. 3.10.1.186  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_L Registers
        187. 3.10.1.187  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_H Registers
        188. 3.10.1.188  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_L Registers
        189. 3.10.1.189  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_H Registers
        190. 3.10.1.190  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_CONTROL Registers
        191. 3.10.1.191  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_0 Registers
        192. 3.10.1.192  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_1 Registers
        193. 3.10.1.193  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_2 Registers
        194. 3.10.1.194  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_L Registers
        195. 3.10.1.195  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_H Registers
        196. 3.10.1.196  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_L Registers
        197. 3.10.1.197  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_H Registers
        198. 3.10.1.198  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_CONTROL Registers
        199. 3.10.1.199  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_0 Registers
        200. 3.10.1.200  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_1 Registers
        201. 3.10.1.201  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_2 Registers
        202. 3.10.1.202  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_L Registers
        203. 3.10.1.203  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_H Registers
        204. 3.10.1.204  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_L Registers
        205. 3.10.1.205  FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_H Registers
        206. 3.10.1.206  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_CONTROL Registers
        207. 3.10.1.207  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_0 Registers
        208. 3.10.1.208  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_1 Registers
        209. 3.10.1.209  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_2 Registers
        210. 3.10.1.210  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_L Registers
        211. 3.10.1.211  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_H Registers
        212. 3.10.1.212  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_L Registers
        213. 3.10.1.213  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_H Registers
        214. 3.10.1.214  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_CONTROL Registers
        215. 3.10.1.215  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_0 Registers
        216. 3.10.1.216  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_1 Registers
        217. 3.10.1.217  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_2 Registers
        218. 3.10.1.218  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_L Registers
        219. 3.10.1.219  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_H Registers
        220. 3.10.1.220  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_L Registers
        221. 3.10.1.221  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_H Registers
        222. 3.10.1.222  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_CONTROL Registers
        223. 3.10.1.223  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_0 Registers
        224. 3.10.1.224  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_1 Registers
        225. 3.10.1.225  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_2 Registers
        226. 3.10.1.226  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_L Registers
        227. 3.10.1.227  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_H Registers
        228. 3.10.1.228  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_L Registers
        229. 3.10.1.229  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_H Registers
        230. 3.10.1.230  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_CONTROL Registers
        231. 3.10.1.231  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_0 Registers
        232. 3.10.1.232  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_1 Registers
        233. 3.10.1.233  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_2 Registers
        234. 3.10.1.234  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_L Registers
        235. 3.10.1.235  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_H Registers
        236. 3.10.1.236  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_L Registers
        237. 3.10.1.237  FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_H Registers
        238. 3.10.1.238  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_CONTROL Registers
        239. 3.10.1.239  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_0 Registers
        240. 3.10.1.240  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_1 Registers
        241. 3.10.1.241  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_2 Registers
        242. 3.10.1.242  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_L Registers
        243. 3.10.1.243  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_H Registers
        244. 3.10.1.244  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_L Registers
        245. 3.10.1.245  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_H Registers
        246. 3.10.1.246  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_CONTROL Registers
        247. 3.10.1.247  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_0 Registers
        248. 3.10.1.248  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_1 Registers
        249. 3.10.1.249  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_2 Registers
        250. 3.10.1.250  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_L Registers
        251. 3.10.1.251  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_H Registers
        252. 3.10.1.252  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_L Registers
        253. 3.10.1.253  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_H Registers
        254. 3.10.1.254  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_CONTROL Registers
        255. 3.10.1.255  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_0 Registers
        256. 3.10.1.256  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_1 Registers
        257. 3.10.1.257  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_2 Registers
        258. 3.10.1.258  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_L Registers
        259. 3.10.1.259  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_H Registers
        260. 3.10.1.260  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_L Registers
        261. 3.10.1.261  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_H Registers
        262. 3.10.1.262  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_CONTROL Registers
        263. 3.10.1.263  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_0 Registers
        264. 3.10.1.264  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_1 Registers
        265. 3.10.1.265  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_2 Registers
        266. 3.10.1.266  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_L Registers
        267. 3.10.1.267  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_H Registers
        268. 3.10.1.268  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_L Registers
        269. 3.10.1.269  FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_H Registers
        270. 3.10.1.270  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_CONTROL Registers
        271. 3.10.1.271  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_0 Registers
        272. 3.10.1.272  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_1 Registers
        273. 3.10.1.273  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_2 Registers
        274. 3.10.1.274  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_L Registers
        275. 3.10.1.275  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_H Registers
        276. 3.10.1.276  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_L Registers
        277. 3.10.1.277  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_H Registers
        278. 3.10.1.278  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_CONTROL Registers
        279. 3.10.1.279  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_0 Registers
        280. 3.10.1.280  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_1 Registers
        281. 3.10.1.281  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_2 Registers
        282. 3.10.1.282  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_L Registers
        283. 3.10.1.283  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_H Registers
        284. 3.10.1.284  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_L Registers
        285. 3.10.1.285  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_H Registers
        286. 3.10.1.286  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_CONTROL Registers
        287. 3.10.1.287  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_0 Registers
        288. 3.10.1.288  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_1 Registers
        289. 3.10.1.289  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_2 Registers
        290. 3.10.1.290  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_L Registers
        291. 3.10.1.291  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_H Registers
        292. 3.10.1.292  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_L Registers
        293. 3.10.1.293  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_H Registers
        294. 3.10.1.294  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_CONTROL Registers
        295. 3.10.1.295  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_0 Registers
        296. 3.10.1.296  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_1 Registers
        297. 3.10.1.297  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_2 Registers
        298. 3.10.1.298  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_L Registers
        299. 3.10.1.299  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_H Registers
        300. 3.10.1.300  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_L Registers
        301. 3.10.1.301  FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_H Registers
        302. 3.10.1.302  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_CONTROL Registers
        303. 3.10.1.303  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_0 Registers
        304. 3.10.1.304  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_1 Registers
        305. 3.10.1.305  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_2 Registers
        306. 3.10.1.306  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_L Registers
        307. 3.10.1.307  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_H Registers
        308. 3.10.1.308  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_L Registers
        309. 3.10.1.309  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_H Registers
        310. 3.10.1.310  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_CONTROL Registers
        311. 3.10.1.311  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_0 Registers
        312. 3.10.1.312  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_1 Registers
        313. 3.10.1.313  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_2 Registers
        314. 3.10.1.314  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_L Registers
        315. 3.10.1.315  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_H Registers
        316. 3.10.1.316  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_L Registers
        317. 3.10.1.317  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_H Registers
        318. 3.10.1.318  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_CONTROL Registers
        319. 3.10.1.319  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_0 Registers
        320. 3.10.1.320  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_1 Registers
        321. 3.10.1.321  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_2 Registers
        322. 3.10.1.322  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_L Registers
        323. 3.10.1.323  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_H Registers
        324. 3.10.1.324  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_L Registers
        325. 3.10.1.325  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_H Registers
        326. 3.10.1.326  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_CONTROL Registers
        327. 3.10.1.327  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_0 Registers
        328. 3.10.1.328  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_1 Registers
        329. 3.10.1.329  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_2 Registers
        330. 3.10.1.330  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_L Registers
        331. 3.10.1.331  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_H Registers
        332. 3.10.1.332  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_L Registers
        333. 3.10.1.333  FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_H Registers
        334. 3.10.1.334  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_CONTROL Registers
        335. 3.10.1.335  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_0 Registers
        336. 3.10.1.336  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_1 Registers
        337. 3.10.1.337  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_2 Registers
        338. 3.10.1.338  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_L Registers
        339. 3.10.1.339  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_H Registers
        340. 3.10.1.340  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_L Registers
        341. 3.10.1.341  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_H Registers
        342. 3.10.1.342  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_CONTROL Registers
        343. 3.10.1.343  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_0 Registers
        344. 3.10.1.344  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_1 Registers
        345. 3.10.1.345  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_2 Registers
        346. 3.10.1.346  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_L Registers
        347. 3.10.1.347  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_H Registers
        348. 3.10.1.348  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_L Registers
        349. 3.10.1.349  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_H Registers
        350. 3.10.1.350  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_CONTROL Registers
        351. 3.10.1.351  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_0 Registers
        352. 3.10.1.352  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_1 Registers
        353. 3.10.1.353  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_2 Registers
        354. 3.10.1.354  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_L Registers
        355. 3.10.1.355  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_H Registers
        356. 3.10.1.356  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_L Registers
        357. 3.10.1.357  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_H Registers
        358. 3.10.1.358  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_CONTROL Registers
        359. 3.10.1.359  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_0 Registers
        360. 3.10.1.360  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_1 Registers
        361. 3.10.1.361  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_2 Registers
        362. 3.10.1.362  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_L Registers
        363. 3.10.1.363  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_H Registers
        364. 3.10.1.364  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_L Registers
        365. 3.10.1.365  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_H Registers
        366. 3.10.1.366  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_CONTROL Registers
        367. 3.10.1.367  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_0 Registers
        368. 3.10.1.368  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_1 Registers
        369. 3.10.1.369  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_2 Registers
        370. 3.10.1.370  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_L Registers
        371. 3.10.1.371  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_H Registers
        372. 3.10.1.372  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_L Registers
        373. 3.10.1.373  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_H Registers
        374. 3.10.1.374  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_CONTROL Registers
        375. 3.10.1.375  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_0 Registers
        376. 3.10.1.376  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_1 Registers
        377. 3.10.1.377  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_2 Registers
        378. 3.10.1.378  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_L Registers
        379. 3.10.1.379  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_H Registers
        380. 3.10.1.380  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_L Registers
        381. 3.10.1.381  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_H Registers
        382. 3.10.1.382  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_CONTROL Registers
        383. 3.10.1.383  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_0 Registers
        384. 3.10.1.384  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_1 Registers
        385. 3.10.1.385  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_2 Registers
        386. 3.10.1.386  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_L Registers
        387. 3.10.1.387  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_H Registers
        388. 3.10.1.388  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_L Registers
        389. 3.10.1.389  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_H Registers
        390. 3.10.1.390  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_CONTROL Registers
        391. 3.10.1.391  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_0 Registers
        392. 3.10.1.392  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_1 Registers
        393. 3.10.1.393  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_2 Registers
        394. 3.10.1.394  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_L Registers
        395. 3.10.1.395  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_H Registers
        396. 3.10.1.396  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_L Registers
        397. 3.10.1.397  FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_H Registers
        398. 3.10.1.398  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_CONTROL Registers
        399. 3.10.1.399  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_0 Registers
        400. 3.10.1.400  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_1 Registers
        401. 3.10.1.401  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_2 Registers
        402. 3.10.1.402  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_L Registers
        403. 3.10.1.403  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_H Registers
        404. 3.10.1.404  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_L Registers
        405. 3.10.1.405  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_H Registers
        406. 3.10.1.406  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_CONTROL Registers
        407. 3.10.1.407  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_0 Registers
        408. 3.10.1.408  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_1 Registers
        409. 3.10.1.409  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_2 Registers
        410. 3.10.1.410  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_L Registers
        411. 3.10.1.411  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_H Registers
        412. 3.10.1.412  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_L Registers
        413. 3.10.1.413  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_H Registers
        414. 3.10.1.414  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_CONTROL Registers
        415. 3.10.1.415  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_0 Registers
        416. 3.10.1.416  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_1 Registers
        417. 3.10.1.417  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_2 Registers
        418. 3.10.1.418  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_L Registers
        419. 3.10.1.419  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_H Registers
        420. 3.10.1.420  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_L Registers
        421. 3.10.1.421  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_H Registers
        422. 3.10.1.422  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_CONTROL Registers
        423. 3.10.1.423  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_0 Registers
        424. 3.10.1.424  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_1 Registers
        425. 3.10.1.425  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_2 Registers
        426. 3.10.1.426  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_L Registers
        427. 3.10.1.427  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_H Registers
        428. 3.10.1.428  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_L Registers
        429. 3.10.1.429  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_H Registers
        430. 3.10.1.430  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_CONTROL Registers
        431. 3.10.1.431  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_0 Registers
        432. 3.10.1.432  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_1 Registers
        433. 3.10.1.433  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_2 Registers
        434. 3.10.1.434  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_L Registers
        435. 3.10.1.435  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_H Registers
        436. 3.10.1.436  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_L Registers
        437. 3.10.1.437  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_H Registers
        438. 3.10.1.438  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_CONTROL Registers
        439. 3.10.1.439  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_0 Registers
        440. 3.10.1.440  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_1 Registers
        441. 3.10.1.441  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_2 Registers
        442. 3.10.1.442  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_L Registers
        443. 3.10.1.443  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_H Registers
        444. 3.10.1.444  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_L Registers
        445. 3.10.1.445  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_H Registers
        446. 3.10.1.446  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_CONTROL Registers
        447. 3.10.1.447  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_0 Registers
        448. 3.10.1.448  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_1 Registers
        449. 3.10.1.449  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_2 Registers
        450. 3.10.1.450  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_L Registers
        451. 3.10.1.451  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_H Registers
        452. 3.10.1.452  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_L Registers
        453. 3.10.1.453  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_H Registers
        454. 3.10.1.454  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_CONTROL Registers
        455. 3.10.1.455  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_0 Registers
        456. 3.10.1.456  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_1 Registers
        457. 3.10.1.457  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_2 Registers
        458. 3.10.1.458  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_L Registers
        459. 3.10.1.459  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_H Registers
        460. 3.10.1.460  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_L Registers
        461. 3.10.1.461  FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_H Registers
        462. 3.10.1.462  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_CONTROL Registers
        463. 3.10.1.463  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_0 Registers
        464. 3.10.1.464  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_1 Registers
        465. 3.10.1.465  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_2 Registers
        466. 3.10.1.466  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_L Registers
        467. 3.10.1.467  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_H Registers
        468. 3.10.1.468  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_L Registers
        469. 3.10.1.469  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_H Registers
        470. 3.10.1.470  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_CONTROL Registers
        471. 3.10.1.471  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_0 Registers
        472. 3.10.1.472  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_1 Registers
        473. 3.10.1.473  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_2 Registers
        474. 3.10.1.474  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_L Registers
        475. 3.10.1.475  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_H Registers
        476. 3.10.1.476  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_L Registers
        477. 3.10.1.477  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_H Registers
        478. 3.10.1.478  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_CONTROL Registers
        479. 3.10.1.479  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_0 Registers
        480. 3.10.1.480  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_1 Registers
        481. 3.10.1.481  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_2 Registers
        482. 3.10.1.482  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_L Registers
        483. 3.10.1.483  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_H Registers
        484. 3.10.1.484  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_L Registers
        485. 3.10.1.485  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_H Registers
        486. 3.10.1.486  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_CONTROL Registers
        487. 3.10.1.487  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_0 Registers
        488. 3.10.1.488  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_1 Registers
        489. 3.10.1.489  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_2 Registers
        490. 3.10.1.490  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_L Registers
        491. 3.10.1.491  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_H Registers
        492. 3.10.1.492  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_L Registers
        493. 3.10.1.493  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_H Registers
        494. 3.10.1.494  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_CONTROL Registers
        495. 3.10.1.495  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_0 Registers
        496. 3.10.1.496  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_1 Registers
        497. 3.10.1.497  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_2 Registers
        498. 3.10.1.498  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_L Registers
        499. 3.10.1.499  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_H Registers
        500. 3.10.1.500  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_L Registers
        501. 3.10.1.501  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_H Registers
        502. 3.10.1.502  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_CONTROL Registers
        503. 3.10.1.503  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_0 Registers
        504. 3.10.1.504  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_1 Registers
        505. 3.10.1.505  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_2 Registers
        506. 3.10.1.506  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_L Registers
        507. 3.10.1.507  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_H Registers
        508. 3.10.1.508  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_L Registers
        509. 3.10.1.509  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_H Registers
        510. 3.10.1.510  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_CONTROL Registers
        511. 3.10.1.511  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_0 Registers
        512. 3.10.1.512  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_1 Registers
        513. 3.10.1.513  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_2 Registers
        514. 3.10.1.514  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_L Registers
        515. 3.10.1.515  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_H Registers
        516. 3.10.1.516  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_L Registers
        517. 3.10.1.517  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_H Registers
        518. 3.10.1.518  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_CONTROL Registers
        519. 3.10.1.519  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_0 Registers
        520. 3.10.1.520  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_1 Registers
        521. 3.10.1.521  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_2 Registers
        522. 3.10.1.522  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_L Registers
        523. 3.10.1.523  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_H Registers
        524. 3.10.1.524  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_L Registers
        525. 3.10.1.525  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_H Registers
        526. 3.10.1.526  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_CONTROL Registers
        527. 3.10.1.527  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_0 Registers
        528. 3.10.1.528  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_1 Registers
        529. 3.10.1.529  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_2 Registers
        530. 3.10.1.530  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_L Registers
        531. 3.10.1.531  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_H Registers
        532. 3.10.1.532  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_L Registers
        533. 3.10.1.533  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_H Registers
        534. 3.10.1.534  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_CONTROL Registers
        535. 3.10.1.535  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_0 Registers
        536. 3.10.1.536  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_1 Registers
        537. 3.10.1.537  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_2 Registers
        538. 3.10.1.538  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_L Registers
        539. 3.10.1.539  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_H Registers
        540. 3.10.1.540  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_L Registers
        541. 3.10.1.541  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_H Registers
        542. 3.10.1.542  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_CONTROL Registers
        543. 3.10.1.543  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_0 Registers
        544. 3.10.1.544  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_1 Registers
        545. 3.10.1.545  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_2 Registers
        546. 3.10.1.546  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_L Registers
        547. 3.10.1.547  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_H Registers
        548. 3.10.1.548  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_L Registers
        549. 3.10.1.549  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_H Registers
        550. 3.10.1.550  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_CONTROL Registers
        551. 3.10.1.551  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_0 Registers
        552. 3.10.1.552  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_1 Registers
        553. 3.10.1.553  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_2 Registers
        554. 3.10.1.554  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_L Registers
        555. 3.10.1.555  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_H Registers
        556. 3.10.1.556  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_L Registers
        557. 3.10.1.557  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_H Registers
        558. 3.10.1.558  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_CONTROL Registers
        559. 3.10.1.559  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_0 Registers
        560. 3.10.1.560  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_1 Registers
        561. 3.10.1.561  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_2 Registers
        562. 3.10.1.562  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_L Registers
        563. 3.10.1.563  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_H Registers
        564. 3.10.1.564  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_L Registers
        565. 3.10.1.565  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_H Registers
        566. 3.10.1.566  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_CONTROL Registers
        567. 3.10.1.567  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_0 Registers
        568. 3.10.1.568  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_1 Registers
        569. 3.10.1.569  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_2 Registers
        570. 3.10.1.570  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_L Registers
        571. 3.10.1.571  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_H Registers
        572. 3.10.1.572  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_L Registers
        573. 3.10.1.573  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_H Registers
        574. 3.10.1.574  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_CONTROL Registers
        575. 3.10.1.575  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_0 Registers
        576. 3.10.1.576  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_1 Registers
        577. 3.10.1.577  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_2 Registers
        578. 3.10.1.578  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_L Registers
        579. 3.10.1.579  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_H Registers
        580. 3.10.1.580  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_L Registers
        581. 3.10.1.581  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_H Registers
        582. 3.10.1.582  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_CONTROL Registers
        583. 3.10.1.583  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_0 Registers
        584. 3.10.1.584  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_1 Registers
        585. 3.10.1.585  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_2 Registers
        586. 3.10.1.586  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_L Registers
        587. 3.10.1.587  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_H Registers
        588. 3.10.1.588  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_L Registers
        589. 3.10.1.589  FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_H Registers
        590. 3.10.1.590  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_CONTROL Registers
        591. 3.10.1.591  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_0 Registers
        592. 3.10.1.592  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_1 Registers
        593. 3.10.1.593  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_2 Registers
        594. 3.10.1.594  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_L Registers
        595. 3.10.1.595  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_H Registers
        596. 3.10.1.596  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_L Registers
        597. 3.10.1.597  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_H Registers
        598. 3.10.1.598  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_CONTROL Registers
        599. 3.10.1.599  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_0 Registers
        600. 3.10.1.600  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_1 Registers
        601. 3.10.1.601  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_2 Registers
        602. 3.10.1.602  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_L Registers
        603. 3.10.1.603  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_H Registers
        604. 3.10.1.604  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_L Registers
        605. 3.10.1.605  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_H Registers
        606. 3.10.1.606  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_CONTROL Registers
        607. 3.10.1.607  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_0 Registers
        608. 3.10.1.608  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_1 Registers
        609. 3.10.1.609  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_2 Registers
        610. 3.10.1.610  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_L Registers
        611. 3.10.1.611  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_H Registers
        612. 3.10.1.612  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_L Registers
        613. 3.10.1.613  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_H Registers
        614. 3.10.1.614  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_CONTROL Registers
        615. 3.10.1.615  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_0 Registers
        616. 3.10.1.616  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_1 Registers
        617. 3.10.1.617  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_2 Registers
        618. 3.10.1.618  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_L Registers
        619. 3.10.1.619  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_H Registers
        620. 3.10.1.620  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_L Registers
        621. 3.10.1.621  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_H Registers
        622. 3.10.1.622  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_CONTROL Registers
        623. 3.10.1.623  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_0 Registers
        624. 3.10.1.624  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_1 Registers
        625. 3.10.1.625  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_2 Registers
        626. 3.10.1.626  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_L Registers
        627. 3.10.1.627  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_H Registers
        628. 3.10.1.628  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_L Registers
        629. 3.10.1.629  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_H Registers
        630. 3.10.1.630  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_CONTROL Registers
        631. 3.10.1.631  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_0 Registers
        632. 3.10.1.632  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_1 Registers
        633. 3.10.1.633  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_2 Registers
        634. 3.10.1.634  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_L Registers
        635. 3.10.1.635  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_H Registers
        636. 3.10.1.636  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_L Registers
        637. 3.10.1.637  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_H Registers
        638. 3.10.1.638  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_CONTROL Registers
        639. 3.10.1.639  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_0 Registers
        640. 3.10.1.640  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_1 Registers
        641. 3.10.1.641  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_2 Registers
        642. 3.10.1.642  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_L Registers
        643. 3.10.1.643  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_H Registers
        644. 3.10.1.644  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_L Registers
        645. 3.10.1.645  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_H Registers
        646. 3.10.1.646  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_CONTROL Registers
        647. 3.10.1.647  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_0 Registers
        648. 3.10.1.648  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_1 Registers
        649. 3.10.1.649  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_2 Registers
        650. 3.10.1.650  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_L Registers
        651. 3.10.1.651  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_H Registers
        652. 3.10.1.652  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_L Registers
        653. 3.10.1.653  FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_H Registers
        654. 3.10.1.654  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_CONTROL Registers
        655. 3.10.1.655  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_0 Registers
        656. 3.10.1.656  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_1 Registers
        657. 3.10.1.657  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_2 Registers
        658. 3.10.1.658  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_L Registers
        659. 3.10.1.659  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_H Registers
        660. 3.10.1.660  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_L Registers
        661. 3.10.1.661  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_H Registers
        662. 3.10.1.662  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_CONTROL Registers
        663. 3.10.1.663  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_0 Registers
        664. 3.10.1.664  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_1 Registers
        665. 3.10.1.665  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_2 Registers
        666. 3.10.1.666  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_L Registers
        667. 3.10.1.667  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_H Registers
        668. 3.10.1.668  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_L Registers
        669. 3.10.1.669  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_H Registers
        670. 3.10.1.670  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_CONTROL Registers
        671. 3.10.1.671  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_0 Registers
        672. 3.10.1.672  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_1 Registers
        673. 3.10.1.673  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_2 Registers
        674. 3.10.1.674  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_L Registers
        675. 3.10.1.675  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_H Registers
        676. 3.10.1.676  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_L Registers
        677. 3.10.1.677  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_H Registers
        678. 3.10.1.678  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_CONTROL Registers
        679. 3.10.1.679  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_0 Registers
        680. 3.10.1.680  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_1 Registers
        681. 3.10.1.681  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_2 Registers
        682. 3.10.1.682  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_L Registers
        683. 3.10.1.683  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_H Registers
        684. 3.10.1.684  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_L Registers
        685. 3.10.1.685  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_H Registers
        686. 3.10.1.686  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_CONTROL Registers
        687. 3.10.1.687  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_0 Registers
        688. 3.10.1.688  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_1 Registers
        689. 3.10.1.689  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_2 Registers
        690. 3.10.1.690  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_L Registers
        691. 3.10.1.691  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_H Registers
        692. 3.10.1.692  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_L Registers
        693. 3.10.1.693  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_H Registers
        694. 3.10.1.694  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_CONTROL Registers
        695. 3.10.1.695  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_0 Registers
        696. 3.10.1.696  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_1 Registers
        697. 3.10.1.697  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_2 Registers
        698. 3.10.1.698  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_L Registers
        699. 3.10.1.699  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_H Registers
        700. 3.10.1.700  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_L Registers
        701. 3.10.1.701  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_H Registers
        702. 3.10.1.702  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_CONTROL Registers
        703. 3.10.1.703  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_0 Registers
        704. 3.10.1.704  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_1 Registers
        705. 3.10.1.705  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_2 Registers
        706. 3.10.1.706  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_L Registers
        707. 3.10.1.707  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_H Registers
        708. 3.10.1.708  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_L Registers
        709. 3.10.1.709  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_H Registers
        710. 3.10.1.710  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_CONTROL Registers
        711. 3.10.1.711  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_0 Registers
        712. 3.10.1.712  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_1 Registers
        713. 3.10.1.713  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_2 Registers
        714. 3.10.1.714  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_L Registers
        715. 3.10.1.715  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_H Registers
        716. 3.10.1.716  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_L Registers
        717. 3.10.1.717  FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_H Registers
        718. 3.10.1.718  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_CONTROL Registers
        719. 3.10.1.719  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_L Registers
        720. 3.10.1.720  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_H Registers
        721. 3.10.1.721  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_L Registers
        722. 3.10.1.722  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_H Registers
        723. 3.10.1.723  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_DEF_CONTROL Registers
        724. 3.10.1.724  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_CONTROL Registers
        725. 3.10.1.725  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_L Registers
        726. 3.10.1.726  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_H Registers
        727. 3.10.1.727  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_L Registers
        728. 3.10.1.728  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_H Registers
        729. 3.10.1.729  ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_DEF_CONTROL Registers
        730. 3.10.1.730  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_CONTROL Registers
        731. 3.10.1.731  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        732. 3.10.1.732  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        733. 3.10.1.733  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        734. 3.10.1.734  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        735. 3.10.1.735  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_DEF_CONTROL Registers
        736. 3.10.1.736  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_CONTROL Registers
        737. 3.10.1.737  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        738. 3.10.1.738  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        739. 3.10.1.739  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        740. 3.10.1.740  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        741. 3.10.1.741  ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_DEF_CONTROL Registers
        742. 3.10.1.742  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_CONTROL Registers
        743. 3.10.1.743  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        744. 3.10.1.744  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        745. 3.10.1.745  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        746. 3.10.1.746  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        747. 3.10.1.747  ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_DEF_CONTROL Registers
        748. 3.10.1.748  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_CONTROL Registers
        749. 3.10.1.749  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        750. 3.10.1.750  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        751. 3.10.1.751  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        752. 3.10.1.752  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        753. 3.10.1.753  ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_DEF_CONTROL Registers
        754. 3.10.1.754  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        755. 3.10.1.755  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        756. 3.10.1.756  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        757. 3.10.1.757  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        758. 3.10.1.758  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        759. 3.10.1.759  ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        760. 3.10.1.760  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        761. 3.10.1.761  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        762. 3.10.1.762  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        763. 3.10.1.763  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        764. 3.10.1.764  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        765. 3.10.1.765  ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        766. 3.10.1.766  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        767. 3.10.1.767  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        768. 3.10.1.768  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        769. 3.10.1.769  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        770. 3.10.1.770  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        771. 3.10.1.771  ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        772. 3.10.1.772  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        773. 3.10.1.773  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        774. 3.10.1.774  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        775. 3.10.1.775  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        776. 3.10.1.776  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        777. 3.10.1.777  ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        778. 3.10.1.778  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_CONTROL Registers
        779. 3.10.1.779  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        780. 3.10.1.780  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        781. 3.10.1.781  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        782. 3.10.1.782  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        783. 3.10.1.783  ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_DEF_CONTROL Registers
        784. 3.10.1.784  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_CONTROL Registers
        785. 3.10.1.785  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        786. 3.10.1.786  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        787. 3.10.1.787  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        788. 3.10.1.788  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        789. 3.10.1.789  ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_DEF_CONTROL Registers
        790. 3.10.1.790  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_CONTROL Registers
        791. 3.10.1.791  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Registers
        792. 3.10.1.792  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Registers
        793. 3.10.1.793  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Registers
        794. 3.10.1.794  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Registers
        795. 3.10.1.795  ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_DEF_CONTROL Registers
        796. 3.10.1.796  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_CONTROL Registers
        797. 3.10.1.797  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Registers
        798. 3.10.1.798  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Registers
        799. 3.10.1.799  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Registers
        800. 3.10.1.800  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Registers
        801. 3.10.1.801  ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_DEF_CONTROL Registers
        802. 3.10.1.802  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        803. 3.10.1.803  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        804. 3.10.1.804  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        805. 3.10.1.805  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        806. 3.10.1.806  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        807. 3.10.1.807  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        808. 3.10.1.808  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        809. 3.10.1.809  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        810. 3.10.1.810  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        811. 3.10.1.811  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        812. 3.10.1.812  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        813. 3.10.1.813  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        814. 3.10.1.814  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        815. 3.10.1.815  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        816. 3.10.1.816  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        817. 3.10.1.817  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        818. 3.10.1.818  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        819. 3.10.1.819  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        820. 3.10.1.820  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        821. 3.10.1.821  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        822. 3.10.1.822  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        823. 3.10.1.823  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        824. 3.10.1.824  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        825. 3.10.1.825  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        826. 3.10.1.826  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        827. 3.10.1.827  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        828. 3.10.1.828  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        829. 3.10.1.829  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        830. 3.10.1.830  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        831. 3.10.1.831  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        832. 3.10.1.832  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        833. 3.10.1.833  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        834. 3.10.1.834  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        835. 3.10.1.835  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        836. 3.10.1.836  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        837. 3.10.1.837  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        838. 3.10.1.838  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        839. 3.10.1.839  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        840. 3.10.1.840  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        841. 3.10.1.841  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        842. 3.10.1.842  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        843. 3.10.1.843  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        844. 3.10.1.844  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        845. 3.10.1.845  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        846. 3.10.1.846  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        847. 3.10.1.847  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        848. 3.10.1.848  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        849. 3.10.1.849  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        850. 3.10.1.850  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        851. 3.10.1.851  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        852. 3.10.1.852  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        853. 3.10.1.853  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        854. 3.10.1.854  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        855. 3.10.1.855  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        856. 3.10.1.856  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        857. 3.10.1.857  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        858. 3.10.1.858  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        859. 3.10.1.859  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        860. 3.10.1.860  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        861. 3.10.1.861  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        862. 3.10.1.862  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        863. 3.10.1.863  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        864. 3.10.1.864  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        865. 3.10.1.865  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        866. 3.10.1.866  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        867. 3.10.1.867  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        868. 3.10.1.868  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        869. 3.10.1.869  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        870. 3.10.1.870  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        871. 3.10.1.871  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        872. 3.10.1.872  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        873. 3.10.1.873  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        874. 3.10.1.874  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        875. 3.10.1.875  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        876. 3.10.1.876  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        877. 3.10.1.877  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        878. 3.10.1.878  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        879. 3.10.1.879  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        880. 3.10.1.880  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        881. 3.10.1.881  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        882. 3.10.1.882  ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        883. 3.10.1.883  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Registers
        884. 3.10.1.884  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Registers
        885. 3.10.1.885  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Registers
        886. 3.10.1.886  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Registers
        887. 3.10.1.887  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Registers
        888. 3.10.1.888  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Registers
        889. 3.10.1.889  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Registers
        890. 3.10.1.890  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Registers
        891. 3.10.1.891  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Registers
        892. 3.10.1.892  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Registers
        893. 3.10.1.893  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Registers
        894. 3.10.1.894  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Registers
        895. 3.10.1.895  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Registers
        896. 3.10.1.896  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Registers
        897. 3.10.1.897  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Registers
        898. 3.10.1.898  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Registers
        899. 3.10.1.899  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Registers
        900. 3.10.1.900  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Registers
        901. 3.10.1.901  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Registers
        902. 3.10.1.902  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Registers
        903. 3.10.1.903  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Registers
        904. 3.10.1.904  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Registers
        905. 3.10.1.905  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Registers
        906. 3.10.1.906  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Registers
        907. 3.10.1.907  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Registers
        908. 3.10.1.908  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Registers
        909. 3.10.1.909  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Registers
        910. 3.10.1.910  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Registers
        911. 3.10.1.911  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Registers
        912. 3.10.1.912  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Registers
        913. 3.10.1.913  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Registers
        914. 3.10.1.914  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Registers
        915. 3.10.1.915  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Registers
        916. 3.10.1.916  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Registers
        917. 3.10.1.917  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Registers
        918. 3.10.1.918  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Registers
        919. 3.10.1.919  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Registers
        920. 3.10.1.920  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Registers
        921. 3.10.1.921  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Registers
        922. 3.10.1.922  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Registers
        923. 3.10.1.923  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Registers
        924. 3.10.1.924  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Registers
        925. 3.10.1.925  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Registers
        926. 3.10.1.926  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Registers
        927. 3.10.1.927  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Registers
        928. 3.10.1.928  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Registers
        929. 3.10.1.929  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Registers
        930. 3.10.1.930  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Registers
        931. 3.10.1.931  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Registers
        932. 3.10.1.932  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Registers
        933. 3.10.1.933  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Registers
        934. 3.10.1.934  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Registers
        935. 3.10.1.935  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Registers
        936. 3.10.1.936  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Registers
        937. 3.10.1.937  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Registers
        938. 3.10.1.938  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Registers
        939. 3.10.1.939  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Registers
        940. 3.10.1.940  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Registers
        941. 3.10.1.941  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Registers
        942. 3.10.1.942  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Registers
        943. 3.10.1.943  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Registers
        944. 3.10.1.944  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Registers
        945. 3.10.1.945  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Registers
        946. 3.10.1.946  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Registers
        947. 3.10.1.947  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Registers
        948. 3.10.1.948  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Registers
        949. 3.10.1.949  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Registers
        950. 3.10.1.950  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Registers
        951. 3.10.1.951  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Registers
        952. 3.10.1.952  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Registers
        953. 3.10.1.953  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Registers
        954. 3.10.1.954  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Registers
        955. 3.10.1.955  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Registers
        956. 3.10.1.956  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Registers
        957. 3.10.1.957  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Registers
        958. 3.10.1.958  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Registers
        959. 3.10.1.959  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Registers
        960. 3.10.1.960  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Registers
        961. 3.10.1.961  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Registers
        962. 3.10.1.962  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Registers
        963. 3.10.1.963  ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Registers
        964. 3.10.1.964  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_CONTROL Registers
        965. 3.10.1.965  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_L Registers
        966. 3.10.1.966  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_H Registers
        967. 3.10.1.967  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_L Registers
        968. 3.10.1.968  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_H Registers
        969. 3.10.1.969  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_CONTROL Registers
        970. 3.10.1.970  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_L Registers
        971. 3.10.1.971  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_H Registers
        972. 3.10.1.972  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_L Registers
        973. 3.10.1.973  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_H Registers
        974. 3.10.1.974  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_CONTROL Registers
        975. 3.10.1.975  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_L Registers
        976. 3.10.1.976  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_H Registers
        977. 3.10.1.977  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_L Registers
        978. 3.10.1.978  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_H Registers
        979. 3.10.1.979  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_CONTROL Registers
        980. 3.10.1.980  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_L Registers
        981. 3.10.1.981  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_H Registers
        982. 3.10.1.982  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_L Registers
        983. 3.10.1.983  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_H Registers
        984. 3.10.1.984  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_CONTROL Registers
        985. 3.10.1.985  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_L Registers
        986. 3.10.1.986  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_H Registers
        987. 3.10.1.987  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_L Registers
        988. 3.10.1.988  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_H Registers
        989. 3.10.1.989  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_CONTROL Registers
        990. 3.10.1.990  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_L Registers
        991. 3.10.1.991  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_H Registers
        992. 3.10.1.992  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_L Registers
        993. 3.10.1.993  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_H Registers
        994. 3.10.1.994  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_CONTROL Registers
        995. 3.10.1.995  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_L Registers
        996. 3.10.1.996  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_H Registers
        997. 3.10.1.997  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_L Registers
        998. 3.10.1.998  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_H Registers
        999. 3.10.1.999  ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_CONTROL Registers
        1000. 3.10.1.1000 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_L Registers
        1001. 3.10.1.1001 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_H Registers
        1002. 3.10.1.1002 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_L Registers
        1003. 3.10.1.1003 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_H Registers
        1004. 3.10.1.1004 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_DEF_CONTROL Registers
        1005. 3.10.1.1005 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_CONTROL Registers
        1006. 3.10.1.1006 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1007. 3.10.1.1007 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1008. 3.10.1.1008 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1009. 3.10.1.1009 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1010. 3.10.1.1010 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_CONTROL Registers
        1011. 3.10.1.1011 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_L Registers
        1012. 3.10.1.1012 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_H Registers
        1013. 3.10.1.1013 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_L Registers
        1014. 3.10.1.1014 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_H Registers
        1015. 3.10.1.1015 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_CONTROL Registers
        1016. 3.10.1.1016 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_L Registers
        1017. 3.10.1.1017 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_H Registers
        1018. 3.10.1.1018 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_L Registers
        1019. 3.10.1.1019 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_H Registers
        1020. 3.10.1.1020 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_CONTROL Registers
        1021. 3.10.1.1021 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_L Registers
        1022. 3.10.1.1022 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_H Registers
        1023. 3.10.1.1023 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_L Registers
        1024. 3.10.1.1024 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_H Registers
        1025. 3.10.1.1025 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_CONTROL Registers
        1026. 3.10.1.1026 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_L Registers
        1027. 3.10.1.1027 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_H Registers
        1028. 3.10.1.1028 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_L Registers
        1029. 3.10.1.1029 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_H Registers
        1030. 3.10.1.1030 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_CONTROL Registers
        1031. 3.10.1.1031 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_L Registers
        1032. 3.10.1.1032 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_H Registers
        1033. 3.10.1.1033 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_L Registers
        1034. 3.10.1.1034 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_H Registers
        1035. 3.10.1.1035 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_CONTROL Registers
        1036. 3.10.1.1036 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_L Registers
        1037. 3.10.1.1037 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_H Registers
        1038. 3.10.1.1038 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_L Registers
        1039. 3.10.1.1039 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_H Registers
        1040. 3.10.1.1040 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_CONTROL Registers
        1041. 3.10.1.1041 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_L Registers
        1042. 3.10.1.1042 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_H Registers
        1043. 3.10.1.1043 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_L Registers
        1044. 3.10.1.1044 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_H Registers
        1045. 3.10.1.1045 ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_DEF_CONTROL Registers
        1046. 3.10.1.1046 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_CONTROL Registers
        1047. 3.10.1.1047 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_L Registers
        1048. 3.10.1.1048 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_H Registers
        1049. 3.10.1.1049 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_L Registers
        1050. 3.10.1.1050 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_H Registers
        1051. 3.10.1.1051 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_DEF_CONTROL Registers
        1052. 3.10.1.1052 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_CONTROL Registers
        1053. 3.10.1.1053 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_L Registers
        1054. 3.10.1.1054 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_H Registers
        1055. 3.10.1.1055 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_L Registers
        1056. 3.10.1.1056 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_H Registers
        1057. 3.10.1.1057 ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_DEF_CONTROL Registers
        1058. 3.10.1.1058 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_CONTROL Registers
        1059. 3.10.1.1059 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_L Registers
        1060. 3.10.1.1060 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_H Registers
        1061. 3.10.1.1061 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_L Registers
        1062. 3.10.1.1062 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_H Registers
        1063. 3.10.1.1063 ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_DEF_CONTROL Registers
        1064. 3.10.1.1064 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_CONTROL Registers
        1065. 3.10.1.1065 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_L Registers
        1066. 3.10.1.1066 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_H Registers
        1067. 3.10.1.1067 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_L Registers
        1068. 3.10.1.1068 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_H Registers
        1069. 3.10.1.1069 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_CONTROL Registers
        1070. 3.10.1.1070 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_L Registers
        1071. 3.10.1.1071 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_H Registers
        1072. 3.10.1.1072 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_L Registers
        1073. 3.10.1.1073 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_H Registers
        1074. 3.10.1.1074 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_CONTROL Registers
        1075. 3.10.1.1075 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_L Registers
        1076. 3.10.1.1076 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_H Registers
        1077. 3.10.1.1077 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_L Registers
        1078. 3.10.1.1078 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_H Registers
        1079. 3.10.1.1079 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_CONTROL Registers
        1080. 3.10.1.1080 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_L Registers
        1081. 3.10.1.1081 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_H Registers
        1082. 3.10.1.1082 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_L Registers
        1083. 3.10.1.1083 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_H Registers
        1084. 3.10.1.1084 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_CONTROL Registers
        1085. 3.10.1.1085 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_L Registers
        1086. 3.10.1.1086 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_H Registers
        1087. 3.10.1.1087 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_L Registers
        1088. 3.10.1.1088 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_H Registers
        1089. 3.10.1.1089 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_CONTROL Registers
        1090. 3.10.1.1090 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_L Registers
        1091. 3.10.1.1091 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_H Registers
        1092. 3.10.1.1092 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_L Registers
        1093. 3.10.1.1093 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_H Registers
        1094. 3.10.1.1094 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_CONTROL Registers
        1095. 3.10.1.1095 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_L Registers
        1096. 3.10.1.1096 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_H Registers
        1097. 3.10.1.1097 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_L Registers
        1098. 3.10.1.1098 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_H Registers
        1099. 3.10.1.1099 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_CONTROL Registers
        1100. 3.10.1.1100 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_L Registers
        1101. 3.10.1.1101 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_H Registers
        1102. 3.10.1.1102 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_L Registers
        1103. 3.10.1.1103 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_H Registers
        1104. 3.10.1.1104 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_DEF_CONTROL Registers
        1105. 3.10.1.1105 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_CONTROL Registers
        1106. 3.10.1.1106 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_L Registers
        1107. 3.10.1.1107 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_H Registers
        1108. 3.10.1.1108 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_L Registers
        1109. 3.10.1.1109 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_H Registers
        1110. 3.10.1.1110 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_CONTROL Registers
        1111. 3.10.1.1111 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_L Registers
        1112. 3.10.1.1112 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_H Registers
        1113. 3.10.1.1113 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_L Registers
        1114. 3.10.1.1114 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_H Registers
        1115. 3.10.1.1115 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_CONTROL Registers
        1116. 3.10.1.1116 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_L Registers
        1117. 3.10.1.1117 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_H Registers
        1118. 3.10.1.1118 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_L Registers
        1119. 3.10.1.1119 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_H Registers
        1120. 3.10.1.1120 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_CONTROL Registers
        1121. 3.10.1.1121 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_L Registers
        1122. 3.10.1.1122 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_H Registers
        1123. 3.10.1.1123 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_L Registers
        1124. 3.10.1.1124 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_H Registers
        1125. 3.10.1.1125 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_CONTROL Registers
        1126. 3.10.1.1126 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_L Registers
        1127. 3.10.1.1127 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_H Registers
        1128. 3.10.1.1128 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_L Registers
        1129. 3.10.1.1129 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_H Registers
        1130. 3.10.1.1130 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_CONTROL Registers
        1131. 3.10.1.1131 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_L Registers
        1132. 3.10.1.1132 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_H Registers
        1133. 3.10.1.1133 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_L Registers
        1134. 3.10.1.1134 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_H Registers
        1135. 3.10.1.1135 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_CONTROL Registers
        1136. 3.10.1.1136 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_L Registers
        1137. 3.10.1.1137 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_H Registers
        1138. 3.10.1.1138 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_L Registers
        1139. 3.10.1.1139 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_H Registers
        1140. 3.10.1.1140 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_CONTROL Registers
        1141. 3.10.1.1141 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_L Registers
        1142. 3.10.1.1142 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_H Registers
        1143. 3.10.1.1143 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_L Registers
        1144. 3.10.1.1144 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_H Registers
        1145. 3.10.1.1145 ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_DEF_CONTROL Registers
        1146. 3.10.1.1146 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_CONTROL Registers
        1147. 3.10.1.1147 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_L Registers
        1148. 3.10.1.1148 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_H Registers
        1149. 3.10.1.1149 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_L Registers
        1150. 3.10.1.1150 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_H Registers
        1151. 3.10.1.1151 ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_DEF_CONTROL Registers
        1152. 3.10.1.1152 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_CONTROL Registers
        1153. 3.10.1.1153 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_L Registers
        1154. 3.10.1.1154 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_H Registers
        1155. 3.10.1.1155 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_L Registers
        1156. 3.10.1.1156 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_H Registers
        1157. 3.10.1.1157 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_DEF_CONTROL Registers
        1158. 3.10.1.1158 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_CONTROL Registers
        1159. 3.10.1.1159 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_L Registers
        1160. 3.10.1.1160 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_H Registers
        1161. 3.10.1.1161 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_L Registers
        1162. 3.10.1.1162 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_H Registers
        1163. 3.10.1.1163 ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_DEF_CONTROL Registers
        1164. 3.10.1.1164 GLB_PID Registers
        1165. 3.10.1.1165 GLB_DESTINATION_ID Registers
        1166. 3.10.1.1166 GLB_EXCEPTION_LOGGING_CONTROL Registers
        1167. 3.10.1.1167 GLB_EXCEPTION_LOGGING_HEADER0 Registers
        1168. 3.10.1.1168 GLB_EXCEPTION_LOGGING_HEADER1 Registers
        1169. 3.10.1.1169 GLB_EXCEPTION_LOGGING_DATA0 Registers
        1170. 3.10.1.1170 GLB_EXCEPTION_LOGGING_DATA1 Registers
        1171. 3.10.1.1171 GLB_EXCEPTION_LOGGING_DATA2 Registers
        1172. 3.10.1.1172 GLB_EXCEPTION_LOGGING_DATA3 Registers
        1173. 3.10.1.1173 GLB_EXCEPTION_PEND_SET Registers
        1174. 3.10.1.1174 GLB_EXCEPTION_PEND_CLEAR Registers
        1175. 3.10.1.1175 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_MAP0 Registers
        1176. 3.10.1.1176 QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_MAP0 Registers
        1177. 3.10.1.1177 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MAP0 Registers
        1178. 3.10.1.1178 QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MAP0 Registers
        1179. 3.10.1.1179 QOS_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_MAP0 Registers
        1180. 3.10.1.1180 QOS_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_MAP0 Registers
        1181. 3.10.1.1181 QOS_IPULSAR_LITE_MAIN_0_CPU0_RMST_MAP0 Registers
        1182. 3.10.1.1182 QOS_IPULSAR_LITE_MAIN_0_CPU0_WMST_MAP0 Registers
        1183. 3.10.1.1183 QOS_IPULSAR_LITE_MAIN_0_CPU1_RMST_MAP0 Registers
        1184. 3.10.1.1184 QOS_IPULSAR_LITE_MAIN_0_CPU1_WMST_MAP0 Registers
        1185. 3.10.1.1185 QOS_IPULSAR_LITE_MAIN_1_CPU0_RMST_MAP0 Registers
        1186. 3.10.1.1186 QOS_IPULSAR_LITE_MAIN_1_CPU0_WMST_MAP0 Registers
        1187. 3.10.1.1187 QOS_IPULSAR_LITE_MAIN_1_CPU1_RMST_MAP0 Registers
        1188. 3.10.1.1188 QOS_IPULSAR_LITE_MAIN_1_CPU1_WMST_MAP0 Registers
        1189. 3.10.1.1189 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP0 Registers
        1190. 3.10.1.1190 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP1 Registers
        1191. 3.10.1.1191 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP2 Registers
        1192. 3.10.1.1192 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP3 Registers
        1193. 3.10.1.1193 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP4 Registers
        1194. 3.10.1.1194 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP5 Registers
        1195. 3.10.1.1195 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP6 Registers
        1196. 3.10.1.1196 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP7 Registers
        1197. 3.10.1.1197 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP8 Registers
        1198. 3.10.1.1198 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP9 Registers
        1199. 3.10.1.1199 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP10 Registers
        1200. 3.10.1.1200 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP11 Registers
        1201. 3.10.1.1201 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP12 Registers
        1202. 3.10.1.1202 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP13 Registers
        1203. 3.10.1.1203 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP14 Registers
        1204. 3.10.1.1204 QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP15 Registers
        1205. 3.10.1.1205 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP0 Registers
        1206. 3.10.1.1206 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP1 Registers
        1207. 3.10.1.1207 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP2 Registers
        1208. 3.10.1.1208 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP3 Registers
        1209. 3.10.1.1209 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP4 Registers
        1210. 3.10.1.1210 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP5 Registers
        1211. 3.10.1.1211 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP6 Registers
        1212. 3.10.1.1212 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP7 Registers
        1213. 3.10.1.1213 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP8 Registers
        1214. 3.10.1.1214 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP9 Registers
        1215. 3.10.1.1215 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP10 Registers
        1216. 3.10.1.1216 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP11 Registers
        1217. 3.10.1.1217 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP12 Registers
        1218. 3.10.1.1218 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP13 Registers
        1219. 3.10.1.1219 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP14 Registers
        1220. 3.10.1.1220 QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP15 Registers
        1221. 3.10.1.1221 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP0 Registers
        1222. 3.10.1.1222 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP1 Registers
        1223. 3.10.1.1223 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP2 Registers
        1224. 3.10.1.1224 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP3 Registers
        1225. 3.10.1.1225 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP4 Registers
        1226. 3.10.1.1226 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP5 Registers
        1227. 3.10.1.1227 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP6 Registers
        1228. 3.10.1.1228 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP7 Registers
        1229. 3.10.1.1229 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP0 Registers
        1230. 3.10.1.1230 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP1 Registers
        1231. 3.10.1.1231 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP2 Registers
        1232. 3.10.1.1232 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP3 Registers
        1233. 3.10.1.1233 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP4 Registers
        1234. 3.10.1.1234 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP5 Registers
        1235. 3.10.1.1235 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP6 Registers
        1236. 3.10.1.1236 QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP7 Registers
        1237. 3.10.1.1237 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MAP0 Registers
        1238. 3.10.1.1238 QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MAP0 Registers
        1239. 3.10.1.1239 QOS_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_MAP0 Registers
        1240. 3.10.1.1240 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP0 Registers
        1241. 3.10.1.1241 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP1 Registers
        1242. 3.10.1.1242 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP2 Registers
        1243. 3.10.1.1243 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP3 Registers
        1244. 3.10.1.1244 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP4 Registers
        1245. 3.10.1.1245 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP5 Registers
        1246. 3.10.1.1246 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP6 Registers
        1247. 3.10.1.1247 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP7 Registers
        1248. 3.10.1.1248 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP0 Registers
        1249. 3.10.1.1249 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP1 Registers
        1250. 3.10.1.1250 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP2 Registers
        1251. 3.10.1.1251 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP3 Registers
        1252. 3.10.1.1252 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP4 Registers
        1253. 3.10.1.1253 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP5 Registers
        1254. 3.10.1.1254 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP6 Registers
        1255. 3.10.1.1255 QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP7 Registers
        1256. 3.10.1.1256 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_MAP0 Registers
        1257. 3.10.1.1257 QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_MAP0 Registers
        1258. 3.10.1.1258 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_CONTROL Registers
        1259. 3.10.1.1259 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_L Registers
        1260. 3.10.1.1260 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_H Registers
        1261. 3.10.1.1261 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_L Registers
        1262. 3.10.1.1262 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_H Registers
        1263. 3.10.1.1263 ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_DEF_CONTROL Registers
        1264. 3.10.1.1264 QOS_IBLAZAR_MCU_0_VBUSP_M_MAP0 Registers
        1265. 3.10.1.1265 Access Table
      2. 3.10.2 CBASS_FW Registers
        1. 3.10.2.1  ERR_REGS_CBASS_FW_PID Registers
        2. 3.10.2.2  ERR_REGS_CBASS_FW_DESTINATION_ID Registers
        3. 3.10.2.3  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.2.4  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.2.5  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.2.6  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.2.7  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.2.8  ERR_REGS_CBASS_FW_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.2.9  ERR_REGS_CBASS_FW_ERR_INTR_RAW_STAT Registers
        10. 3.10.2.10 ERR_REGS_CBASS_FW_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.2.11 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_SET Registers
        12. 3.10.2.12 ERR_REGS_CBASS_FW_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.2.13 ERR_REGS_CBASS_FW_EOI Registers
        14. 3.10.2.14 Access Table
      3. 3.10.3 CBASS_INFRA Registers
        1. 3.10.3.1   ERR_REGS_CBASS_INFRA_PID Registers
        2. 3.10.3.2   ERR_REGS_CBASS_INFRA_DESTINATION_ID Registers
        3. 3.10.3.3   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.3.4   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.3.5   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.3.6   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.3.7   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.3.8   ERR_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.3.9   ERR_REGS_CBASS_INFRA_ERR_INTR_RAW_STAT Registers
        10. 3.10.3.10  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.3.11  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_SET Registers
        12. 3.10.3.12  ERR_REGS_CBASS_INFRA_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.3.13  ERR_REGS_CBASS_INFRA_EOI Registers
        14. 3.10.3.14  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_CONTROL Registers
        15. 3.10.3.15  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_0 Registers
        16. 3.10.3.16  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_1 Registers
        17. 3.10.3.17  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_2 Registers
        18. 3.10.3.18  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_L Registers
        19. 3.10.3.19  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_H Registers
        20. 3.10.3.20  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_L Registers
        21. 3.10.3.21  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_H Registers
        22. 3.10.3.22  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_CONTROL Registers
        23. 3.10.3.23  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_0 Registers
        24. 3.10.3.24  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_1 Registers
        25. 3.10.3.25  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_2 Registers
        26. 3.10.3.26  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_L Registers
        27. 3.10.3.27  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_H Registers
        28. 3.10.3.28  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_L Registers
        29. 3.10.3.29  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_H Registers
        30. 3.10.3.30  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_CONTROL Registers
        31. 3.10.3.31  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_0 Registers
        32. 3.10.3.32  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_1 Registers
        33. 3.10.3.33  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_2 Registers
        34. 3.10.3.34  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_L Registers
        35. 3.10.3.35  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_H Registers
        36. 3.10.3.36  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_L Registers
        37. 3.10.3.37  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_H Registers
        38. 3.10.3.38  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_CONTROL Registers
        39. 3.10.3.39  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_0 Registers
        40. 3.10.3.40  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_1 Registers
        41. 3.10.3.41  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_2 Registers
        42. 3.10.3.42  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_L Registers
        43. 3.10.3.43  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_H Registers
        44. 3.10.3.44  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_L Registers
        45. 3.10.3.45  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_H Registers
        46. 3.10.3.46  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_CONTROL Registers
        47. 3.10.3.47  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_0 Registers
        48. 3.10.3.48  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_1 Registers
        49. 3.10.3.49  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_2 Registers
        50. 3.10.3.50  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_L Registers
        51. 3.10.3.51  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_H Registers
        52. 3.10.3.52  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_L Registers
        53. 3.10.3.53  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_H Registers
        54. 3.10.3.54  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_CONTROL Registers
        55. 3.10.3.55  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_0 Registers
        56. 3.10.3.56  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_1 Registers
        57. 3.10.3.57  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_2 Registers
        58. 3.10.3.58  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_L Registers
        59. 3.10.3.59  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_H Registers
        60. 3.10.3.60  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_L Registers
        61. 3.10.3.61  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_H Registers
        62. 3.10.3.62  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_CONTROL Registers
        63. 3.10.3.63  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_0 Registers
        64. 3.10.3.64  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_1 Registers
        65. 3.10.3.65  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_2 Registers
        66. 3.10.3.66  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_L Registers
        67. 3.10.3.67  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_H Registers
        68. 3.10.3.68  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_L Registers
        69. 3.10.3.69  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_H Registers
        70. 3.10.3.70  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_CONTROL Registers
        71. 3.10.3.71  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_0 Registers
        72. 3.10.3.72  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_1 Registers
        73. 3.10.3.73  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_2 Registers
        74. 3.10.3.74  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_L Registers
        75. 3.10.3.75  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_H Registers
        76. 3.10.3.76  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_L Registers
        77. 3.10.3.77  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_H Registers
        78. 3.10.3.78  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_CONTROL Registers
        79. 3.10.3.79  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_0 Registers
        80. 3.10.3.80  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_1 Registers
        81. 3.10.3.81  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_2 Registers
        82. 3.10.3.82  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_L Registers
        83. 3.10.3.83  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_H Registers
        84. 3.10.3.84  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_L Registers
        85. 3.10.3.85  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_H Registers
        86. 3.10.3.86  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_CONTROL Registers
        87. 3.10.3.87  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_0 Registers
        88. 3.10.3.88  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_1 Registers
        89. 3.10.3.89  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_2 Registers
        90. 3.10.3.90  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_L Registers
        91. 3.10.3.91  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_H Registers
        92. 3.10.3.92  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_L Registers
        93. 3.10.3.93  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_H Registers
        94. 3.10.3.94  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_CONTROL Registers
        95. 3.10.3.95  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_0 Registers
        96. 3.10.3.96  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_1 Registers
        97. 3.10.3.97  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_2 Registers
        98. 3.10.3.98  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_L Registers
        99. 3.10.3.99  FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_H Registers
        100. 3.10.3.100 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_L Registers
        101. 3.10.3.101 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_H Registers
        102. 3.10.3.102 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_CONTROL Registers
        103. 3.10.3.103 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_0 Registers
        104. 3.10.3.104 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_1 Registers
        105. 3.10.3.105 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_2 Registers
        106. 3.10.3.106 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_L Registers
        107. 3.10.3.107 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_H Registers
        108. 3.10.3.108 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_L Registers
        109. 3.10.3.109 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_H Registers
        110. 3.10.3.110 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_CONTROL Registers
        111. 3.10.3.111 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_0 Registers
        112. 3.10.3.112 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_1 Registers
        113. 3.10.3.113 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_2 Registers
        114. 3.10.3.114 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_L Registers
        115. 3.10.3.115 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_H Registers
        116. 3.10.3.116 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_L Registers
        117. 3.10.3.117 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_H Registers
        118. 3.10.3.118 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_CONTROL Registers
        119. 3.10.3.119 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_0 Registers
        120. 3.10.3.120 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_1 Registers
        121. 3.10.3.121 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_2 Registers
        122. 3.10.3.122 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_L Registers
        123. 3.10.3.123 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_H Registers
        124. 3.10.3.124 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_L Registers
        125. 3.10.3.125 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_H Registers
        126. 3.10.3.126 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_CONTROL Registers
        127. 3.10.3.127 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_0 Registers
        128. 3.10.3.128 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_1 Registers
        129. 3.10.3.129 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_2 Registers
        130. 3.10.3.130 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_L Registers
        131. 3.10.3.131 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_H Registers
        132. 3.10.3.132 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_L Registers
        133. 3.10.3.133 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_H Registers
        134. 3.10.3.134 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_CONTROL Registers
        135. 3.10.3.135 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_0 Registers
        136. 3.10.3.136 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_1 Registers
        137. 3.10.3.137 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_2 Registers
        138. 3.10.3.138 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_L Registers
        139. 3.10.3.139 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_H Registers
        140. 3.10.3.140 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_L Registers
        141. 3.10.3.141 FW_REGS_CBASS_INFRA_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_H Registers
        142. 3.10.3.142 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        143. 3.10.3.143 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        144. 3.10.3.144 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        145. 3.10.3.145 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        146. 3.10.3.146 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        147. 3.10.3.147 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        148. 3.10.3.148 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        149. 3.10.3.149 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        150. 3.10.3.150 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        151. 3.10.3.151 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        152. 3.10.3.152 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        153. 3.10.3.153 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        154. 3.10.3.154 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_CONTROL Registers
        155. 3.10.3.155 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        156. 3.10.3.156 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        157. 3.10.3.157 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        158. 3.10.3.158 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        159. 3.10.3.159 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_DEF_CONTROL Registers
        160. 3.10.3.160 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_CONTROL Registers
        161. 3.10.3.161 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Registers
        162. 3.10.3.162 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Registers
        163. 3.10.3.163 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Registers
        164. 3.10.3.164 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Registers
        165. 3.10.3.165 ISC_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_DEF_CONTROL Registers
        166. 3.10.3.166 GLB_REGS_CBASS_INFRA_PID Registers
        167. 3.10.3.167 GLB_REGS_CBASS_INFRA_DESTINATION_ID Registers
        168. 3.10.3.168 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_CONTROL Registers
        169. 3.10.3.169 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER0 Registers
        170. 3.10.3.170 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_HEADER1 Registers
        171. 3.10.3.171 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA0 Registers
        172. 3.10.3.172 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA1 Registers
        173. 3.10.3.173 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA2 Registers
        174. 3.10.3.174 GLB_REGS_CBASS_INFRA_EXCEPTION_LOGGING_DATA3 Registers
        175. 3.10.3.175 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_SET Registers
        176. 3.10.3.176 GLB_REGS_CBASS_INFRA_EXCEPTION_PEND_CLEAR Registers
        177. 3.10.3.177 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU0_PMST_MAP0 Registers
        178. 3.10.3.178 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_0_CPU1_PMST_MAP0 Registers
        179. 3.10.3.179 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU0_PMST_MAP0 Registers
        180. 3.10.3.180 QOS_REGS_CBASS_INFRA_IPULSAR_LITE_MAIN_1_CPU1_PMST_MAP0 Registers
        181. 3.10.3.181 Access Table
      4. 3.10.4 CBASS_DBG Registers
        1. 3.10.4.1  ERR_REGS_CBASS_DBG_PID Registers
        2. 3.10.4.2  ERR_REGS_CBASS_DBG_DESTINATION_ID Registers
        3. 3.10.4.3  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER0 Registers
        4. 3.10.4.4  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_HEADER1 Registers
        5. 3.10.4.5  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA0 Registers
        6. 3.10.4.6  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA1 Registers
        7. 3.10.4.7  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA2 Registers
        8. 3.10.4.8  ERR_REGS_CBASS_DBG_EXCEPTION_LOGGING_DATA3 Registers
        9. 3.10.4.9  ERR_REGS_CBASS_DBG_ERR_INTR_RAW_STAT Registers
        10. 3.10.4.10 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLED_STAT Registers
        11. 3.10.4.11 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_SET Registers
        12. 3.10.4.12 ERR_REGS_CBASS_DBG_ERR_INTR_ENABLE_CLR Registers
        13. 3.10.4.13 ERR_REGS_CBASS_DBG_EOI Registers
        14. 3.10.4.14 Access Table
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Boot Terminology
    2. 4.2 Boot Process
      1. 4.2.1 Public ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
    3. 4.3 Boot Mode Pins
      1. 4.3.1 BOOTMODE Pin Mapping
        1. 4.3.1.1 Primary Boot Mode Selection and Configuration
        2. 4.3.1.2 Backup Boot Mode Selection and Configuration
    4. 4.4 Boot Modes
      1. 4.4.1  OSPI, xSPI, QSPI, SPI Boot
        1. 4.4.1.1 OSPI Boot
          1. 4.4.1.1.1 OSPI Bootloader Operation
            1. 4.4.1.1.1.1 OSPI Initialization Process
            2. 4.4.1.1.1.2 OSPI Loading Process
        2. 4.4.1.2 xSPI Boot
          1. 4.4.1.2.1 xSPI Bootloader Operation
        3. 4.4.1.3 QSPI Boot
          1. 4.4.1.3.1 QSPI Bootloader Operation
            1. 4.4.1.3.1.1 QSPI Initialization Process
            2. 4.4.1.3.1.2 QSPI Loading Process
        4. 4.4.1.4 SPI Boot
          1. 4.4.1.4.1 SPI Bootloader Operation
            1. 4.4.1.4.1.1 SPI Initialization Process
            2. 4.4.1.4.1.2 SPI Loading Process
      2. 4.4.2  I2C Boot
        1. 4.4.2.1 I2C Bootloader Operation
          1. 4.4.2.1.1 I2C Initialization Process
            1. 4.4.2.1.1.1 Block Size
            2. 4.4.2.1.1.2 Addressing
          2. 4.4.2.1.2 I2C Loading Process
            1. 4.4.2.1.2.1 Loading a Boot Image From EEPROM
      3. 4.4.3  SD Card Boot
        1. 4.4.3.1 SD Card Bootloader Operation
      4. 4.4.4  eMMC Boot
        1. 4.4.4.1 eMMC Bootloader Operation
      5. 4.4.5  Ethernet Boot
        1. 4.4.5.1 Ethernet Bootloader Operation
          1. 4.4.5.1.1 Ethernet Initialization Process
          2. 4.4.5.1.2 Ethernet Loading Process
            1. 4.4.5.1.2.1 Ethernet Boot Data Formats
              1. 4.4.5.1.2.1.1 Limitations
              2. 4.4.5.1.2.1.2 BOOTP Request
                1. 4.4.5.1.2.1.2.1 MAC Header (DIX)
                2. 4.4.5.1.2.1.2.2 IPv4 Header
                3. 4.4.5.1.2.1.2.3 UDP Header
                4. 4.4.5.1.2.1.2.4 BOOTP Payload
                5. 4.4.5.1.2.1.2.5 TFTP
          3. 4.4.5.1.3 Ethernet Hand Over Process
      6. 4.4.6  USB Boot
        1. 4.4.6.1 USB Bootloader Operation
          1. 4.4.6.1.1 USB-Specific Attributes
            1. 4.4.6.1.1.1 DFU Device Mode
        2. 4.4.6.2 Limitations for USB DFU and PCIe boot modes
      7. 4.4.7  PCIe Boot
        1. 4.4.7.1 PCIe Bootloader Operation
          1. 4.4.7.1.1 PCIe Initialization Process
          2. 4.4.7.1.2 PCIe Loading Process
        2. 4.4.7.2 Limitations for USB DFU and PCIe boot modes
      8. 4.4.8  UART Boot
        1. 4.4.8.1 UART Bootloader Operation
          1. 4.4.8.1.1 Initialization Process
          2. 4.4.8.1.2 UART Loading Process
            1. 4.4.8.1.2.1 UART XMODEM
          3. 4.4.8.1.3 UART Hand-Over Process
      9. 4.4.9  GPMC NOR Boot
        1. 4.4.9.1 GPMC NOR Bootloader Operation
          1. 4.4.9.1.1 GPMC NOR Initialization Process
          2. 4.4.9.1.2 GPMC NOR Loading Process
      10. 4.4.10 GPMC NAND Boot
        1. 4.4.10.1 GPMC NAND Bootloader Operation
      11. 4.4.11 No boot/Development boot
    5. 4.5 PLL Configuration
    6. 4.6 Boot Parameter Tables
      1. 4.6.1  Common Header
      2. 4.6.2  PLL Setup
      3. 4.6.3  OSPI/QSPI/SPI Boot Parameter Table
      4. 4.6.4  UART Boot Parameter Table
      5. 4.6.5  PCIe Boot Parameter Table
      6. 4.6.6  I2C Boot Parameter Table
      7. 4.6.7  MMCSD/eMMC Boot Parameter Table
      8. 4.6.8  Ethernet Boot Parameter Table
      9. 4.6.9  xSPI Boot Parameter Table
      10. 4.6.10 USB DFU Boot Parameter Table
      11. 4.6.11 USB MSC Boot Parameter Table
      12. 4.6.12 GPMC NOR Boot Parameter Table
      13. 4.6.13 GPMC NAND Boot Parameter Table
    7. 4.7 Boot Image Format
      1. 4.7.1 Overall Structure
      2. 4.7.2 X.509 Certificate
      3. 4.7.3 Organizational Identifier (OID)
      4. 4.7.4 X.509 Extensions Specific to Boot
        1. 4.7.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.7.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.7.5 Extended Boot Info Extension
        1. 4.7.5.1 Impact on HS Device
        2. 4.7.5.2 Extended Boot Info Details
        3. 4.7.5.3 Certificate / Component Types
        4. 4.7.5.4 Extended Boot Encryption Info
        5. 4.7.5.5 Component Ordering
        6. 4.7.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.7.5.7 Device Type and Extended Boot Extension
      6. 4.7.6 Generating X.509 Certificates
        1. 4.7.6.1 Key Generation
          1. 4.7.6.1.1 Degenerate RSA Keys
        2. 4.7.6.2 Configuration Script
        3. 4.7.6.3 Image Data
    8. 4.8 Boot Memory Maps
      1. 4.8.1 Memory Layout/MPU
      2. 4.8.2 Global Memory Addresses Used by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0
        1. 5.1.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Overview
        2. 5.1.1.2 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Integration
        3. 5.1.1.3 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.1.3.1 Description for CTRL_MMR0 and PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.1.3.1.1 Pad Configuration Registers
            2. 5.1.1.3.1.2 Kick Protection Registers
            3. 5.1.1.3.1.3 Proxy Addressing Registers
            4. 5.1.1.3.1.4 CTRL_MMR0 Module Interrupts
            5. 5.1.1.3.1.5 EHRPWM/EQEP Control and Status Registers
            6. 5.1.1.3.1.6 Clock Muxing and Division Registers
            7. 5.1.1.3.1.7 Ethernet Port Operation Control Registers
            8. 5.1.1.3.1.8 DDRSS Dynamic Frequency Change Registers
            9. 5.1.1.3.1.9 Device Feature Registers
        4. 5.1.1.4 Pad Configuration Registers
          1. 5.1.1.4.1 Pad Configuration Register Functional Description
          2. 5.1.1.4.2 Pad Configuration Ball Names
          3. 5.1.1.4.3 PADCFG_CTRL0_CFG0 Registers
        5. 5.1.1.5 CTRL_MMR0 Registers
        6. 5.1.1.6 MAIN_SEC_MMR0_CFG2 Registers
        7. 5.1.1.7 MAIN_SEC_MMR0_CFG0 Registers
      2. 5.1.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0
        1. 5.1.2.1 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.2.3.1.1 Pad Configuration Registers
            2. 5.1.2.3.1.2 Kick Protection Registers
            3. 5.1.2.3.1.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Module Interrupts
            4. 5.1.2.3.1.4 Clock Muxing and Division Registers
            5. 5.1.2.3.1.5 I/O Debounce Control Registers
            6. 5.1.2.3.1.6 PRG Related Registers
            7. 5.1.2.3.1.7 POK Module Registers
        4. 5.1.2.4 MCU_PADCFG_CTRL0_CFG0 Registers
        5. 5.1.2.5 MCU_CTRL_MMR0 Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power System Modules
          1. 5.2.2.1.1 Power OK (POK) Modules
            1. 5.2.2.1.1.1 Configuration Registers
          2. 5.2.2.1.2 Power on Reset (POR) Module
            1. 5.2.2.1.2.1 POR Overview
            2. 5.2.2.1.2.2 POR Integration
          3. 5.2.2.1.3 PoR/Reset Generator (PRG) Modules
            1. 5.2.2.1.3.1 PRG Overview
          4. 5.2.2.1.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.1.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.1.5.1 VTM Overview
              1. 5.2.2.1.5.1.1 VTM Features
              2. 5.2.2.1.5.1.2 VTM Not Supported Features
            2. 5.2.2.1.5.2 VTM Functional Description
              1. 5.2.2.1.5.2.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.1.5.2.1.1 10-bit Temperature Values Versus Temperature
          6. 5.2.2.1.6 Integrated Low-dropout Regulator (LDO)
            1. 5.2.2.1.6.1 SDIO LDO Overview
        2. 5.2.2.2 Power Control Modules
          1. 5.2.2.2.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.2.1.1 PSC Terminology
            2. 5.2.2.2.1.2 PSC Features
            3. 5.2.2.2.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.2.1.3.1 Device Power-Management Layout
            4. 5.2.2.2.1.4 PSC: Executing State Transitions
              1. 5.2.2.2.1.4.1 Power Domain State Transitions
              2. 5.2.2.2.1.4.2 Module State Transitions
              3. 5.2.2.2.1.4.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.2.1.4.4 Recommendations for Power Domain/Module Sequencing
            5. 5.2.2.2.1.5 LPSC Dependencies Overview
          2. 5.2.2.2.2 DMSC-L Power Management Overview
            1. 5.2.2.2.2.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Device Power States and Transitions
      4. 5.2.4 Thermal Management
      5. 5.2.5 Power Registers
        1. 5.2.5.1 VTM Registers
        2. 5.2.5.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Overview
        1. 5.3.1.1 MAIN Domain Supported Resets
        2. 5.3.1.2 MCU Domain Supported Resets
        3. 5.3.1.3 Reset Terminology
        4. 5.3.1.4 Reset Architecture
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
        1. 5.3.3.1 Reset Source Status Registers
        2. 5.3.3.2 MCU_RESETSTATz Status Pin
        3. 5.3.3.3 MCU_SAFETY_ERRORn Status Pin
        4. 5.3.3.4 MAIN_RESETSTATz Status Pin
        5. 5.3.3.5 MAIN_PORz_OUT Status Pin
      4. 5.3.4 Reset Controls
        1. 5.3.4.1 Reset Control Registers
        2. 5.3.4.2 Reset Isolation
      5. 5.3.5 Reset Details
        1. 5.3.5.1 POR Resets
          1. 5.3.5.1.1 SW_MAIN_PORz Reset
          2. 5.3.5.1.2 MCU_PORz Reset
        2. 5.3.5.2 Warm Resets
          1. 5.3.5.2.1 MAIN Domain Warm Reset Sequence Flow
          2. 5.3.5.2.2 MAIN_RESETz_REQ Reset
          3. 5.3.5.2.3 SW_MAIN_WARMRSTz Reset
          4. 5.3.5.2.4 MCU_RESETz Reset
          5. 5.3.5.2.5 SW_MCU_WARMRSTz Reset
        3. 5.3.5.3 DMSC-L Resets
          1. 5.3.5.3.1 DMSC_COLD_OUT_RST_n MAIN Reset
          2. 5.3.5.3.2 DMSC_WARM_OUT_RST_n MAIN Reset
          3. 5.3.5.3.3 DMSC_COLD_OUT_RST_n MCU Reset
        4. 5.3.5.4 VTM Thermal Alert Reset
        5. 5.3.5.5 MAIN ESM_ERRORz Reset
        6. 5.3.5.6 MCU ESM_ERRORz Reset
        7. 5.3.5.7 Reset - High Heating Value (HHV)
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 1800
          3. 5.4.3.1.3 OBSCLK0 Pin
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillator with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 MCU Domain PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRACF Type Output Clocks
              2. 5.4.5.4.1.2.2 PLL Lock
              3. 5.4.5.4.1.2.3 HSDIVIDER
              4. 5.4.5.4.1.2.4 ICG Module
              5. 5.4.5.4.1.2.5 PLL Power Down
              6. 5.4.5.4.1.2.6 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Clocking Registers
        1. 5.4.6.1 PLLCTRL0 Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 MCU_PLL0_CFG Registers
  8. 6 Processors and Accelerators
    1. 6.1 Arm Cortex-A53 Subsystem (A53SS)
      1. 6.1.1 A53SS Overview
        1. 6.1.1.1 A53SS Introduction
        2. 6.1.1.2 A53SS Features
      2. 6.1.2 A53SS Integration
      3. 6.1.3 A53SS Functional Description
        1. 6.1.3.1  A53SS Block Diagram
        2. 6.1.3.2  Arm Cortex-A53 Cluster
        3. 6.1.3.3  A53SS Interfaces and Async Bridges
        4. 6.1.3.4  A53SS Interrupts
          1. 6.1.3.4.1 A53SS Interrupt Inputs
          2. 6.1.3.4.2 A53SS Interrupt Outputs
        5. 6.1.3.5  A53SS Power Management and Clocking
          1. 6.1.3.5.1 A53SS Power Management
          2. 6.1.3.5.2 A53SS Clocking
        6. 6.1.3.6  A53SS Debug
        7. 6.1.3.7  A53SS Global and Debug Timestamps
        8. 6.1.3.8  A53SS Watchdog
        9. 6.1.3.9  A53SS Functional Safety - ECC Error Injection Support
          1. 6.1.3.9.1 A53 ECC Aggregators During Low Power States
          2. 6.1.3.9.2 Auto-initialization of Memories
          3. 6.1.3.9.3 A53 SRAM Safety
          4. 6.1.3.9.4 A53 SRAM ECC Aggregator Configurations
        10. 6.1.3.10 A53SS Boot
        11. 6.1.3.11 A53SS Interprocessor Communication
      4. 6.1.4 A53SS Registers
        1. 6.1.4.1 A53SS Registers
    2. 6.2 Arm Cortex R5F Subsystem (R5FSS)
      1. 6.2.1 R5FSS Overview
        1. 6.2.1.1 R5FSS Features
        2. 6.2.1.2 R5FSS Not Supported Features
      2. 6.2.2 R5FSS Integration
        1. 6.2.2.1 R5FSS Integration in MAIN Domain
      3. 6.2.3 R5FSS Functional Description
        1. 6.2.3.1  R5FSS Block Diagram
        2. 6.2.3.2  R5FSS Cortex-R5F Core
          1. 6.2.3.2.1 L1 Caches
          2. 6.2.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.2.3.2.3 R5FSS Special Signals
        3. 6.2.3.3  R5FSS Interfaces
          1. 6.2.3.3.1 Initiator Interfaces
          2. 6.2.3.3.2 Target Interfaces
        4. 6.2.3.4  R5FSS Power, Clocking and Reset
          1. 6.2.3.4.1 R5FSS Power
          2. 6.2.3.4.2 R5FSS Clocking
          3. 6.2.3.4.3 R5FSS Reset
        5. 6.2.3.5  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.2.3.5.1 VIM Overview
          2. 6.2.3.5.2 VIM Interrupt Inputs
          3. 6.2.3.5.3 VIM Interrupt Outputs
          4. 6.2.3.5.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.2.3.5.5 VIM Interrupt Prioritization
          6. 6.2.3.5.6 VIM ECC Support
          7. 6.2.3.5.7 VIM IDLE State
          8. 6.2.3.5.8 VIM Interrupt Handling
            1. 6.2.3.5.8.1 Servicing IRQ Through Vector Interface
            2. 6.2.3.5.8.2 Servicing IRQ Through MMR Interface
            3. 6.2.3.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.2.3.5.8.4 Servicing FIQ
            5. 6.2.3.5.8.5 Servicing FIQ (Alternative)
        6. 6.2.3.6  R5FSS Region Address Translation (RAT)
          1. 6.2.3.6.1 R5FSS Usage
          2. 6.2.3.6.2 RAT Function
          3. 6.2.3.6.3 How to use RAT Block in R5
          4. 6.2.3.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
        7. 6.2.3.7  R5FSS ECC Support
        8. 6.2.3.8  R5FSS Memory View
        9. 6.2.3.9  R5FSS Interrupts
        10. 6.2.3.10 R5FSS Debug and Trace
        11. 6.2.3.11 R5FSS Boot Options
        12. 6.2.3.12 R5FSS Core Memory ECC Events
      4. 6.2.4 R5FSS Registers
        1. 6.2.4.1 R5FSS_MPIDR Register
        2. 6.2.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.2.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.2.4.4 R5FSS_VIM Registers
        5. 6.2.4.5 R5FSS_RAT Registers
        6. 6.2.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
    3. 6.3 Cortex-M4F Subsystem (MCU_M4FSS)
      1. 6.3.1 MCU_M4FSS Overview
        1. 6.3.1.1 MCU_M4FSS Features
        2. 6.3.1.2 MCU_M4FSS Not Supported Features
      2. 6.3.2 MCU_M4FSS Integration
      3. 6.3.3 MCU_M4FSS Functional Description
        1. 6.3.3.1  MCU_M4FSS Block Diagram
        2. 6.3.3.2  MCU_M4FSS Processor
        3. 6.3.3.3  MCU_M4FSS Internal RAMs
        4. 6.3.3.4  MCU_M4FSS Interfaces
        5. 6.3.3.5  MCU_M4FSS Power, Clocking and Reset
          1. 6.3.3.5.1 MCU_M4FSS Power
          2. 6.3.3.5.2 MCU_M4FSS Clocking
          3. 6.3.3.5.3 MCU_M4FSS Reset
        6. 6.3.3.6  MCU_M4FSS Memory View
        7. 6.3.3.7  MCU_M4FSS RAT
          1. 6.3.3.7.1 Why RAT is needed for M4F
          2. 6.3.3.7.2 RAT Function
          3. 6.3.3.7.3 How to use RAT Block in Blazar M4F
        8. 6.3.3.8  MCU_M4FSS ECC Support
        9. 6.3.3.9  MCU_M4FSS Interrupts
        10. 6.3.3.10 MCU_M4FSS Debug and Trace
        11. 6.3.3.11 MCU_M4FSS Time Sync
        12. 6.3.3.12 MCU_M4FSS SysTick
        13. 6.3.3.13 MCU_M4FSS Initialization
      4. 6.3.4 MCU_M4FSS Registers
        1. 6.3.4.1 M4FSS_RAT_0 Registers
          1. 6.3.4.1.1  RAT__CFG__MMRS_M4FSS_RAT_0_PID Registers
          2. 6.3.4.1.2  RAT__CFG__MMRS_M4FSS_RAT_0_CONFIG Registers
          3. 6.3.4.1.3  RAT__CFG__MMRS_M4FSS_RAT_0_DESTINATION_ID Registers
          4. 6.3.4.1.4  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_CONTROL Registers
          5. 6.3.4.1.5  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER0 Registers
          6. 6.3.4.1.6  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_HEADER1 Registers
          7. 6.3.4.1.7  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA0 Registers
          8. 6.3.4.1.8  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA1 Registers
          9. 6.3.4.1.9  RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA2 Registers
          10. 6.3.4.1.10 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_LOGGING_DATA3 Registers
          11. 6.3.4.1.11 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_SET Registers
          12. 6.3.4.1.12 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_PEND_CLEAR Registers
          13. 6.3.4.1.13 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_SET Registers
          14. 6.3.4.1.14 RAT__CFG__MMRS_M4FSS_RAT_0_EXCEPTION_ENABLE_CLEAR Registers
          15. 6.3.4.1.15 RAT__CFG__MMRS_M4FSS_RAT_0_EOI_REG Registers
          16. 6.3.4.1.16 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_CTRL_J Registers
          17. 6.3.4.1.17 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_BASE_J Registers
          18. 6.3.4.1.18 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_L_J Registers
          19. 6.3.4.1.19 RAT__CFG__MMRS_M4FSS_RAT_0_REGION_TRANS_U_J Registers
          20. 6.3.4.1.20 Access Table
    4. 6.4 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      1. 6.4.1  PRU_ICSSG Overview
        1. 6.4.1.1 PRU_ICSSG Key Features
        2. 6.4.1.2 Not Supported Features
      2. 6.4.2  PRU_ICSSG Environment
        1. 6.4.2.1 PRU_ICSSG Internal Pinmux
          1.        PRU_ICSSG I/O Signals
        2. 6.4.2.2 PRU_ICSSG Fast GPIO pins
      3. 6.4.3  PRU_ICSSG Integration
        1.       PRU_ICSSG Clocks
      4. 6.4.4  PRU_ICSSG Top Level Resources Functional Description
        1. 6.4.4.1 PRU_ICSSG Reset Management
        2. 6.4.4.2 PRU_ICSSG Power and Clock Management
          1. 6.4.4.2.1 PRU_ICSSG CORE Clock Generation
          2. 6.4.4.2.2 PRU_ICSSG Idle State
          3. 6.4.4.2.3 PRU_ICSSG Protect
          4. 6.4.4.2.4 Module Clock Configurations at PRU_ICSSG Top Level
        3. 6.4.4.3 Other PRU_ICSSG Module Functional Registers at Subsystem Level
        4. 6.4.4.4 PRU_ICSSG Memory Maps
          1. 6.4.4.4.1 PRU_ICSSG Local Memory Map
            1. 6.4.4.4.1.1 PRU_ICSSG Local Instruction Memory Map
            2. 6.4.4.4.1.2 PRU_ICSSG Local Data Memory Map
          2. 6.4.4.4.2 PRU_ICSSG Global Memory Map
      5. 6.4.5  PRU_ICSSG PRU Cores
        1. 6.4.5.1 PRU Cores Overview
        2. 6.4.5.2 PRU Cores Functional Description
          1. 6.4.5.2.1 PRUs Constant Table
          2. 6.4.5.2.2 PRU Module Interface
            1. 6.4.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 6.4.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 6.4.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 6.4.5.2.2.3.1 PRU EGPIs Direct Input
              2. 6.4.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 6.4.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 6.4.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 6.4.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 6.4.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 6.4.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 4.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 6.4.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 6.4.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 6.4.5.2.2.3.5.3 Sigma Delta Description
                4. 6.4.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 6.4.5.2.2.3.6 Three Channel Peripheral Interface
                1. 6.4.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 6.4.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 6.4.5.2.2.3.6.3 Clock Generation
                  1. 4.5.2.2.3.6.3.1 Configuration
                  2. 4.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 4.5.2.2.3.6.3.3 Stop Conditions
                4. 6.4.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 4.5.2.2.3.6.4.1 Clock Generation
                  2. 4.5.2.2.3.6.4.2 TX - Single Shot
                  3. 4.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 4.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 6.4.5.3 PRU_ICSSG RAM Index Allocation
      6. 6.4.6  PRU_ICSSG Broadside Accelerators
        1. 6.4.6.1 PRU_ICSSG Broadside Accelerators Overview
        2. 6.4.6.2 PRU_ICSSG Data Processing Accelerators Functional
          1. 6.4.6.2.1  PRU Multiplier with Accumulation (MPY/MAC)
            1. 6.4.6.2.1.1 PRU MAC Operations
              1. 6.4.6.2.1.1.1 PRU versus MAC Interface
              2. 6.4.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 6.4.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 6.4.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 6.4.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 6.4.6.2.2  PRU CRC16/32 Module
            1. 6.4.6.2.2.1 PRU and CRC16/32 Interface
            2. 6.4.6.2.2.2 CRC Programming Model
            3. 6.4.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 6.4.6.2.3  PRU_ICSSG Scratch Pad Memory
            1. 6.4.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 6.4.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 6.4.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 6.4.6.2.3.2.2 Scratch Pad Operations Examples
          4. 6.4.6.2.4  PRU_ICSSG IPC Scratch Pad Memory
          5. 6.4.6.2.5  PRU_ICSSG Broadside (BS) RAM
            1. 6.4.6.2.5.1 Programming the BS RAM
          6. 6.4.6.2.6  PRU_ICSSG SUM32 Hardware Accelerator
          7. 6.4.6.2.7  PRU_ICSSG Byte Swap (BSWAP)
            1. 6.4.6.2.7.1 Byte Order Swap Function
            2. 6.4.6.2.7.2 4_8 Function
            3. 6.4.6.2.7.3 4_16 Function
          8. 6.4.6.2.8  PRU_ICSSG Task Manager
            1. 6.4.6.2.8.1 Task Manager General Purpose Mode
              1. 6.4.6.2.8.1.1 Tasks and Sub-tasks
              2. 6.4.6.2.8.1.2 Task Manager Hardware Context Switching
              3. 6.4.6.2.8.1.3 Task Manager Programming Guide
            2. 6.4.6.2.8.2 Task Manager RX_TX Mode
              1. 6.4.6.2.8.2.1 RX_TX Task Manager Features
              2. 6.4.6.2.8.2.2 Tasks and Sub-tasks
          9. 6.4.6.2.9  PRU_ICSSG Spinlock
            1. 6.4.6.2.9.1 PRU0/1 and RTU_PRU0/1 Spinlock Interface
          10. 6.4.6.2.10 PRU_ICSSG Filter Data Base (FDB)
            1. 6.4.6.2.10.1 FDB Modes of operation
              1. 6.4.6.2.10.1.1 FDB LUT: Hardware operation (HSR Disabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 0h)
              2. 6.4.6.2.10.1.2 FDB LUT: Hardware operation (HSR Enabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 1h)
              3. 6.4.6.2.10.1.3 8KB/16KB Generic broadside RAM mode of operation
                1. 6.4.6.2.10.1.3.1 Broadside (BS) Mapping
              4. 6.4.6.2.10.1.4 FDB General purpose compare mode operation
        3. 6.4.6.3 PRU_ICSSG Data Movement Accelerators Functional
          1. 6.4.6.3.1 PRU_ICSSG XFR2VBUS Hardware Accelerator
            1. 6.4.6.3.1.1 Blocking Conditions
            2. 6.4.6.3.1.2 Read Operation with Auto Disabled
            3. 6.4.6.3.1.3 Read Operation with Auto Enabled
            4. 6.4.6.3.1.4 Write Operation with Auto Disabled
            5. 6.4.6.3.1.5 RTU_PRU/ PRU to XFR2VBUS Interface
            6. 6.4.6.3.1.6 XFR2VBUS Programming Model
          2. 6.4.6.3.2 PRU_ICSSG XFRDMA Functional Operation
            1. 6.4.6.3.2.1 XFRDMA: XFR Bus
              1. 6.4.6.3.2.1.1 XFRDMA: XFR Status
              2. 6.4.6.3.2.1.2 XFRDMA: XFR Bus XOUT
              3. 6.4.6.3.2.1.3 XFRDMA: XFR Bus XOUXFRDMA Functional Operation T Alignment
              4. 6.4.6.3.2.1.4 XFRDMA: XFR Bus XIN
                1. 6.4.6.3.2.1.4.1 XFRDMA: XFR Bus XIN Alignment
            2. 6.4.6.3.2.2 XFRDMA: PSI-L Bus
              1. 6.4.6.3.2.2.1 PRU XFRPSI Mapping
            3. 6.4.6.3.2.3 XFRDMA: Temporary FIFOs
              1. 6.4.6.3.2.3.1 XFRDMA: FIFO Stalls
          3. 6.4.6.3.3 PRU_ICSSG XFR2TR Ring Accelerator
            1. 6.4.6.3.3.1 XFR2TR Programming Model
      7. 6.4.7  PRU_ICSSG Local INTC
        1. 6.4.7.1 PRU_ICSSG Interrupt Controller Functional Description
          1. 6.4.7.1.1 PRU_ICSSG Interrupt Controller Events
          2. 6.4.7.1.2 PRU_ICSSG Interrupt Controller System Events Flow
            1. 6.4.7.1.2.1 PRU_ICSSG Interrupt Processing
              1. 6.4.7.1.2.1.1 PRU_ICSSG Interrupt Enabling
            2. 6.4.7.1.2.2 PRU_ICSSG Interrupt Status Checking
            3. 6.4.7.1.2.3 PRU_ICSSG Interrupt Channel Mapping
              1. 6.4.7.1.2.3.1 PRU_ICSSG Host Interrupt Mapping
              2. 6.4.7.1.2.3.2 PRU_ICSSG Interrupt Prioritization
            4. 6.4.7.1.2.4 PRU_ICSSG Interrupt Nesting
            5. 6.4.7.1.2.5 PRU_ICSSG Interrupt Status Clearing
          3. 6.4.7.1.3 PRU_ICSSG Interrupt Disabling
        2. 6.4.7.2 PRU_ICSSG Interrupt Controller Basic Programming Model
        3. 6.4.7.3 PRU_ICSSG Interrupt Requests Mapping
      8. 6.4.8  PRU_ICSSG UART Module
        1. 6.4.8.1 PRU_ICSSG UART Overview
        2. 6.4.8.2 PRU_ICSSG UART Environment
          1. 6.4.8.2.1 PRU_ICSSG UART Pin Multiplexing
          2. 6.4.8.2.2 PRU_ICSSG UART Signal Descriptions
          3. 6.4.8.2.3 PRU_ICSSG UART Protocol Description and Data Format
            1. 6.4.8.2.3.1 PRU_ICSSG UART Transmission Protocol
            2. 6.4.8.2.3.2 PRU_ICSSG UART Reception Protocol
            3. 6.4.8.2.3.3 PRU_ICSSG UART Data Format
              1. 6.4.8.2.3.3.1 Frame Formatting
          4. 6.4.8.2.4 PRU_ICSSG UART Clock Generation and Control
        3. 6.4.8.3 PRU_ICSSG UART Functional Description
          1. 6.4.8.3.1 PRU_ICSSG UART Functional Block Diagram
          2. 6.4.8.3.2 PRU_ICSSG UART Reset Considerations
            1. 6.4.8.3.2.1 PRU_ICSSG UART Software Reset Considerations
            2. 6.4.8.3.2.2 PRU_ICSSG UART Hardware Reset Considerations
          3. 6.4.8.3.3 PRU_ICSSG UART Power Management
          4. 6.4.8.3.4 PRU_ICSSG UART Interrupt Support
            1. 6.4.8.3.4.1 PRU_ICSSG UART Interrupt Events and Requests
            2. 6.4.8.3.4.2 PRU_ICSSG UART Interrupt Multiplexing
          5. 6.4.8.3.5 2134
          6. 6.4.8.3.6 PRU_ICSSG UART DMA Event Support
          7. 6.4.8.3.7 PRU_ICSSG UART Operations
            1. 6.4.8.3.7.1 PRU_ICSSG UART FIFO Modes
              1. 6.4.8.3.7.1.1 PRU_ICSSG UART FIFO Interrupt Mode
              2. 6.4.8.3.7.1.2 PRU_ICSSG UART FIFO Poll Mode
            2. 6.4.8.3.7.2 PRU_ICSSG UART Autoflow Control
              1. 6.4.8.3.7.2.1 PRU_ICSSG UART Signal UART0_RTS Behavior
              2. 6.4.8.3.7.2.2 PRU_ICSSG UART Signal UART0_CTS Behavior
            3. 6.4.8.3.7.3 PRU_ICSSG UART Loopback Control
          8. 6.4.8.3.8 PRU_ICSSG UART Emulation Considerations
          9. 6.4.8.3.9 PRU_ICSSG UART Exception Processing
            1. 6.4.8.3.9.1 PRU_ICSSG UART Divisor Latch Not Programmed
            2. 6.4.8.3.9.2 Changing Operating Mode During Busy Serial Communication of PRU_ICSSG UART
      9. 6.4.9  PRU_ICSSG ECAP Module
        1. 6.4.9.1 PRU_ICSSG ECAP Functional Description
      10. 6.4.10 PRU_ICSSG PWM Module
        1. 6.4.10.1 PRU_ICSSG PWM Supported Features
        2. 6.4.10.2 PRU_ICSSG PWM States Overview
        3. 6.4.10.3 PRU_ICSSG PWM Trip State Logic
        4. 6.4.10.4 PRU_ICSSG PWM Glitch Filter
      11. 6.4.11 PRU_ICSSG MII_G_RT Module
        1. 6.4.11.1 PRU_ICSSG MII_G_RT Introduction
          1. 6.4.11.1.1 PRU_ICSSG MII_G_RT Features
          2. 6.4.11.1.2 Unsupported Features
          3. 6.4.11.1.3 PRU_ICSSG MII_G_RT Block Diagram
        2. 6.4.11.2 MII_G_RT Functional Description
          1. 6.4.11.2.1 MII_G_RT Data Path Configuration
            1. 6.4.11.2.1.1 Auto-forward with Optional PRU Snoop
            2. 6.4.11.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 6.4.11.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 6.4.11.2.2 MII_G_RT Definition and Terms
            1. 6.4.11.2.2.1 MII_G_RT Data Frame Structure
            2. 6.4.11.2.2.2 PRU R30 and R31
            3. 6.4.11.2.2.3 RX and TX L1 FIFO Data Movement
            4. 6.4.11.2.2.4 Receive CRC Computation
            5. 6.4.11.2.2.5 Transmit CRC Computation
            6. 6.4.11.2.2.6 Transmit CRC Computation for fragmented frames
          3. 6.4.11.2.3 RX MII Interface
            1. 6.4.11.2.3.1 RX MII Receive Data Latch
            2. 6.4.11.2.3.2 RX MII Start of Frame Detection
            3. 6.4.11.2.3.3 CRC Error Detection
            4. 6.4.11.2.3.4 RX Error Detection and Action
            5. 6.4.11.2.3.5 RX Data Path Options to PRU
            6. 6.4.11.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 6.4.11.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 6.4.11.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_G_CFG[2] RX_L2_G_EN= 0h)
              2. 6.4.11.2.3.7.2 2181
              3. 6.4.11.2.3.7.3 RX L2 Status for IET Type 1/Type 2 (when MII_G_RT_ICSS_G_CFG[2] RX_L2_G_EN = 1h)
              4. 6.4.11.2.3.7.4 2183
              5. 6.4.11.2.3.7.5 Broadside Stitch FIFO
              6. 6.4.11.2.3.7.6 MII_G_RT RX Classifier
                1. 6.4.11.2.3.7.6.1 RX Rate Counter Block
                2. 6.4.11.2.3.7.6.2 RX Rate Hit Mapping
                3. 6.4.11.2.3.7.6.3 Traffic Class Selector Block
                4. 6.4.11.2.3.7.6.4 PRU_ICSSG RX L2 Filter Block
                  1. 4.11.2.3.7.6.4.1 PRU_ICSSG RX L2 Filter Operation
                  2. 4.11.2.3.7.6.4.2 PRU_ICSSG RX L2 Filter - Type 1 (MAC Filter) Operation
                  3. 4.11.2.3.7.6.4.3 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Operation
                  4. 4.11.2.3.7.6.4.4 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Auto Restart operation
                  5. 4.11.2.3.7.6.4.5 RX SA Hash
                  6. 4.11.2.3.7.6.4.6 RX Connection Hash
          4. 6.4.11.2.4 PRU_ICSSG TX MII Interface
            1. 6.4.11.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 6.4.11.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 6.4.11.2.4.1.1.1 TX L2 FIFO Features
                2. 6.4.11.2.4.1.1.2 2200
                3. 6.4.11.2.4.1.1.3 TX Insertion
                4. 6.4.11.2.4.1.1.4 TX Preemption
                  1. 4.11.2.4.1.1.4.1 TX Preemption Programming Model
              2. 6.4.11.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 6.4.11.2.5 PRU R31 Command Interface
          6. 6.4.11.2.6 Other Configuration Options
            1. 6.4.11.2.6.1 Nibble and Byte Order
            2. 6.4.11.2.6.2 MII_G_RT Preamble Source
            3. 6.4.11.2.6.3 PRU and MII Port Multiplexer
              1. 6.4.11.2.6.3.1 Receive Multiplexer
              2. 6.4.11.2.6.3.2 Transmit Multiplexer
            4. 6.4.11.2.6.4 RX L2 Scratch Pad
        3. 6.4.11.3 PRU_ICSSG PA_STATS Module
          1. 6.4.11.3.1 Statistics Page
          2. 6.4.11.3.2 Statistics Collection Modes
            1. 6.4.11.3.2.1 Manual Read Mode
          3. 6.4.11.3.3 Clock Stop
      12. 6.4.12 PRU_ICSSG MII MDIO Module
        1. 6.4.12.1 PRU_ICSSG MII MDIO Overview
        2. 6.4.12.2 PRU_ICSSG MII MDIO Functional Description
          1. 6.4.12.2.1 MDIO Clause 22 Frame Formats
            1. 6.4.12.2.1.1 PRU-ICSSG MDIO Control and Interface Signals
          2. 6.4.12.2.2 MDIO Clause 45 Frame Formats
          3. 6.4.12.2.3 PRU_ICSSG MII MDIO Interractions
          4. 6.4.12.2.4 PRU_ICSSG MII MDIO Interrupts
            1. 6.4.12.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 6.4.12.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 6.4.12.2.5 Manual Mode
        3. 6.4.12.3 PRU_ICSSG MII MDIO Receive/Transmit Frame Host Software Interface
      13. 6.4.13 PRU_ICSSG IEP
        1. 6.4.13.1 PRU_ICSSG IEP Overview
        2. 6.4.13.2 PRU_ICSSG IEP Functional Description
          1. 6.4.13.2.1 PRU_ICSSG IEP Clock Generation
          2. 6.4.13.2.2 PRU_ICSSG IEP Timer
            1. 6.4.13.2.2.1 PRU_ICSSG IEP Timer Features
          3. 6.4.13.2.3 32-Bit Shadow Mode
          4. 6.4.13.2.4 PRU_ICSSG IEP Timer Basic Programming Sequence
          5. 6.4.13.2.5 Industrial Ethernet Mapping
          6. 6.4.13.2.6 PRU_ICSSG IEP Sync0/Sync1 Module
            1. 6.4.13.2.6.1 PRU_ICSSG IEP Sync0/Sync1 Features
            2. 6.4.13.2.6.2 PRU_ICSSG IEP Sync0/Sync1 Generation Modes
          7. 6.4.13.2.7 PRU_ICSSG IEP WatchDog
          8. 6.4.13.2.8 PRU_ICSSG IEP DIGIO
            1. 6.4.13.2.8.1 PRU_ICSSG IEP DIGIO Features
            2. 6.4.13.2.8.2 2245
            3. 6.4.13.2.8.3 PRU_ICSSG IEP DIGIO Block Diagrams
            4. 6.4.13.2.8.4 PRU_ICSSG IEP Basic Programming Model
      14. 6.4.14 PRU_ICSSG Registers
        1. 6.4.14.1  PRU_ICSSG PRU_CTRL, RTU_PRU_CTRL, and TX_PRU_CTRL Registers
        2. 6.4.14.2  PRU_ICSSG PRU_DEBUG, RTU_PRU_DEBUG, and TX_PRU_DEBUG Registers
        3. 6.4.14.3  PRU_ICSSG_ECC_AGGR Registers
        4. 6.4.14.4  PRU_ICSSG_DDRAM Registers
        5. 6.4.14.5  PRU_ICSSG_CFG Registers
        6. 6.4.14.6  PRU_ECAP_ECAP0 Registers
        7. 6.4.14.7  PRU_ICSS_INTC_INTC Registers
        8. 6.4.14.8  PRU_UART_UART0 Registers
        9. 6.4.14.9  PRU_IEP_IEP Registers
        10. 6.4.14.10 PRU_MDIO_MDIO Registers
        11. 6.4.14.11 PRU_MII_RT_MII_RT Registers
        12. 6.4.14.12 PRU_MII_G_RT_MII_G_RT Registers
        13. 6.4.14.13 PRU_ICSSG_PA_STAT Registers
        14. 6.4.14.14 PRU_ICSSG_PA_STAT_QSTAT Registers
        15. 6.4.14.15 PRU_ICSSG_PA_STAT_CSTAT Registers
        16. 6.4.14.16 PRU_PROT_PROTECT Registers
        17. 6.4.14.17 PRU_RAT_SLICE_RAT_SLICE Registers
        18. 6.4.14.18 PRU_TASKS_MGR_TASKS_MGR_PRU_RTU_TX Registers
        19. 6.4.14.19 PRU_ICSSG_RAM Registers
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
      5. 7.1.5 Mailbox Registers
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
      5. 7.2.5 Spinlock Registers
  10. 8 Memory Controllers
    1. 8.1 DDR Subsystem (DDRSS)
      1. 8.1.1 DDRSS Overview
        1. 8.1.1.1 DDRSS Not Supported Features
      2. 8.1.2 DDRSS Environment
      3. 8.1.3 DDRSS Integration
        1. 8.1.3.1 DDRSS Integration in MAIN Domain
      4. 8.1.4 DDRSS Functional Description
        1. 8.1.4.1 Class of Service (CoS)
        2. 8.1.4.2 AXI Write Data All-Strobes
        3. 8.1.4.3 Inline ECC for SDRAM Data
          1. 8.1.4.3.1 ECC Cache
          2. 8.1.4.3.2 ECC Cache Flush
          3. 8.1.4.3.3 ECC Statistics
        4. 8.1.4.4 Address Alias Prevention
        5. 8.1.4.5 AXI Bus Timeout
        6. 8.1.4.6 DDRSS Interrupts
        7. 8.1.4.7 DDRSS Memory Regions
        8. 8.1.4.8 DDRSS Dynamic Frequency Change Interface
        9. 8.1.4.9 DDR Controller Functional Description
          1. 8.1.4.9.1 DDR PHY Interface (DFI)
          2. 8.1.4.9.2 Command Queue
            1. 8.1.4.9.2.1 Placement Logic
            2. 8.1.4.9.2.2 Command Selection Logic
          3. 8.1.4.9.3 Transaction Processing
          4. 8.1.4.9.4 Paging Policy
          5. 8.1.4.9.5 DDR Controller Initialization
      5. 8.1.5 DDR16SS Registers
        1. 8.1.5.1    REGS__SS_CFG__SSCFG_DDR16SS_SS_ID_REV_REG Registers
        2. 8.1.5.2    REGS__SS_CFG__SSCFG_DDR16SS_SS_CTL_REG Registers
        3. 8.1.5.3    REGS__SS_CFG__SSCFG_DDR16SS_V2A_CTL_REG Registers
        4. 8.1.5.4    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_MAT_REG Registers
        5. 8.1.5.5    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_MAT_REG Registers
        6. 8.1.5.6    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_MAT_REG Registers
        7. 8.1.5.7    REGS__SS_CFG__SSCFG_DDR16SS_V2A_DEF_PRI_MAP_REG Registers
        8. 8.1.5.8    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R1_PRI_MAP_REG Registers
        9. 8.1.5.9    REGS__SS_CFG__SSCFG_DDR16SS_V2A_R2_PRI_MAP_REG Registers
        10. 8.1.5.10   REGS__SS_CFG__SSCFG_DDR16SS_V2A_R3_PRI_MAP_REG Registers
        11. 8.1.5.11   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG1_REG Registers
        12. 8.1.5.12   REGS__SS_CFG__SSCFG_DDR16SS_V2A_AERR_LOG2_REG Registers
        13. 8.1.5.13   REGS__SS_CFG__SSCFG_DDR16SS_V2A_BUS_TO Registers
        14. 8.1.5.14   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_RAW_REG Registers
        15. 8.1.5.15   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_STAT_REG Registers
        16. 8.1.5.16   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_SET_REG Registers
        17. 8.1.5.17   REGS__SS_CFG__SSCFG_DDR16SS_V2A_INT_CLR_REG Registers
        18. 8.1.5.18   REGS__SS_CFG__SSCFG_DDR16SS_V2A_EOI_REG Registers
        19. 8.1.5.19   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT_SEL_REG Registers
        20. 8.1.5.20   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT1_REG Registers
        21. 8.1.5.21   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT2_REG Registers
        22. 8.1.5.22   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT3_REG Registers
        23. 8.1.5.23   REGS__SS_CFG__SSCFG_DDR16SS_PERF_CNT4_REG Registers
        24. 8.1.5.24   REGS__SS_CFG__SSCFG_DDR16SS_ECC_CTRL_REG Registers
        25. 8.1.5.25   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_INDX_REG Registers
        26. 8.1.5.26   REGS__SS_CFG__SSCFG_DDR16SS_ECC_RID_VAL_REG Registers
        27. 8.1.5.27   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_STR_ADDR_REG Registers
        28. 8.1.5.28   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R0_END_ADDR_REG Registers
        29. 8.1.5.29   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_STR_ADDR_REG Registers
        30. 8.1.5.30   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R1_END_ADDR_REG Registers
        31. 8.1.5.31   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_STR_ADDR_REG Registers
        32. 8.1.5.32   REGS__SS_CFG__SSCFG_DDR16SS_ECC_R2_END_ADDR_REG Registers
        33. 8.1.5.33   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_CNT_REG Registers
        34. 8.1.5.34   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_THRSH_REG Registers
        35. 8.1.5.35   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_ADR_LOG_REG Registers
        36. 8.1.5.36   REGS__SS_CFG__SSCFG_DDR16SS_ECC_1B_ERR_MSK_LOG_REG Registers
        37. 8.1.5.37   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_ADR_LOG_REG Registers
        38. 8.1.5.38   REGS__SS_CFG__SSCFG_DDR16SS_ECC_2B_ERR_MSK_LOG_REG Registers
        39. 8.1.5.39   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL1_REG Registers
        40. 8.1.5.40   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL2_REG Registers
        41. 8.1.5.41   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL3_REG Registers
        42. 8.1.5.42   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL4_REG Registers
        43. 8.1.5.43   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL5_REG Registers
        44. 8.1.5.44   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL6_REG Registers
        45. 8.1.5.45   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL7_REG Registers
        46. 8.1.5.46   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL8_REG Registers
        47. 8.1.5.47   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL9_REG Registers
        48. 8.1.5.48   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_CTRL10_REG Registers
        49. 8.1.5.49   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT1_REG Registers
        50. 8.1.5.50   REGS__SS_CFG__SSCFG_DDR16SS_PHY_TEST_STAT2_REG Registers
        51. 8.1.5.51   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_0 Registers
        52. 8.1.5.52   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_1 Registers
        53. 8.1.5.53   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_2 Registers
        54. 8.1.5.54   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_3 Registers
        55. 8.1.5.55   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_4 Registers
        56. 8.1.5.56   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_5 Registers
        57. 8.1.5.57   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_6 Registers
        58. 8.1.5.58   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_7 Registers
        59. 8.1.5.59   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_8 Registers
        60. 8.1.5.60   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_9 Registers
        61. 8.1.5.61   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_10 Registers
        62. 8.1.5.62   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_11 Registers
        63. 8.1.5.63   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_12 Registers
        64. 8.1.5.64   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_13 Registers
        65. 8.1.5.65   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_14 Registers
        66. 8.1.5.66   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_15 Registers
        67. 8.1.5.67   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_16 Registers
        68. 8.1.5.68   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_17 Registers
        69. 8.1.5.69   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_18 Registers
        70. 8.1.5.70   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_19 Registers
        71. 8.1.5.71   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_20 Registers
        72. 8.1.5.72   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_21 Registers
        73. 8.1.5.73   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_22 Registers
        74. 8.1.5.74   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_23 Registers
        75. 8.1.5.75   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_24 Registers
        76. 8.1.5.76   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_25 Registers
        77. 8.1.5.77   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_26 Registers
        78. 8.1.5.78   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_27 Registers
        79. 8.1.5.79   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_28 Registers
        80. 8.1.5.80   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_29 Registers
        81. 8.1.5.81   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_30 Registers
        82. 8.1.5.82   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_31 Registers
        83. 8.1.5.83   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_32 Registers
        84. 8.1.5.84   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_33 Registers
        85. 8.1.5.85   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_34 Registers
        86. 8.1.5.86   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_35 Registers
        87. 8.1.5.87   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_36 Registers
        88. 8.1.5.88   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_37 Registers
        89. 8.1.5.89   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_38 Registers
        90. 8.1.5.90   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_39 Registers
        91. 8.1.5.91   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_40 Registers
        92. 8.1.5.92   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_41 Registers
        93. 8.1.5.93   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_42 Registers
        94. 8.1.5.94   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_43 Registers
        95. 8.1.5.95   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_44 Registers
        96. 8.1.5.96   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_45 Registers
        97. 8.1.5.97   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_46 Registers
        98. 8.1.5.98   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_47 Registers
        99. 8.1.5.99   CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_48 Registers
        100. 8.1.5.100  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_49 Registers
        101. 8.1.5.101  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_50 Registers
        102. 8.1.5.102  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_51 Registers
        103. 8.1.5.103  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_52 Registers
        104. 8.1.5.104  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_53 Registers
        105. 8.1.5.105  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_54 Registers
        106. 8.1.5.106  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_55 Registers
        107. 8.1.5.107  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_56 Registers
        108. 8.1.5.108  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_57 Registers
        109. 8.1.5.109  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_58 Registers
        110. 8.1.5.110  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_59 Registers
        111. 8.1.5.111  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_60 Registers
        112. 8.1.5.112  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_61 Registers
        113. 8.1.5.113  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_62 Registers
        114. 8.1.5.114  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_63 Registers
        115. 8.1.5.115  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_64 Registers
        116. 8.1.5.116  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_65 Registers
        117. 8.1.5.117  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_66 Registers
        118. 8.1.5.118  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_67 Registers
        119. 8.1.5.119  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_68 Registers
        120. 8.1.5.120  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_69 Registers
        121. 8.1.5.121  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_70 Registers
        122. 8.1.5.122  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_71 Registers
        123. 8.1.5.123  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_72 Registers
        124. 8.1.5.124  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_73 Registers
        125. 8.1.5.125  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_74 Registers
        126. 8.1.5.126  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_75 Registers
        127. 8.1.5.127  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_76 Registers
        128. 8.1.5.128  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_77 Registers
        129. 8.1.5.129  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_78 Registers
        130. 8.1.5.130  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_79 Registers
        131. 8.1.5.131  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_80 Registers
        132. 8.1.5.132  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_81 Registers
        133. 8.1.5.133  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_82 Registers
        134. 8.1.5.134  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_83 Registers
        135. 8.1.5.135  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_84 Registers
        136. 8.1.5.136  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_85 Registers
        137. 8.1.5.137  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_86 Registers
        138. 8.1.5.138  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_87 Registers
        139. 8.1.5.139  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_88 Registers
        140. 8.1.5.140  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_89 Registers
        141. 8.1.5.141  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_90 Registers
        142. 8.1.5.142  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_91 Registers
        143. 8.1.5.143  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_92 Registers
        144. 8.1.5.144  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_93 Registers
        145. 8.1.5.145  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_94 Registers
        146. 8.1.5.146  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_95 Registers
        147. 8.1.5.147  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_96 Registers
        148. 8.1.5.148  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_97 Registers
        149. 8.1.5.149  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_98 Registers
        150. 8.1.5.150  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_99 Registers
        151. 8.1.5.151  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_100 Registers
        152. 8.1.5.152  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_101 Registers
        153. 8.1.5.153  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_102 Registers
        154. 8.1.5.154  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_103 Registers
        155. 8.1.5.155  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_104 Registers
        156. 8.1.5.156  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_105 Registers
        157. 8.1.5.157  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_106 Registers
        158. 8.1.5.158  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_107 Registers
        159. 8.1.5.159  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_108 Registers
        160. 8.1.5.160  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_109 Registers
        161. 8.1.5.161  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_110 Registers
        162. 8.1.5.162  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_111 Registers
        163. 8.1.5.163  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_112 Registers
        164. 8.1.5.164  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_113 Registers
        165. 8.1.5.165  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_114 Registers
        166. 8.1.5.166  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_115 Registers
        167. 8.1.5.167  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_116 Registers
        168. 8.1.5.168  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_117 Registers
        169. 8.1.5.169  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_118 Registers
        170. 8.1.5.170  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_119 Registers
        171. 8.1.5.171  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_120 Registers
        172. 8.1.5.172  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_121 Registers
        173. 8.1.5.173  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_122 Registers
        174. 8.1.5.174  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_123 Registers
        175. 8.1.5.175  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_124 Registers
        176. 8.1.5.176  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_125 Registers
        177. 8.1.5.177  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_126 Registers
        178. 8.1.5.178  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_127 Registers
        179. 8.1.5.179  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_128 Registers
        180. 8.1.5.180  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_129 Registers
        181. 8.1.5.181  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_130 Registers
        182. 8.1.5.182  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_131 Registers
        183. 8.1.5.183  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_132 Registers
        184. 8.1.5.184  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_133 Registers
        185. 8.1.5.185  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_134 Registers
        186. 8.1.5.186  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_135 Registers
        187. 8.1.5.187  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_136 Registers
        188. 8.1.5.188  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_137 Registers
        189. 8.1.5.189  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_138 Registers
        190. 8.1.5.190  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_139 Registers
        191. 8.1.5.191  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_140 Registers
        192. 8.1.5.192  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_141 Registers
        193. 8.1.5.193  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_142 Registers
        194. 8.1.5.194  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_143 Registers
        195. 8.1.5.195  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_144 Registers
        196. 8.1.5.196  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_145 Registers
        197. 8.1.5.197  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_146 Registers
        198. 8.1.5.198  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_147 Registers
        199. 8.1.5.199  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_148 Registers
        200. 8.1.5.200  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_149 Registers
        201. 8.1.5.201  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_150 Registers
        202. 8.1.5.202  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_151 Registers
        203. 8.1.5.203  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_152 Registers
        204. 8.1.5.204  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_153 Registers
        205. 8.1.5.205  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_154 Registers
        206. 8.1.5.206  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_155 Registers
        207. 8.1.5.207  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_156 Registers
        208. 8.1.5.208  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_157 Registers
        209. 8.1.5.209  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_158 Registers
        210. 8.1.5.210  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_159 Registers
        211. 8.1.5.211  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_160 Registers
        212. 8.1.5.212  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_161 Registers
        213. 8.1.5.213  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_162 Registers
        214. 8.1.5.214  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_163 Registers
        215. 8.1.5.215  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_164 Registers
        216. 8.1.5.216  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_165 Registers
        217. 8.1.5.217  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_166 Registers
        218. 8.1.5.218  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_167 Registers
        219. 8.1.5.219  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_168 Registers
        220. 8.1.5.220  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_169 Registers
        221. 8.1.5.221  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_170 Registers
        222. 8.1.5.222  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_171 Registers
        223. 8.1.5.223  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_172 Registers
        224. 8.1.5.224  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_173 Registers
        225. 8.1.5.225  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_174 Registers
        226. 8.1.5.226  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_175 Registers
        227. 8.1.5.227  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_176 Registers
        228. 8.1.5.228  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_177 Registers
        229. 8.1.5.229  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_178 Registers
        230. 8.1.5.230  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_179 Registers
        231. 8.1.5.231  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_180 Registers
        232. 8.1.5.232  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_181 Registers
        233. 8.1.5.233  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_182 Registers
        234. 8.1.5.234  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_183 Registers
        235. 8.1.5.235  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_184 Registers
        236. 8.1.5.236  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_185 Registers
        237. 8.1.5.237  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_186 Registers
        238. 8.1.5.238  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_187 Registers
        239. 8.1.5.239  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_188 Registers
        240. 8.1.5.240  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_189 Registers
        241. 8.1.5.241  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_190 Registers
        242. 8.1.5.242  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_191 Registers
        243. 8.1.5.243  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_192 Registers
        244. 8.1.5.244  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_193 Registers
        245. 8.1.5.245  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_194 Registers
        246. 8.1.5.246  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_195 Registers
        247. 8.1.5.247  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_196 Registers
        248. 8.1.5.248  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_197 Registers
        249. 8.1.5.249  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_198 Registers
        250. 8.1.5.250  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_199 Registers
        251. 8.1.5.251  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_200 Registers
        252. 8.1.5.252  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_201 Registers
        253. 8.1.5.253  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_202 Registers
        254. 8.1.5.254  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_203 Registers
        255. 8.1.5.255  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_204 Registers
        256. 8.1.5.256  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_205 Registers
        257. 8.1.5.257  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_206 Registers
        258. 8.1.5.258  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_207 Registers
        259. 8.1.5.259  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_208 Registers
        260. 8.1.5.260  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_209 Registers
        261. 8.1.5.261  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_210 Registers
        262. 8.1.5.262  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_211 Registers
        263. 8.1.5.263  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_212 Registers
        264. 8.1.5.264  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_213 Registers
        265. 8.1.5.265  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_214 Registers
        266. 8.1.5.266  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_215 Registers
        267. 8.1.5.267  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_216 Registers
        268. 8.1.5.268  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_217 Registers
        269. 8.1.5.269  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_218 Registers
        270. 8.1.5.270  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_219 Registers
        271. 8.1.5.271  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_220 Registers
        272. 8.1.5.272  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_221 Registers
        273. 8.1.5.273  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_222 Registers
        274. 8.1.5.274  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_223 Registers
        275. 8.1.5.275  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_224 Registers
        276. 8.1.5.276  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_225 Registers
        277. 8.1.5.277  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_226 Registers
        278. 8.1.5.278  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_227 Registers
        279. 8.1.5.279  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_228 Registers
        280. 8.1.5.280  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_229 Registers
        281. 8.1.5.281  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_230 Registers
        282. 8.1.5.282  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_231 Registers
        283. 8.1.5.283  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_232 Registers
        284. 8.1.5.284  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_233 Registers
        285. 8.1.5.285  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_234 Registers
        286. 8.1.5.286  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_235 Registers
        287. 8.1.5.287  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_236 Registers
        288. 8.1.5.288  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_237 Registers
        289. 8.1.5.289  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_238 Registers
        290. 8.1.5.290  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_239 Registers
        291. 8.1.5.291  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_240 Registers
        292. 8.1.5.292  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_241 Registers
        293. 8.1.5.293  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 Registers
        294. 8.1.5.294  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_243 Registers
        295. 8.1.5.295  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_244 Registers
        296. 8.1.5.296  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_245 Registers
        297. 8.1.5.297  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_246 Registers
        298. 8.1.5.298  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_247 Registers
        299. 8.1.5.299  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_248 Registers
        300. 8.1.5.300  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_249 Registers
        301. 8.1.5.301  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_250 Registers
        302. 8.1.5.302  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_251 Registers
        303. 8.1.5.303  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_252 Registers
        304. 8.1.5.304  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_253 Registers
        305. 8.1.5.305  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_254 Registers
        306. 8.1.5.306  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_255 Registers
        307. 8.1.5.307  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_256 Registers
        308. 8.1.5.308  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_257 Registers
        309. 8.1.5.309  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_258 Registers
        310. 8.1.5.310  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_259 Registers
        311. 8.1.5.311  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_260 Registers
        312. 8.1.5.312  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_261 Registers
        313. 8.1.5.313  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_262 Registers
        314. 8.1.5.314  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_263 Registers
        315. 8.1.5.315  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_264 Registers
        316. 8.1.5.316  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_265 Registers
        317. 8.1.5.317  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_266 Registers
        318. 8.1.5.318  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_267 Registers
        319. 8.1.5.319  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_268 Registers
        320. 8.1.5.320  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_269 Registers
        321. 8.1.5.321  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_270 Registers
        322. 8.1.5.322  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_271 Registers
        323. 8.1.5.323  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_272 Registers
        324. 8.1.5.324  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_273 Registers
        325. 8.1.5.325  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_274 Registers
        326. 8.1.5.326  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_275 Registers
        327. 8.1.5.327  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_276 Registers
        328. 8.1.5.328  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_277 Registers
        329. 8.1.5.329  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_278 Registers
        330. 8.1.5.330  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_279 Registers
        331. 8.1.5.331  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_280 Registers
        332. 8.1.5.332  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_281 Registers
        333. 8.1.5.333  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_282 Registers
        334. 8.1.5.334  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_283 Registers
        335. 8.1.5.335  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_284 Registers
        336. 8.1.5.336  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_285 Registers
        337. 8.1.5.337  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_286 Registers
        338. 8.1.5.338  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_287 Registers
        339. 8.1.5.339  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_288 Registers
        340. 8.1.5.340  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_289 Registers
        341. 8.1.5.341  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_290 Registers
        342. 8.1.5.342  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_291 Registers
        343. 8.1.5.343  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_292 Registers
        344. 8.1.5.344  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_293 Registers
        345. 8.1.5.345  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_294 Registers
        346. 8.1.5.346  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_295 Registers
        347. 8.1.5.347  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_296 Registers
        348. 8.1.5.348  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_297 Registers
        349. 8.1.5.349  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_298 Registers
        350. 8.1.5.350  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_299 Registers
        351. 8.1.5.351  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_300 Registers
        352. 8.1.5.352  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_301 Registers
        353. 8.1.5.353  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_302 Registers
        354. 8.1.5.354  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_303 Registers
        355. 8.1.5.355  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_304 Registers
        356. 8.1.5.356  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_305 Registers
        357. 8.1.5.357  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_306 Registers
        358. 8.1.5.358  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_307 Registers
        359. 8.1.5.359  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_308 Registers
        360. 8.1.5.360  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_309 Registers
        361. 8.1.5.361  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_310 Registers
        362. 8.1.5.362  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_311 Registers
        363. 8.1.5.363  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_312 Registers
        364. 8.1.5.364  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_313 Registers
        365. 8.1.5.365  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_314 Registers
        366. 8.1.5.366  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_315 Registers
        367. 8.1.5.367  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_316 Registers
        368. 8.1.5.368  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_317 Registers
        369. 8.1.5.369  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_318 Registers
        370. 8.1.5.370  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_319 Registers
        371. 8.1.5.371  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_320 Registers
        372. 8.1.5.372  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_321 Registers
        373. 8.1.5.373  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_322 Registers
        374. 8.1.5.374  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_323 Registers
        375. 8.1.5.375  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_324 Registers
        376. 8.1.5.376  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_325 Registers
        377. 8.1.5.377  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_326 Registers
        378. 8.1.5.378  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_327 Registers
        379. 8.1.5.379  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_328 Registers
        380. 8.1.5.380  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_329 Registers
        381. 8.1.5.381  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_330 Registers
        382. 8.1.5.382  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_331 Registers
        383. 8.1.5.383  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_332 Registers
        384. 8.1.5.384  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_333 Registers
        385. 8.1.5.385  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_334 Registers
        386. 8.1.5.386  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_335 Registers
        387. 8.1.5.387  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_336 Registers
        388. 8.1.5.388  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_337 Registers
        389. 8.1.5.389  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_338 Registers
        390. 8.1.5.390  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_339 Registers
        391. 8.1.5.391  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_340 Registers
        392. 8.1.5.392  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_341 Registers
        393. 8.1.5.393  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_342 Registers
        394. 8.1.5.394  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_343 Registers
        395. 8.1.5.395  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_344 Registers
        396. 8.1.5.396  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_345 Registers
        397. 8.1.5.397  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_346 Registers
        398. 8.1.5.398  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_347 Registers
        399. 8.1.5.399  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_348 Registers
        400. 8.1.5.400  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_349 Registers
        401. 8.1.5.401  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_350 Registers
        402. 8.1.5.402  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_351 Registers
        403. 8.1.5.403  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_352 Registers
        404. 8.1.5.404  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_353 Registers
        405. 8.1.5.405  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_354 Registers
        406. 8.1.5.406  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_355 Registers
        407. 8.1.5.407  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_356 Registers
        408. 8.1.5.408  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_357 Registers
        409. 8.1.5.409  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_358 Registers
        410. 8.1.5.410  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_359 Registers
        411. 8.1.5.411  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_360 Registers
        412. 8.1.5.412  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_361 Registers
        413. 8.1.5.413  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_362 Registers
        414. 8.1.5.414  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_363 Registers
        415. 8.1.5.415  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_364 Registers
        416. 8.1.5.416  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_365 Registers
        417. 8.1.5.417  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_366 Registers
        418. 8.1.5.418  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_367 Registers
        419. 8.1.5.419  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_368 Registers
        420. 8.1.5.420  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_369 Registers
        421. 8.1.5.421  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_370 Registers
        422. 8.1.5.422  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_371 Registers
        423. 8.1.5.423  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_372 Registers
        424. 8.1.5.424  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_373 Registers
        425. 8.1.5.425  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_374 Registers
        426. 8.1.5.426  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_375 Registers
        427. 8.1.5.427  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_376 Registers
        428. 8.1.5.428  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_377 Registers
        429. 8.1.5.429  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_378 Registers
        430. 8.1.5.430  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_379 Registers
        431. 8.1.5.431  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_380 Registers
        432. 8.1.5.432  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_381 Registers
        433. 8.1.5.433  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_382 Registers
        434. 8.1.5.434  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_383 Registers
        435. 8.1.5.435  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_384 Registers
        436. 8.1.5.436  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_385 Registers
        437. 8.1.5.437  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_386 Registers
        438. 8.1.5.438  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_387 Registers
        439. 8.1.5.439  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_388 Registers
        440. 8.1.5.440  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_389 Registers
        441. 8.1.5.441  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_390 Registers
        442. 8.1.5.442  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_391 Registers
        443. 8.1.5.443  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_392 Registers
        444. 8.1.5.444  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_393 Registers
        445. 8.1.5.445  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_394 Registers
        446. 8.1.5.446  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_395 Registers
        447. 8.1.5.447  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_396 Registers
        448. 8.1.5.448  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_397 Registers
        449. 8.1.5.449  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_398 Registers
        450. 8.1.5.450  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_399 Registers
        451. 8.1.5.451  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_400 Registers
        452. 8.1.5.452  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_401 Registers
        453. 8.1.5.453  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_402 Registers
        454. 8.1.5.454  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_403 Registers
        455. 8.1.5.455  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_404 Registers
        456. 8.1.5.456  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_405 Registers
        457. 8.1.5.457  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_406 Registers
        458. 8.1.5.458  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_407 Registers
        459. 8.1.5.459  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_408 Registers
        460. 8.1.5.460  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_409 Registers
        461. 8.1.5.461  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_410 Registers
        462. 8.1.5.462  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_411 Registers
        463. 8.1.5.463  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_412 Registers
        464. 8.1.5.464  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_413 Registers
        465. 8.1.5.465  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_414 Registers
        466. 8.1.5.466  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_415 Registers
        467. 8.1.5.467  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_416 Registers
        468. 8.1.5.468  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_417 Registers
        469. 8.1.5.469  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_418 Registers
        470. 8.1.5.470  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_419 Registers
        471. 8.1.5.471  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_420 Registers
        472. 8.1.5.472  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_421 Registers
        473. 8.1.5.473  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_422 Registers
        474. 8.1.5.474  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_0 Registers
        475. 8.1.5.475  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_1 Registers
        476. 8.1.5.476  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_2 Registers
        477. 8.1.5.477  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_3 Registers
        478. 8.1.5.478  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_4 Registers
        479. 8.1.5.479  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_5 Registers
        480. 8.1.5.480  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_6 Registers
        481. 8.1.5.481  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_7 Registers
        482. 8.1.5.482  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_8 Registers
        483. 8.1.5.483  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_9 Registers
        484. 8.1.5.484  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_10 Registers
        485. 8.1.5.485  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_11 Registers
        486. 8.1.5.486  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_12 Registers
        487. 8.1.5.487  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_13 Registers
        488. 8.1.5.488  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_14 Registers
        489. 8.1.5.489  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_15 Registers
        490. 8.1.5.490  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_16 Registers
        491. 8.1.5.491  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_17 Registers
        492. 8.1.5.492  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_18 Registers
        493. 8.1.5.493  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_19 Registers
        494. 8.1.5.494  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_20 Registers
        495. 8.1.5.495  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_21 Registers
        496. 8.1.5.496  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_22 Registers
        497. 8.1.5.497  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_23 Registers
        498. 8.1.5.498  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_24 Registers
        499. 8.1.5.499  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_25 Registers
        500. 8.1.5.500  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_26 Registers
        501. 8.1.5.501  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_27 Registers
        502. 8.1.5.502  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_28 Registers
        503. 8.1.5.503  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_29 Registers
        504. 8.1.5.504  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_30 Registers
        505. 8.1.5.505  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_31 Registers
        506. 8.1.5.506  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_32 Registers
        507. 8.1.5.507  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_33 Registers
        508. 8.1.5.508  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_34 Registers
        509. 8.1.5.509  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_35 Registers
        510. 8.1.5.510  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_36 Registers
        511. 8.1.5.511  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_37 Registers
        512. 8.1.5.512  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_38 Registers
        513. 8.1.5.513  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_39 Registers
        514. 8.1.5.514  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_40 Registers
        515. 8.1.5.515  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_41 Registers
        516. 8.1.5.516  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_42 Registers
        517. 8.1.5.517  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_43 Registers
        518. 8.1.5.518  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_44 Registers
        519. 8.1.5.519  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_45 Registers
        520. 8.1.5.520  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_46 Registers
        521. 8.1.5.521  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_47 Registers
        522. 8.1.5.522  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_48 Registers
        523. 8.1.5.523  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_49 Registers
        524. 8.1.5.524  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_50 Registers
        525. 8.1.5.525  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_51 Registers
        526. 8.1.5.526  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_52 Registers
        527. 8.1.5.527  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_53 Registers
        528. 8.1.5.528  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_54 Registers
        529. 8.1.5.529  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_55 Registers
        530. 8.1.5.530  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_56 Registers
        531. 8.1.5.531  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_57 Registers
        532. 8.1.5.532  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_58 Registers
        533. 8.1.5.533  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_59 Registers
        534. 8.1.5.534  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_60 Registers
        535. 8.1.5.535  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_61 Registers
        536. 8.1.5.536  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_62 Registers
        537. 8.1.5.537  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_63 Registers
        538. 8.1.5.538  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_64 Registers
        539. 8.1.5.539  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_65 Registers
        540. 8.1.5.540  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_66 Registers
        541. 8.1.5.541  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_67 Registers
        542. 8.1.5.542  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_68 Registers
        543. 8.1.5.543  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_69 Registers
        544. 8.1.5.544  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_70 Registers
        545. 8.1.5.545  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_71 Registers
        546. 8.1.5.546  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_72 Registers
        547. 8.1.5.547  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_73 Registers
        548. 8.1.5.548  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_74 Registers
        549. 8.1.5.549  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_75 Registers
        550. 8.1.5.550  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_76 Registers
        551. 8.1.5.551  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_77 Registers
        552. 8.1.5.552  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_78 Registers
        553. 8.1.5.553  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_79 Registers
        554. 8.1.5.554  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_80 Registers
        555. 8.1.5.555  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_81 Registers
        556. 8.1.5.556  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_82 Registers
        557. 8.1.5.557  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_83 Registers
        558. 8.1.5.558  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_84 Registers
        559. 8.1.5.559  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_85 Registers
        560. 8.1.5.560  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_86 Registers
        561. 8.1.5.561  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_87 Registers
        562. 8.1.5.562  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_88 Registers
        563. 8.1.5.563  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_89 Registers
        564. 8.1.5.564  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_90 Registers
        565. 8.1.5.565  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_91 Registers
        566. 8.1.5.566  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_92 Registers
        567. 8.1.5.567  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_93 Registers
        568. 8.1.5.568  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_94 Registers
        569. 8.1.5.569  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_95 Registers
        570. 8.1.5.570  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_96 Registers
        571. 8.1.5.571  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_97 Registers
        572. 8.1.5.572  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_98 Registers
        573. 8.1.5.573  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_99 Registers
        574. 8.1.5.574  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_100 Registers
        575. 8.1.5.575  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_101 Registers
        576. 8.1.5.576  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_102 Registers
        577. 8.1.5.577  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_103 Registers
        578. 8.1.5.578  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_104 Registers
        579. 8.1.5.579  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_105 Registers
        580. 8.1.5.580  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_106 Registers
        581. 8.1.5.581  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_107 Registers
        582. 8.1.5.582  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_108 Registers
        583. 8.1.5.583  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_109 Registers
        584. 8.1.5.584  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_110 Registers
        585. 8.1.5.585  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_111 Registers
        586. 8.1.5.586  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_112 Registers
        587. 8.1.5.587  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_113 Registers
        588. 8.1.5.588  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_114 Registers
        589. 8.1.5.589  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_115 Registers
        590. 8.1.5.590  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_116 Registers
        591. 8.1.5.591  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_117 Registers
        592. 8.1.5.592  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_118 Registers
        593. 8.1.5.593  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_119 Registers
        594. 8.1.5.594  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_120 Registers
        595. 8.1.5.595  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_121 Registers
        596. 8.1.5.596  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_122 Registers
        597. 8.1.5.597  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_123 Registers
        598. 8.1.5.598  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_124 Registers
        599. 8.1.5.599  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_125 Registers
        600. 8.1.5.600  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_126 Registers
        601. 8.1.5.601  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_127 Registers
        602. 8.1.5.602  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_128 Registers
        603. 8.1.5.603  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_129 Registers
        604. 8.1.5.604  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_130 Registers
        605. 8.1.5.605  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_131 Registers
        606. 8.1.5.606  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_132 Registers
        607. 8.1.5.607  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_133 Registers
        608. 8.1.5.608  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_134 Registers
        609. 8.1.5.609  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_135 Registers
        610. 8.1.5.610  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_136 Registers
        611. 8.1.5.611  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_137 Registers
        612. 8.1.5.612  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_138 Registers
        613. 8.1.5.613  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_139 Registers
        614. 8.1.5.614  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_140 Registers
        615. 8.1.5.615  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_141 Registers
        616. 8.1.5.616  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_142 Registers
        617. 8.1.5.617  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_143 Registers
        618. 8.1.5.618  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_144 Registers
        619. 8.1.5.619  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_145 Registers
        620. 8.1.5.620  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_146 Registers
        621. 8.1.5.621  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_147 Registers
        622. 8.1.5.622  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_148 Registers
        623. 8.1.5.623  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_149 Registers
        624. 8.1.5.624  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_150 Registers
        625. 8.1.5.625  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_151 Registers
        626. 8.1.5.626  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_152 Registers
        627. 8.1.5.627  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_153 Registers
        628. 8.1.5.628  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_154 Registers
        629. 8.1.5.629  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_155 Registers
        630. 8.1.5.630  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_156 Registers
        631. 8.1.5.631  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_157 Registers
        632. 8.1.5.632  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_158 Registers
        633. 8.1.5.633  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_159 Registers
        634. 8.1.5.634  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_160 Registers
        635. 8.1.5.635  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_161 Registers
        636. 8.1.5.636  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_162 Registers
        637. 8.1.5.637  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_163 Registers
        638. 8.1.5.638  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_164 Registers
        639. 8.1.5.639  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_165 Registers
        640. 8.1.5.640  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_166 Registers
        641. 8.1.5.641  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_167 Registers
        642. 8.1.5.642  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_168 Registers
        643. 8.1.5.643  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_169 Registers
        644. 8.1.5.644  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_170 Registers
        645. 8.1.5.645  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_171 Registers
        646. 8.1.5.646  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_172 Registers
        647. 8.1.5.647  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_173 Registers
        648. 8.1.5.648  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_174 Registers
        649. 8.1.5.649  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_175 Registers
        650. 8.1.5.650  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_176 Registers
        651. 8.1.5.651  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_177 Registers
        652. 8.1.5.652  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_178 Registers
        653. 8.1.5.653  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_179 Registers
        654. 8.1.5.654  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_180 Registers
        655. 8.1.5.655  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_181 Registers
        656. 8.1.5.656  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_182 Registers
        657. 8.1.5.657  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_183 Registers
        658. 8.1.5.658  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_184 Registers
        659. 8.1.5.659  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_185 Registers
        660. 8.1.5.660  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_186 Registers
        661. 8.1.5.661  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_187 Registers
        662. 8.1.5.662  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_188 Registers
        663. 8.1.5.663  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_189 Registers
        664. 8.1.5.664  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_190 Registers
        665. 8.1.5.665  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_191 Registers
        666. 8.1.5.666  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_192 Registers
        667. 8.1.5.667  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_193 Registers
        668. 8.1.5.668  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_194 Registers
        669. 8.1.5.669  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_195 Registers
        670. 8.1.5.670  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_196 Registers
        671. 8.1.5.671  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_197 Registers
        672. 8.1.5.672  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_198 Registers
        673. 8.1.5.673  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_199 Registers
        674. 8.1.5.674  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_200 Registers
        675. 8.1.5.675  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_201 Registers
        676. 8.1.5.676  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_202 Registers
        677. 8.1.5.677  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_203 Registers
        678. 8.1.5.678  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_204 Registers
        679. 8.1.5.679  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_205 Registers
        680. 8.1.5.680  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_206 Registers
        681. 8.1.5.681  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_207 Registers
        682. 8.1.5.682  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_208 Registers
        683. 8.1.5.683  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_209 Registers
        684. 8.1.5.684  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_210 Registers
        685. 8.1.5.685  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_211 Registers
        686. 8.1.5.686  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_212 Registers
        687. 8.1.5.687  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_213 Registers
        688. 8.1.5.688  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_214 Registers
        689. 8.1.5.689  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_215 Registers
        690. 8.1.5.690  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_216 Registers
        691. 8.1.5.691  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_217 Registers
        692. 8.1.5.692  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_218 Registers
        693. 8.1.5.693  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_219 Registers
        694. 8.1.5.694  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_220 Registers
        695. 8.1.5.695  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_221 Registers
        696. 8.1.5.696  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_222 Registers
        697. 8.1.5.697  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_223 Registers
        698. 8.1.5.698  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_224 Registers
        699. 8.1.5.699  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_225 Registers
        700. 8.1.5.700  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_226 Registers
        701. 8.1.5.701  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_227 Registers
        702. 8.1.5.702  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_228 Registers
        703. 8.1.5.703  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_229 Registers
        704. 8.1.5.704  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_230 Registers
        705. 8.1.5.705  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_231 Registers
        706. 8.1.5.706  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_232 Registers
        707. 8.1.5.707  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_233 Registers
        708. 8.1.5.708  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_234 Registers
        709. 8.1.5.709  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_235 Registers
        710. 8.1.5.710  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_236 Registers
        711. 8.1.5.711  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_237 Registers
        712. 8.1.5.712  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_238 Registers
        713. 8.1.5.713  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_239 Registers
        714. 8.1.5.714  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_240 Registers
        715. 8.1.5.715  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_241 Registers
        716. 8.1.5.716  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_242 Registers
        717. 8.1.5.717  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_243 Registers
        718. 8.1.5.718  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_244 Registers
        719. 8.1.5.719  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_245 Registers
        720. 8.1.5.720  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_246 Registers
        721. 8.1.5.721  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_247 Registers
        722. 8.1.5.722  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_248 Registers
        723. 8.1.5.723  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_249 Registers
        724. 8.1.5.724  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_250 Registers
        725. 8.1.5.725  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_251 Registers
        726. 8.1.5.726  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_252 Registers
        727. 8.1.5.727  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_253 Registers
        728. 8.1.5.728  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_254 Registers
        729. 8.1.5.729  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_255 Registers
        730. 8.1.5.730  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_256 Registers
        731. 8.1.5.731  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_257 Registers
        732. 8.1.5.732  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_258 Registers
        733. 8.1.5.733  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_259 Registers
        734. 8.1.5.734  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_260 Registers
        735. 8.1.5.735  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_261 Registers
        736. 8.1.5.736  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_262 Registers
        737. 8.1.5.737  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_263 Registers
        738. 8.1.5.738  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_264 Registers
        739. 8.1.5.739  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_265 Registers
        740. 8.1.5.740  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_266 Registers
        741. 8.1.5.741  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_267 Registers
        742. 8.1.5.742  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_268 Registers
        743. 8.1.5.743  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_269 Registers
        744. 8.1.5.744  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_270 Registers
        745. 8.1.5.745  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_271 Registers
        746. 8.1.5.746  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_272 Registers
        747. 8.1.5.747  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_273 Registers
        748. 8.1.5.748  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_274 Registers
        749. 8.1.5.749  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_275 Registers
        750. 8.1.5.750  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_276 Registers
        751. 8.1.5.751  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_277 Registers
        752. 8.1.5.752  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_278 Registers
        753. 8.1.5.753  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_279 Registers
        754. 8.1.5.754  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_280 Registers
        755. 8.1.5.755  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_281 Registers
        756. 8.1.5.756  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_282 Registers
        757. 8.1.5.757  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_283 Registers
        758. 8.1.5.758  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_284 Registers
        759. 8.1.5.759  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_285 Registers
        760. 8.1.5.760  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_286 Registers
        761. 8.1.5.761  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_287 Registers
        762. 8.1.5.762  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_288 Registers
        763. 8.1.5.763  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_289 Registers
        764. 8.1.5.764  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_290 Registers
        765. 8.1.5.765  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_291 Registers
        766. 8.1.5.766  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_292 Registers
        767. 8.1.5.767  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_293 Registers
        768. 8.1.5.768  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_294 Registers
        769. 8.1.5.769  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_295 Registers
        770. 8.1.5.770  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_296 Registers
        771. 8.1.5.771  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_297 Registers
        772. 8.1.5.772  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_298 Registers
        773. 8.1.5.773  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_299 Registers
        774. 8.1.5.774  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_300 Registers
        775. 8.1.5.775  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_301 Registers
        776. 8.1.5.776  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_302 Registers
        777. 8.1.5.777  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_303 Registers
        778. 8.1.5.778  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_304 Registers
        779. 8.1.5.779  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_305 Registers
        780. 8.1.5.780  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_306 Registers
        781. 8.1.5.781  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_307 Registers
        782. 8.1.5.782  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_308 Registers
        783. 8.1.5.783  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_309 Registers
        784. 8.1.5.784  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_310 Registers
        785. 8.1.5.785  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_311 Registers
        786. 8.1.5.786  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_312 Registers
        787. 8.1.5.787  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_313 Registers
        788. 8.1.5.788  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_314 Registers
        789. 8.1.5.789  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_315 Registers
        790. 8.1.5.790  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_316 Registers
        791. 8.1.5.791  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_317 Registers
        792. 8.1.5.792  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_318 Registers
        793. 8.1.5.793  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_319 Registers
        794. 8.1.5.794  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_320 Registers
        795. 8.1.5.795  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_321 Registers
        796. 8.1.5.796  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_322 Registers
        797. 8.1.5.797  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_323 Registers
        798. 8.1.5.798  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_324 Registers
        799. 8.1.5.799  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_325 Registers
        800. 8.1.5.800  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_326 Registers
        801. 8.1.5.801  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_327 Registers
        802. 8.1.5.802  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_328 Registers
        803. 8.1.5.803  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_329 Registers
        804. 8.1.5.804  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_330 Registers
        805. 8.1.5.805  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_331 Registers
        806. 8.1.5.806  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_332 Registers
        807. 8.1.5.807  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_333 Registers
        808. 8.1.5.808  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_334 Registers
        809. 8.1.5.809  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_335 Registers
        810. 8.1.5.810  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_336 Registers
        811. 8.1.5.811  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_337 Registers
        812. 8.1.5.812  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_338 Registers
        813. 8.1.5.813  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_339 Registers
        814. 8.1.5.814  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_340 Registers
        815. 8.1.5.815  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_341 Registers
        816. 8.1.5.816  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_342 Registers
        817. 8.1.5.817  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_343 Registers
        818. 8.1.5.818  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PI_344 Registers
        819. 8.1.5.819  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_0 Registers
        820. 8.1.5.820  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1 Registers
        821. 8.1.5.821  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_2 Registers
        822. 8.1.5.822  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_3 Registers
        823. 8.1.5.823  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_4 Registers
        824. 8.1.5.824  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_5 Registers
        825. 8.1.5.825  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_6 Registers
        826. 8.1.5.826  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_7 Registers
        827. 8.1.5.827  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_8 Registers
        828. 8.1.5.828  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_9 Registers
        829. 8.1.5.829  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_10 Registers
        830. 8.1.5.830  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_11 Registers
        831. 8.1.5.831  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_12 Registers
        832. 8.1.5.832  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_13 Registers
        833. 8.1.5.833  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_14 Registers
        834. 8.1.5.834  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_15 Registers
        835. 8.1.5.835  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_16 Registers
        836. 8.1.5.836  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_17 Registers
        837. 8.1.5.837  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_18 Registers
        838. 8.1.5.838  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_19 Registers
        839. 8.1.5.839  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_20 Registers
        840. 8.1.5.840  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_21 Registers
        841. 8.1.5.841  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_22 Registers
        842. 8.1.5.842  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_23 Registers
        843. 8.1.5.843  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_24 Registers
        844. 8.1.5.844  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_25 Registers
        845. 8.1.5.845  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_26 Registers
        846. 8.1.5.846  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_27 Registers
        847. 8.1.5.847  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_28 Registers
        848. 8.1.5.848  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_29 Registers
        849. 8.1.5.849  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_30 Registers
        850. 8.1.5.850  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_31 Registers
        851. 8.1.5.851  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_32 Registers
        852. 8.1.5.852  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_33 Registers
        853. 8.1.5.853  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_34 Registers
        854. 8.1.5.854  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_35 Registers
        855. 8.1.5.855  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_36 Registers
        856. 8.1.5.856  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_37 Registers
        857. 8.1.5.857  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_38 Registers
        858. 8.1.5.858  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_39 Registers
        859. 8.1.5.859  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_40 Registers
        860. 8.1.5.860  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_41 Registers
        861. 8.1.5.861  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_42 Registers
        862. 8.1.5.862  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_43 Registers
        863. 8.1.5.863  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_44 Registers
        864. 8.1.5.864  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_45 Registers
        865. 8.1.5.865  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_46 Registers
        866. 8.1.5.866  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_47 Registers
        867. 8.1.5.867  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_48 Registers
        868. 8.1.5.868  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_49 Registers
        869. 8.1.5.869  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_50 Registers
        870. 8.1.5.870  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_51 Registers
        871. 8.1.5.871  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_52 Registers
        872. 8.1.5.872  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_53 Registers
        873. 8.1.5.873  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_54 Registers
        874. 8.1.5.874  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_55 Registers
        875. 8.1.5.875  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_56 Registers
        876. 8.1.5.876  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_57 Registers
        877. 8.1.5.877  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_58 Registers
        878. 8.1.5.878  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_59 Registers
        879. 8.1.5.879  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_60 Registers
        880. 8.1.5.880  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_61 Registers
        881. 8.1.5.881  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_62 Registers
        882. 8.1.5.882  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_63 Registers
        883. 8.1.5.883  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_64 Registers
        884. 8.1.5.884  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_65 Registers
        885. 8.1.5.885  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_66 Registers
        886. 8.1.5.886  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_67 Registers
        887. 8.1.5.887  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_68 Registers
        888. 8.1.5.888  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_69 Registers
        889. 8.1.5.889  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_70 Registers
        890. 8.1.5.890  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_71 Registers
        891. 8.1.5.891  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_72 Registers
        892. 8.1.5.892  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_73 Registers
        893. 8.1.5.893  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_74 Registers
        894. 8.1.5.894  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_75 Registers
        895. 8.1.5.895  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_76 Registers
        896. 8.1.5.896  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_77 Registers
        897. 8.1.5.897  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_78 Registers
        898. 8.1.5.898  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_79 Registers
        899. 8.1.5.899  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_80 Registers
        900. 8.1.5.900  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_81 Registers
        901. 8.1.5.901  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_82 Registers
        902. 8.1.5.902  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_83 Registers
        903. 8.1.5.903  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_84 Registers
        904. 8.1.5.904  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_85 Registers
        905. 8.1.5.905  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_86 Registers
        906. 8.1.5.906  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_87 Registers
        907. 8.1.5.907  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_88 Registers
        908. 8.1.5.908  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_89 Registers
        909. 8.1.5.909  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_90 Registers
        910. 8.1.5.910  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_91 Registers
        911. 8.1.5.911  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_92 Registers
        912. 8.1.5.912  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_93 Registers
        913. 8.1.5.913  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_94 Registers
        914. 8.1.5.914  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_95 Registers
        915. 8.1.5.915  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_96 Registers
        916. 8.1.5.916  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_97 Registers
        917. 8.1.5.917  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_98 Registers
        918. 8.1.5.918  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_99 Registers
        919. 8.1.5.919  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_100 Registers
        920. 8.1.5.920  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_101 Registers
        921. 8.1.5.921  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_102 Registers
        922. 8.1.5.922  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_103 Registers
        923. 8.1.5.923  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_104 Registers
        924. 8.1.5.924  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_105 Registers
        925. 8.1.5.925  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_106 Registers
        926. 8.1.5.926  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_107 Registers
        927. 8.1.5.927  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_108 Registers
        928. 8.1.5.928  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_109 Registers
        929. 8.1.5.929  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_110 Registers
        930. 8.1.5.930  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_111 Registers
        931. 8.1.5.931  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_112 Registers
        932. 8.1.5.932  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_113 Registers
        933. 8.1.5.933  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_114 Registers
        934. 8.1.5.934  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_115 Registers
        935. 8.1.5.935  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_116 Registers
        936. 8.1.5.936  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_117 Registers
        937. 8.1.5.937  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_118 Registers
        938. 8.1.5.938  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_119 Registers
        939. 8.1.5.939  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_120 Registers
        940. 8.1.5.940  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_121 Registers
        941. 8.1.5.941  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_122 Registers
        942. 8.1.5.942  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_123 Registers
        943. 8.1.5.943  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_124 Registers
        944. 8.1.5.944  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_125 Registers
        945. 8.1.5.945  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_256 Registers
        946. 8.1.5.946  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_257 Registers
        947. 8.1.5.947  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_258 Registers
        948. 8.1.5.948  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_259 Registers
        949. 8.1.5.949  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_260 Registers
        950. 8.1.5.950  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_261 Registers
        951. 8.1.5.951  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_262 Registers
        952. 8.1.5.952  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_263 Registers
        953. 8.1.5.953  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_264 Registers
        954. 8.1.5.954  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_265 Registers
        955. 8.1.5.955  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_266 Registers
        956. 8.1.5.956  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_267 Registers
        957. 8.1.5.957  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_268 Registers
        958. 8.1.5.958  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_269 Registers
        959. 8.1.5.959  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_270 Registers
        960. 8.1.5.960  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_271 Registers
        961. 8.1.5.961  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_272 Registers
        962. 8.1.5.962  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_273 Registers
        963. 8.1.5.963  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_274 Registers
        964. 8.1.5.964  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_275 Registers
        965. 8.1.5.965  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_276 Registers
        966. 8.1.5.966  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_277 Registers
        967. 8.1.5.967  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_278 Registers
        968. 8.1.5.968  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_279 Registers
        969. 8.1.5.969  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_280 Registers
        970. 8.1.5.970  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_281 Registers
        971. 8.1.5.971  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_282 Registers
        972. 8.1.5.972  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_283 Registers
        973. 8.1.5.973  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_284 Registers
        974. 8.1.5.974  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_285 Registers
        975. 8.1.5.975  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_286 Registers
        976. 8.1.5.976  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_287 Registers
        977. 8.1.5.977  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_288 Registers
        978. 8.1.5.978  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_289 Registers
        979. 8.1.5.979  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_290 Registers
        980. 8.1.5.980  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_291 Registers
        981. 8.1.5.981  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_292 Registers
        982. 8.1.5.982  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_293 Registers
        983. 8.1.5.983  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_294 Registers
        984. 8.1.5.984  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_295 Registers
        985. 8.1.5.985  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_296 Registers
        986. 8.1.5.986  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_297 Registers
        987. 8.1.5.987  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_298 Registers
        988. 8.1.5.988  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_299 Registers
        989. 8.1.5.989  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_300 Registers
        990. 8.1.5.990  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_301 Registers
        991. 8.1.5.991  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_302 Registers
        992. 8.1.5.992  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_303 Registers
        993. 8.1.5.993  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_304 Registers
        994. 8.1.5.994  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_305 Registers
        995. 8.1.5.995  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_306 Registers
        996. 8.1.5.996  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_307 Registers
        997. 8.1.5.997  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_308 Registers
        998. 8.1.5.998  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_309 Registers
        999. 8.1.5.999  CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_310 Registers
        1000. 8.1.5.1000 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_311 Registers
        1001. 8.1.5.1001 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_312 Registers
        1002. 8.1.5.1002 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_313 Registers
        1003. 8.1.5.1003 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_314 Registers
        1004. 8.1.5.1004 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_315 Registers
        1005. 8.1.5.1005 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_316 Registers
        1006. 8.1.5.1006 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_317 Registers
        1007. 8.1.5.1007 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_318 Registers
        1008. 8.1.5.1008 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_319 Registers
        1009. 8.1.5.1009 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_320 Registers
        1010. 8.1.5.1010 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_321 Registers
        1011. 8.1.5.1011 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_322 Registers
        1012. 8.1.5.1012 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_323 Registers
        1013. 8.1.5.1013 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_324 Registers
        1014. 8.1.5.1014 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_325 Registers
        1015. 8.1.5.1015 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_326 Registers
        1016. 8.1.5.1016 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_327 Registers
        1017. 8.1.5.1017 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_328 Registers
        1018. 8.1.5.1018 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_329 Registers
        1019. 8.1.5.1019 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_330 Registers
        1020. 8.1.5.1020 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_331 Registers
        1021. 8.1.5.1021 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_332 Registers
        1022. 8.1.5.1022 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_333 Registers
        1023. 8.1.5.1023 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_334 Registers
        1024. 8.1.5.1024 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_335 Registers
        1025. 8.1.5.1025 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_336 Registers
        1026. 8.1.5.1026 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_337 Registers
        1027. 8.1.5.1027 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_338 Registers
        1028. 8.1.5.1028 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_339 Registers
        1029. 8.1.5.1029 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_340 Registers
        1030. 8.1.5.1030 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_341 Registers
        1031. 8.1.5.1031 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_342 Registers
        1032. 8.1.5.1032 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_343 Registers
        1033. 8.1.5.1033 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_344 Registers
        1034. 8.1.5.1034 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_345 Registers
        1035. 8.1.5.1035 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_346 Registers
        1036. 8.1.5.1036 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_347 Registers
        1037. 8.1.5.1037 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_348 Registers
        1038. 8.1.5.1038 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_349 Registers
        1039. 8.1.5.1039 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_350 Registers
        1040. 8.1.5.1040 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_351 Registers
        1041. 8.1.5.1041 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_352 Registers
        1042. 8.1.5.1042 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_353 Registers
        1043. 8.1.5.1043 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_354 Registers
        1044. 8.1.5.1044 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_355 Registers
        1045. 8.1.5.1045 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_356 Registers
        1046. 8.1.5.1046 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_357 Registers
        1047. 8.1.5.1047 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_358 Registers
        1048. 8.1.5.1048 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_359 Registers
        1049. 8.1.5.1049 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_360 Registers
        1050. 8.1.5.1050 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_361 Registers
        1051. 8.1.5.1051 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_362 Registers
        1052. 8.1.5.1052 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_363 Registers
        1053. 8.1.5.1053 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_364 Registers
        1054. 8.1.5.1054 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_365 Registers
        1055. 8.1.5.1055 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_366 Registers
        1056. 8.1.5.1056 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_367 Registers
        1057. 8.1.5.1057 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_368 Registers
        1058. 8.1.5.1058 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_369 Registers
        1059. 8.1.5.1059 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_370 Registers
        1060. 8.1.5.1060 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_371 Registers
        1061. 8.1.5.1061 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_372 Registers
        1062. 8.1.5.1062 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_373 Registers
        1063. 8.1.5.1063 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_374 Registers
        1064. 8.1.5.1064 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_375 Registers
        1065. 8.1.5.1065 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_376 Registers
        1066. 8.1.5.1066 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_377 Registers
        1067. 8.1.5.1067 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_378 Registers
        1068. 8.1.5.1068 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_379 Registers
        1069. 8.1.5.1069 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_380 Registers
        1070. 8.1.5.1070 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_381 Registers
        1071. 8.1.5.1071 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_512 Registers
        1072. 8.1.5.1072 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_513 Registers
        1073. 8.1.5.1073 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_514 Registers
        1074. 8.1.5.1074 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_515 Registers
        1075. 8.1.5.1075 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_516 Registers
        1076. 8.1.5.1076 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_517 Registers
        1077. 8.1.5.1077 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_518 Registers
        1078. 8.1.5.1078 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_519 Registers
        1079. 8.1.5.1079 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_520 Registers
        1080. 8.1.5.1080 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_521 Registers
        1081. 8.1.5.1081 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_522 Registers
        1082. 8.1.5.1082 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_523 Registers
        1083. 8.1.5.1083 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_524 Registers
        1084. 8.1.5.1084 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_525 Registers
        1085. 8.1.5.1085 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_526 Registers
        1086. 8.1.5.1086 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_527 Registers
        1087. 8.1.5.1087 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_528 Registers
        1088. 8.1.5.1088 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_529 Registers
        1089. 8.1.5.1089 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_530 Registers
        1090. 8.1.5.1090 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_531 Registers
        1091. 8.1.5.1091 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_532 Registers
        1092. 8.1.5.1092 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_533 Registers
        1093. 8.1.5.1093 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_534 Registers
        1094. 8.1.5.1094 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_535 Registers
        1095. 8.1.5.1095 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_536 Registers
        1096. 8.1.5.1096 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_537 Registers
        1097. 8.1.5.1097 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_538 Registers
        1098. 8.1.5.1098 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_539 Registers
        1099. 8.1.5.1099 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_540 Registers
        1100. 8.1.5.1100 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_541 Registers
        1101. 8.1.5.1101 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_542 Registers
        1102. 8.1.5.1102 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_543 Registers
        1103. 8.1.5.1103 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_544 Registers
        1104. 8.1.5.1104 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_545 Registers
        1105. 8.1.5.1105 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_546 Registers
        1106. 8.1.5.1106 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_547 Registers
        1107. 8.1.5.1107 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_548 Registers
        1108. 8.1.5.1108 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_549 Registers
        1109. 8.1.5.1109 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_550 Registers
        1110. 8.1.5.1110 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_551 Registers
        1111. 8.1.5.1111 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_552 Registers
        1112. 8.1.5.1112 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_553 Registers
        1113. 8.1.5.1113 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_554 Registers
        1114. 8.1.5.1114 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_768 Registers
        1115. 8.1.5.1115 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_769 Registers
        1116. 8.1.5.1116 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_770 Registers
        1117. 8.1.5.1117 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_771 Registers
        1118. 8.1.5.1118 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_772 Registers
        1119. 8.1.5.1119 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_773 Registers
        1120. 8.1.5.1120 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_774 Registers
        1121. 8.1.5.1121 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_775 Registers
        1122. 8.1.5.1122 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_776 Registers
        1123. 8.1.5.1123 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_777 Registers
        1124. 8.1.5.1124 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_778 Registers
        1125. 8.1.5.1125 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_779 Registers
        1126. 8.1.5.1126 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_780 Registers
        1127. 8.1.5.1127 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_781 Registers
        1128. 8.1.5.1128 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_782 Registers
        1129. 8.1.5.1129 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_783 Registers
        1130. 8.1.5.1130 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_784 Registers
        1131. 8.1.5.1131 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_785 Registers
        1132. 8.1.5.1132 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_786 Registers
        1133. 8.1.5.1133 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_787 Registers
        1134. 8.1.5.1134 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_788 Registers
        1135. 8.1.5.1135 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_789 Registers
        1136. 8.1.5.1136 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_790 Registers
        1137. 8.1.5.1137 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_791 Registers
        1138. 8.1.5.1138 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_792 Registers
        1139. 8.1.5.1139 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_793 Registers
        1140. 8.1.5.1140 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_794 Registers
        1141. 8.1.5.1141 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_795 Registers
        1142. 8.1.5.1142 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_796 Registers
        1143. 8.1.5.1143 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_797 Registers
        1144. 8.1.5.1144 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_798 Registers
        1145. 8.1.5.1145 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_799 Registers
        1146. 8.1.5.1146 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_800 Registers
        1147. 8.1.5.1147 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_801 Registers
        1148. 8.1.5.1148 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_802 Registers
        1149. 8.1.5.1149 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_803 Registers
        1150. 8.1.5.1150 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_804 Registers
        1151. 8.1.5.1151 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_805 Registers
        1152. 8.1.5.1152 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_806 Registers
        1153. 8.1.5.1153 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_807 Registers
        1154. 8.1.5.1154 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_808 Registers
        1155. 8.1.5.1155 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_809 Registers
        1156. 8.1.5.1156 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_810 Registers
        1157. 8.1.5.1157 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1024 Registers
        1158. 8.1.5.1158 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1025 Registers
        1159. 8.1.5.1159 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1026 Registers
        1160. 8.1.5.1160 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1027 Registers
        1161. 8.1.5.1161 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1028 Registers
        1162. 8.1.5.1162 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1029 Registers
        1163. 8.1.5.1163 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1030 Registers
        1164. 8.1.5.1164 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1031 Registers
        1165. 8.1.5.1165 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1032 Registers
        1166. 8.1.5.1166 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1033 Registers
        1167. 8.1.5.1167 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1034 Registers
        1168. 8.1.5.1168 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1035 Registers
        1169. 8.1.5.1169 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1036 Registers
        1170. 8.1.5.1170 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1037 Registers
        1171. 8.1.5.1171 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1038 Registers
        1172. 8.1.5.1172 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1039 Registers
        1173. 8.1.5.1173 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1040 Registers
        1174. 8.1.5.1174 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1041 Registers
        1175. 8.1.5.1175 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1042 Registers
        1176. 8.1.5.1176 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1043 Registers
        1177. 8.1.5.1177 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1044 Registers
        1178. 8.1.5.1178 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1045 Registers
        1179. 8.1.5.1179 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1046 Registers
        1180. 8.1.5.1180 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1047 Registers
        1181. 8.1.5.1181 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1048 Registers
        1182. 8.1.5.1182 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1049 Registers
        1183. 8.1.5.1183 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1050 Registers
        1184. 8.1.5.1184 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1051 Registers
        1185. 8.1.5.1185 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1052 Registers
        1186. 8.1.5.1186 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1053 Registers
        1187. 8.1.5.1187 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1054 Registers
        1188. 8.1.5.1188 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1055 Registers
        1189. 8.1.5.1189 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1056 Registers
        1190. 8.1.5.1190 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1057 Registers
        1191. 8.1.5.1191 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1058 Registers
        1192. 8.1.5.1192 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1059 Registers
        1193. 8.1.5.1193 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1060 Registers
        1194. 8.1.5.1194 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1061 Registers
        1195. 8.1.5.1195 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1062 Registers
        1196. 8.1.5.1196 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1063 Registers
        1197. 8.1.5.1197 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1064 Registers
        1198. 8.1.5.1198 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1065 Registers
        1199. 8.1.5.1199 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1066 Registers
        1200. 8.1.5.1200 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1280 Registers
        1201. 8.1.5.1201 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1281 Registers
        1202. 8.1.5.1202 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1282 Registers
        1203. 8.1.5.1203 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1283 Registers
        1204. 8.1.5.1204 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1284 Registers
        1205. 8.1.5.1205 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1285 Registers
        1206. 8.1.5.1206 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1286 Registers
        1207. 8.1.5.1207 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1287 Registers
        1208. 8.1.5.1208 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1288 Registers
        1209. 8.1.5.1209 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1289 Registers
        1210. 8.1.5.1210 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1290 Registers
        1211. 8.1.5.1211 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1291 Registers
        1212. 8.1.5.1212 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1292 Registers
        1213. 8.1.5.1213 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1293 Registers
        1214. 8.1.5.1214 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1294 Registers
        1215. 8.1.5.1215 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1295 Registers
        1216. 8.1.5.1216 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1296 Registers
        1217. 8.1.5.1217 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1297 Registers
        1218. 8.1.5.1218 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1298 Registers
        1219. 8.1.5.1219 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1299 Registers
        1220. 8.1.5.1220 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1300 Registers
        1221. 8.1.5.1221 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1301 Registers
        1222. 8.1.5.1222 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1302 Registers
        1223. 8.1.5.1223 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1303 Registers
        1224. 8.1.5.1224 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1304 Registers
        1225. 8.1.5.1225 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1305 Registers
        1226. 8.1.5.1226 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1306 Registers
        1227. 8.1.5.1227 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1307 Registers
        1228. 8.1.5.1228 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1308 Registers
        1229. 8.1.5.1229 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1309 Registers
        1230. 8.1.5.1230 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1310 Registers
        1231. 8.1.5.1231 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1311 Registers
        1232. 8.1.5.1232 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1312 Registers
        1233. 8.1.5.1233 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1313 Registers
        1234. 8.1.5.1234 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1314 Registers
        1235. 8.1.5.1235 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1315 Registers
        1236. 8.1.5.1236 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1316 Registers
        1237. 8.1.5.1237 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1317 Registers
        1238. 8.1.5.1238 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1318 Registers
        1239. 8.1.5.1239 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1319 Registers
        1240. 8.1.5.1240 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1320 Registers
        1241. 8.1.5.1241 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1321 Registers
        1242. 8.1.5.1242 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1322 Registers
        1243. 8.1.5.1243 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1323 Registers
        1244. 8.1.5.1244 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1324 Registers
        1245. 8.1.5.1245 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1325 Registers
        1246. 8.1.5.1246 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1326 Registers
        1247. 8.1.5.1247 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1327 Registers
        1248. 8.1.5.1248 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1328 Registers
        1249. 8.1.5.1249 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1329 Registers
        1250. 8.1.5.1250 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1330 Registers
        1251. 8.1.5.1251 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1331 Registers
        1252. 8.1.5.1252 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1332 Registers
        1253. 8.1.5.1253 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1333 Registers
        1254. 8.1.5.1254 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1334 Registers
        1255. 8.1.5.1255 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1335 Registers
        1256. 8.1.5.1256 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1336 Registers
        1257. 8.1.5.1257 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1337 Registers
        1258. 8.1.5.1258 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1338 Registers
        1259. 8.1.5.1259 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1339 Registers
        1260. 8.1.5.1260 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1340 Registers
        1261. 8.1.5.1261 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1341 Registers
        1262. 8.1.5.1262 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1342 Registers
        1263. 8.1.5.1263 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1343 Registers
        1264. 8.1.5.1264 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1344 Registers
        1265. 8.1.5.1265 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1345 Registers
        1266. 8.1.5.1266 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1346 Registers
        1267. 8.1.5.1267 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1347 Registers
        1268. 8.1.5.1268 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1348 Registers
        1269. 8.1.5.1269 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1349 Registers
        1270. 8.1.5.1270 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1350 Registers
        1271. 8.1.5.1271 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1351 Registers
        1272. 8.1.5.1272 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1352 Registers
        1273. 8.1.5.1273 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1353 Registers
        1274. 8.1.5.1274 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1354 Registers
        1275. 8.1.5.1275 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1355 Registers
        1276. 8.1.5.1276 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1356 Registers
        1277. 8.1.5.1277 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1357 Registers
        1278. 8.1.5.1278 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1358 Registers
        1279. 8.1.5.1279 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1359 Registers
        1280. 8.1.5.1280 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1360 Registers
        1281. 8.1.5.1281 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1361 Registers
        1282. 8.1.5.1282 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1362 Registers
        1283. 8.1.5.1283 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1363 Registers
        1284. 8.1.5.1284 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1364 Registers
        1285. 8.1.5.1285 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1365 Registers
        1286. 8.1.5.1286 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1366 Registers
        1287. 8.1.5.1287 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1367 Registers
        1288. 8.1.5.1288 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1368 Registers
        1289. 8.1.5.1289 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1369 Registers
        1290. 8.1.5.1290 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1370 Registers
        1291. 8.1.5.1291 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1371 Registers
        1292. 8.1.5.1292 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1372 Registers
        1293. 8.1.5.1293 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1373 Registers
        1294. 8.1.5.1294 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1374 Registers
        1295. 8.1.5.1295 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1375 Registers
        1296. 8.1.5.1296 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1376 Registers
        1297. 8.1.5.1297 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1377 Registers
        1298. 8.1.5.1298 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1378 Registers
        1299. 8.1.5.1299 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1379 Registers
        1300. 8.1.5.1300 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1380 Registers
        1301. 8.1.5.1301 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1381 Registers
        1302. 8.1.5.1302 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1382 Registers
        1303. 8.1.5.1303 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1383 Registers
        1304. 8.1.5.1304 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1384 Registers
        1305. 8.1.5.1305 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1385 Registers
        1306. 8.1.5.1306 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1386 Registers
        1307. 8.1.5.1307 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1387 Registers
        1308. 8.1.5.1308 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1388 Registers
        1309. 8.1.5.1309 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1389 Registers
        1310. 8.1.5.1310 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1390 Registers
        1311. 8.1.5.1311 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1391 Registers
        1312. 8.1.5.1312 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1392 Registers
        1313. 8.1.5.1313 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1393 Registers
        1314. 8.1.5.1314 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1394 Registers
        1315. 8.1.5.1315 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1395 Registers
        1316. 8.1.5.1316 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1396 Registers
        1317. 8.1.5.1317 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1397 Registers
        1318. 8.1.5.1318 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1398 Registers
        1319. 8.1.5.1319 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1399 Registers
        1320. 8.1.5.1320 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1400 Registers
        1321. 8.1.5.1321 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1401 Registers
        1322. 8.1.5.1322 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1402 Registers
        1323. 8.1.5.1323 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1403 Registers
        1324. 8.1.5.1324 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1404 Registers
        1325. 8.1.5.1325 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_PHY_1405 Registers
        1326. 8.1.5.1326 Access Table
    2. 8.2 Region-based Address Translation (RAT) Module
      1. 8.2.1 RAT Functional Description
        1. 8.2.1.1 RAT Availability
        2. 8.2.1.2 RAT Operation
        3. 8.2.1.3 RAT Error Logging
      2. 8.2.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GICSS)
        1. 9.2.1.1 GICSS Overview
          1. 9.2.1.1.1 GICSS Features
          2. 9.2.1.1.2 GICSS Not Supported Features
        2. 9.2.1.2 GICSS Integration
        3. 9.2.1.3 GICSS Functional Description
          1. 9.2.1.3.1 GICSS Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GICSS Interrupt Types
          4. 9.2.1.3.4 GICSS Interfaces
          5. 9.2.1.3.5 GICSS Interrupt Outputs
          6. 9.2.1.3.6 GICSS ECC Support
          7. 9.2.1.3.7 GICSS AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GICSS Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GICSS0_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 MCU_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 MCU_GPIOMUX_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 MAIN Domain Interrupt Maps
        1. 9.4.1.1 GICSS0 Interrupt Map
          1. 9.4.1.1.1 GICSS0 PPI Interrupt Map
          2. 9.4.1.1.2 GICSS0 SPI Interrupt Map
        2. 9.4.1.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.1.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.1.4 R5FSS1_CORE0 Interrupt Map
        5. 9.4.1.5 R5FSS1_CORE1 Interrupt Map
        6. 9.4.1.6 PRU_ICSSG0 Interrupt Map
        7. 9.4.1.7 PRU_ICSSG1 Interrupt Map
        8. 9.4.1.8 GPIOMUX_INTRTR0 Interrupt Map
        9. 9.4.1.9 ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_M4FSS Interrupt Map
        2. 9.4.2.2 MCU_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
    5. 9.5 Time Sync and Compare Interrupt Events
      1. 9.5.1 CMPEVT_INTRTR0 Interrupt Map
      2. 9.5.2 TIMESYNC_INTRTR0 Interrupt Map
  12. 10Time Sync
    1. 10.1 Time Sync Module (CPTS)
      1. 10.1.1 CPTS Overview
        1. 10.1.1.1 CPTS Features
        2. 10.1.1.2 CPTS Not Supported Features
      2. 10.1.2 CPTS Integration
      3. 10.1.3 CPTS Functional Description
        1. 10.1.3.1  CPTS Architecture
        2. 10.1.3.2  CPTS Initialization
        3. 10.1.3.3  32-bit Time Stamp Value
        4. 10.1.3.4  64-bit Time Stamp Value
          1. 10.1.3.4.1 64-Bit Timestamp Nudge
          2. 10.1.3.4.2 64-bit Timestamp PPM
        5. 10.1.3.5  Event FIFO
        6. 10.1.3.6  Timestamp Compare Output
          1. 10.1.3.6.1 Non-Toggle Mode
          2. 10.1.3.6.2 Toggle Mode
        7. 10.1.3.7  Timestamp Sync Output
        8. 10.1.3.8  Timestamp GENF Output
          1. 10.1.3.8.1 GENFn Nudge
          2. 10.1.3.8.2 GENFn PPM
        9. 10.1.3.9  Time Sync Events
          1. 10.1.3.9.1 Time Stamp Push Event
          2. 10.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 10.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 10.1.3.9.4 Hardware Time Stamp Push Event
        10. 10.1.3.10 Timestamp Compare Event
        11. 10.1.3.11 CPTS Interrupt Handling
      4. 10.1.4 CPTS Registers
    2. 10.2 Timer Manager
      1. 10.2.1 Timer Manager Overview
        1. 10.2.1.1 Timer Manager Features
        2. 10.2.1.2 Timer Manager Not Supported Features
      2. 10.2.2 Timer Manager Integration
      3. 10.2.3 Timer Manager Functional Description
        1. 10.2.3.1 Timer Manager Function Overview
        2. 10.2.3.2 Timer Counter
          1. 10.2.3.2.1 Timer Counter Rollover
        3. 10.2.3.3 Timer Control Module (FSM)
        4. 10.2.3.4 Timer Reprogramming
          1. 10.2.3.4.1 Periodic Hardware Timers
        5. 10.2.3.5 Event FIFO
        6. 10.2.3.6 Timer Manager Unmapped Events mapping
      4. 10.2.4 Timer Manager Programming Guide
        1. 10.2.4.1 Timer Manager Low-level Programming Models
          1. 10.2.4.1.1 Surrounding Modules Global Initialization
          2. 10.2.4.1.2 Initialization Sequence
          3. 10.2.4.1.3 Real-time Operating Requirements
            1. 10.2.4.1.3.1 Timer Touch
            2. 10.2.4.1.3.2 Timer Disable
            3. 10.2.4.1.3.3 Timer Enable
          4. 10.2.4.1.4 Power Up/Power Down Sequence
      5. 10.2.5 Timer Manager Registers
        1. 10.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 10.2.5.2 TIMERMGR_CFG_TIMERS Registers
    3. 10.3 Time Sync and Compare Events
      1. 10.3.1 Time Sync Architecture
        1. 10.3.1.1 Time Sync Architecture Overview
      2. 10.3.2 Time Sync Routers
        1. 10.3.2.1 Time Sync Routers Overview
        2. 10.3.2.2 Time Sync Routers Integration
          1. 10.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 10.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 10.3.2.3 Time Sync Routers Registers
          1. 10.3.2.3.1 TIMESYNC_EVENT_INTROUTER Registers
            1. 10.3.2.3.1.1 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.1.2 INTR_ROUTER_CFG_TIMESYNC_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.1.3 Access Table
          2. 10.3.2.3.2 CMP_EVENT_INTROUTER Registers
            1. 10.3.2.3.2.1 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_PID Registers
            2. 10.3.2.3.2.2 INTR_ROUTER_CFG_CMP_EVENT_INTROUTER_MUXCNTL Registers
            3. 10.3.2.3.2.3 Access Table
      3. 10.3.3 Time Sync Event Sources
  13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
      1. 11.1.1 Overview
        1. 11.1.1.1 Ring Accelerator (RINGACC)
        2. 11.1.1.2 Secure Proxy (SEC_PROXY)
        3. 11.1.1.3 Interrupt Aggregator (INTAGGR)
        4. 11.1.1.4 Packet DMA (PKTDMA)
          1. 11.1.1.4.1 PKTDMA Submodule Descriptions
            1. 11.1.1.4.1.1  Bus Interface Unit
            2. 11.1.1.4.1.2  Config CR
            3. 11.1.1.4.1.3  Configuration Registers
              1. 11.1.1.4.1.3.1 RX State Mapping
              2. 11.1.1.4.1.3.2 TX State Mapping
            4. 11.1.1.4.1.4  Tx Packet DMA Unit
            5. 11.1.1.4.1.5  Tx Packet Coherency Unit
            6. 11.1.1.4.1.6  Tx Per Channel Buffers
            7. 11.1.1.4.1.7  Rx Per Channel Buffers
            8. 11.1.1.4.1.8  Rx Packet DMA Unit
            9. 11.1.1.4.1.9  Rx Packet Coherency Unit
            10. 11.1.1.4.1.10 Event Handler
          2. 11.1.1.4.2 Channel Classes
        5. 11.1.1.5 Block Copy DMA (BCDMA)
          1. 11.1.1.5.1 BCDMA Submodule Descriptions
            1. 11.1.1.5.1.1  Bus Interface Unit
            2. 11.1.1.5.1.2  Config CR
            3. 11.1.1.5.1.3  Configuration Registers
              1. 11.1.1.5.1.3.1 BCDMA Mapping Table
            4. 11.1.1.5.1.4  Read Unit(s)
            5. 11.1.1.5.1.5  TR Coherency Unit
            6. 11.1.1.5.1.6  Per-Copy-Channel Buffers
            7. 11.1.1.5.1.7  Tx Per-Split-Channel Buffers
            8. 11.1.1.5.1.8  Rx Per-Split-Channel Buffers
            9. 11.1.1.5.1.9  Write Unit(s)
            10. 11.1.1.5.1.10 Event Coherency Unit
            11. 11.1.1.5.1.11 Event Handler
          2. 11.1.1.5.2 Channel Classes
      2. 11.1.2 Definition of Terms
      3. 11.1.3 DMSS Hardware/Software Interface
        1. 11.1.3.1 Data Buffers
        2. 11.1.3.2 Descriptors
          1. 11.1.3.2.1 Host Packet Descriptor
          2. 11.1.3.2.2 Host Buffer Descriptor
          3. 11.1.3.2.3 Transfer Request Descriptor
        3. 11.1.3.3 Transfer Request Record
          1. 11.1.3.3.1 Overview
          2. 11.1.3.3.2 Addressing Algorithm
            1. 11.1.3.3.2.1 Linear Addressing (Forward)
          3. 11.1.3.3.3 Transfer Request Formats
          4. 11.1.3.3.4 Flags Field Definition
            1. 11.1.3.3.4.1 Type: TR Type Field
            2. 11.1.3.3.4.2 EVENT_SIZE: Event Generation Definition
            3. 11.1.3.3.4.3 TRIGGER_INFO: TR Triggers
            4. 11.1.3.3.4.4 TRIGGERX_TYPE: Trigger Type
            5. 11.1.3.3.4.5 TRIGGERX: Trigger Selection
            6. 11.1.3.3.4.6 Configuration Specific Flags Definition
          5. 11.1.3.3.5 TR Address and Size Attributes
            1. 11.1.3.3.5.1  ICNT0
            2. 11.1.3.3.5.2  ICNT1
            3. 11.1.3.3.5.3  ADDR
            4. 11.1.3.3.5.4  DIM1
            5. 11.1.3.3.5.5  ICNT2
            6. 11.1.3.3.5.6  ICNT3
            7. 11.1.3.3.5.7  DIM2
            8. 11.1.3.3.5.8  DIM3
            9. 11.1.3.3.5.9  DDIM1
            10. 11.1.3.3.5.10 DADDR
            11. 11.1.3.3.5.11 DDIM2
            12. 11.1.3.3.5.12 DDIM3
            13. 11.1.3.3.5.13 DICNT0
            14. 11.1.3.3.5.14 DICNT1
            15. 11.1.3.3.5.15 DICNT2
            16. 11.1.3.3.5.16 DICNT3
        4. 11.1.3.4 Transfer Response Record
          1. 11.1.3.4.1 STATUS Field Definition
            1. 11.1.3.4.1.1 STATUS_TYPE Definitions
              1. 11.1.3.4.1.1.1 Transfer Error
              2. 11.1.3.4.1.1.2 Aborted Error
              3. 11.1.3.4.1.1.3 Submission Error
              4. 11.1.3.4.1.1.4 Unsupported Feature
              5. 11.1.3.4.1.1.5 Transfer Exception
              6. 11.1.3.4.1.1.6 Teardown Flush
        5. 11.1.3.5 Channels
        6. 11.1.3.6 Flows
        7. 11.1.3.7 Queues
          1. 11.1.3.7.1 Queue Types
            1. 11.1.3.7.1.1 Transmit Queues
            2. 11.1.3.7.1.2 Transmit Completion Queues
            3. 11.1.3.7.1.3 Free Descriptor / Buffer Queues
            4. 11.1.3.7.1.4 Receive Queues
            5. 11.1.3.7.1.5 Ring Based Queues Implementation
      4. 11.1.4 Operational Description
        1. 11.1.4.1  Resource Allocation
        2. 11.1.4.2  PKTDMA/BCDMA - Ring Operation
          1. 11.1.4.2.1 Queue Initialization
          2. 11.1.4.2.2 Queueing Entries
          3. 11.1.4.2.3 De-queueing Entries
        3. 11.1.4.3  PKTDMA/BCDMA - Output Event Generation
        4. 11.1.4.4  PKTDMA - Transmit Channel Setup
        5. 11.1.4.5  PKTDMA - Transmit Channel Pause
        6. 11.1.4.6  PKTDMA - Transmit Channel Teardown
        7. 11.1.4.7  PKTDMA - Transmit Operation
        8. 11.1.4.8  PKTDMA - Receive Free Descriptor / Buffer Queue Setup
        9. 11.1.4.9  PKTDMA - Receive Channel Setup
        10. 11.1.4.10 PKTDMA - Receive Channel Teardown
        11. 11.1.4.11 PKTDMA - Receive Channel Pause
        12. 11.1.4.12 PKTDMA - Receive Operation
        13. 11.1.4.13 BCDMA - Block Copy Channel Setup
        14. 11.1.4.14 BCDMA - Block Copy Channel Pause
        15. 11.1.4.15 BCDMA - Block Copy Channel Teardown
        16. 11.1.4.16 BCDMA - Block Copy Operation (TR Packet)
        17. 11.1.4.17 BCDMA - Block Copy Error/Exception Handling
          1. 11.1.4.17.1 Null Icnt0 Error
          2. 11.1.4.17.2 Unsupported TR Type
          3. 11.1.4.17.3 Bus Errors
        18. 11.1.4.18 BCDMA - Split Transmit Channel Setup
        19. 11.1.4.19 BCDMA - Split Transmit Operation Pause
        20. 11.1.4.20 BCDMA - Split Transmit Channel Teardown
        21. 11.1.4.21 BCDMA - Split Transmit Operation (TR Packet)
        22. 11.1.4.22 BCDMA - Split Transmit Error / Exception Handling
          1. 11.1.4.22.1 Null Icnt0 Error
          2. 11.1.4.22.2 Unsupported TR Type
          3. 11.1.4.22.3 Bus Errors
        23. 11.1.4.23 BCDMA - Split Receive Channel Setup
        24. 11.1.4.24 BCDMA - Split Receive Channel Pause
        25. 11.1.4.25 BCDMA - Split Receive Channel Teardown
        26. 11.1.4.26 BCDMA - Split Receive Operation (TR Packet)
        27. 11.1.4.27 BCDMA - Split Receive Error / Exception Handling
          1. 11.1.4.27.1 PKTDMA Exception Conditions
            1. 11.1.4.27.1.1 Descriptor Starvation
            2. 11.1.4.27.1.2 Protocol Errors
            3. 11.1.4.27.1.3 Dropped Packets
            4. 11.1.4.27.1.4 Long Packet
          2. 11.1.4.27.2 BCDMA Exception Conditions
            1. 11.1.4.27.2.1 Reception of EOL Delimiter
            2. 11.1.4.27.2.2 EOP Asserted Prematurely (Short Packet)
            3. 11.1.4.27.2.3 EOP Asserted Late (Long Packets)
            4. 11.1.4.27.2.4 Descriptor Starvation
    2. 11.2 Data Movement Subsystem (DMSS)
      1. 11.2.1 Data Movement Subsystem (DMSS)
        1. 11.2.1.1 DMSS Overview
        2. 11.2.1.2 DMSS Integration
          1. 11.2.1.2.1 DMSS Integration Attributes
          2. 11.2.1.2.2 DMSS Clocks
          3. 11.2.1.2.3 DMSS Resets
          4. 11.2.1.2.4 DMSS Interrupt Requests
          5. 11.2.1.2.5 DMSS L2G Interrupt Inputs
          6. 11.2.1.2.6 DMSS DMA Events
          7. 11.2.1.2.7 Global Event Map
          8. 11.2.1.2.8 PSI-L System Thread Map
        3. 11.2.1.3 DMSS Functional Description
        4. 11.2.1.4 DMSS Interrupt Configuration
          1. 11.2.1.4.1 DMSS Event and Interrupt Flow
            1. 11.2.1.4.1.1 DMSS Interrupt Description
        5. 11.2.1.5 DMSS Top-Level Registers
          1. 11.2.1.5.1 DMASS_PKTDMA_0 Registers
          2. 11.2.1.5.2 DMASS_BCDMA_0 Registers
      2. 11.2.2 Ring Accelerator (RINGACC)
        1. 11.2.2.1 RINGACC Overview
          1. 11.2.2.1.1 RINGACC Features
          2. 11.2.2.1.2 RINGACC Not Supported Features
          3. 11.2.2.1.3 RINGACC Parameters
        2. 11.2.2.2 RINGACC Integration
          1. 11.2.2.2.1 RINGACC Integration Attributes
          2. 11.2.2.2.2 RINGACC Clocks
          3. 11.2.2.2.3 RINGACC Resets
          4. 11.2.2.2.4 RINGACC Interrupt Requests
          5. 11.2.2.2.5 RINGACC Outbound Events
        3. 11.2.2.3 RINGACC Functional Description
          1. 11.2.2.3.1 Block Diagram
            1. 11.2.2.3.1.1  Configuration Registers
            2. 11.2.2.3.1.2  Source Command FIFO
            3. 11.2.2.3.1.3  Source Write Data FIFO
            4. 11.2.2.3.1.4  Source Read Data FIFO
            5. 11.2.2.3.1.5  Source Write Status FIFO
            6. 11.2.2.3.1.6  Main State Machine
            7. 11.2.2.3.1.7  Destination Command FIFO
            8. 11.2.2.3.1.8  Destination Write Data FIFO
            9. 11.2.2.3.1.9  Destination Read Data FIFO
            10. 11.2.2.3.1.10 Destination Write Status FIFO
          2. 11.2.2.3.2 RINGACC Functional Operation
            1. 11.2.2.3.2.1 Queue Modes
              1. 11.2.2.3.2.1.1 Ring Mode
              2. 11.2.2.3.2.1.2 Messaging Mode
              3. 11.2.2.3.2.1.3 Credentials Mode
              4. 11.2.2.3.2.1.4 Peek Support
              5. 11.2.2.3.2.1.5 Index Register Operation
            2. 11.2.2.3.2.2 VBUSM Target Ring Operations
            3. 11.2.2.3.2.3 VBUSM Initiator Interface Command ID Selection
            4. 11.2.2.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 11.2.2.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 11.2.2.3.2.6 Host Doorbell Access
            7. 11.2.2.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 11.2.2.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 11.2.2.3.2.9 Mismatched Element Size Handling
          3. 11.2.2.3.3 Events
          4. 11.2.2.3.4 Bus Error Handling
          5. 11.2.2.3.5 Monitors
            1. 11.2.2.3.5.1 Threshold Monitor
            2. 11.2.2.3.5.2 Watermark Monitor
            3. 11.2.2.3.5.3 Starvation Monitor
            4. 11.2.2.3.5.4 Statistics Monitor
            5. 11.2.2.3.5.5 Overflow
            6. 11.2.2.3.5.6 Ring Update Port
            7. 11.2.2.3.5.7 Tracing
        4. 11.2.2.4 RINGACC Registers
          1. 11.2.2.4.1 DMASS_RINGACC_0 Registers
      3. 11.2.3 Secure Proxy (SEC_PROXY)
        1. 11.2.3.1 Secure Proxy Overview
          1. 11.2.3.1.1 Secure Proxy Features
          2. 11.2.3.1.2 Secure Proxy Parameters
          3. 11.2.3.1.3 Secure Proxy Not Supported Features
        2. 11.2.3.2 Secure Proxy Integration
          1. 11.2.3.2.1 Secure Proxy Integration Attributes
          2. 11.2.3.2.2 Secure Proxy Clocks
          3. 11.2.3.2.3 Secure Proxy Resets
          4. 11.2.3.2.4 Secure Proxy Interrupt Requests
          5. 11.2.3.2.5 Secure Proxy DMA Events
        3. 11.2.3.3 Secure Proxy Functional Description
          1. 11.2.3.3.1  Targets
          2. 11.2.3.3.2  Buffers
          3. 11.2.3.3.3  Proxy Thread Sizes
          4. 11.2.3.3.4  Proxy Thread Interleaving
          5. 11.2.3.3.5  Proxy States
          6. 11.2.3.3.6  Proxy Host Access
          7. 11.2.3.3.7  Permission Inheritance
          8. 11.2.3.3.8  Resource Association
          9. 11.2.3.3.9  Direction
          10. 11.2.3.3.10 Threshold Events
          11. 11.2.3.3.11 Error Events
          12. 11.2.3.3.12 Bus Error and Credits
          13. 11.2.3.3.13 Debug
        4. 11.2.3.4 Secure Proxy Registers
          1. 11.2.3.4.1 DMASS_SEC_PROXY_0 Registers
      4. 11.2.4 Interrupt Aggregator (INTAGGR)
        1. 11.2.4.1 INTAGGR Overview
          1. 11.2.4.1.1 INTAGGR Features
          2. 11.2.4.1.2 INTAGGR Parameters
        2. 11.2.4.2 INTAGGR Integration
          1. 11.2.4.2.1 INTAGGR Integration Attributes
          2. 11.2.4.2.2 INTAGGR Clocks
          3. 11.2.4.2.3 INTAGGR Resets
          4. 11.2.4.2.4 INTAGGR Interrupt Requests
          5. 11.2.4.2.5 INTAGGR DMA Events
        3. 11.2.4.3 INTAGGR Functional Description
          1. 11.2.4.3.1 Submodule Descriptions
          2. 11.2.4.3.2 General Functionality
        4. 11.2.4.4 INTAGGR Registers
          1. 11.2.4.4.1 DMASS_INTAGGR_0 Registers
      5. 11.2.5 Packet Streaming Interface Link (PSI-L)
        1. 11.2.5.1 PSI-L Overview
        2. 11.2.5.2 PSI-L Functional Description
          1. 11.2.5.2.1 PSI-L Introduction
          2. 11.2.5.2.2 PSI-L Operation
        3. 11.2.5.3 PSI-L Configuration Registers
          1. 11.2.5.3.1 DMASS_PSILCFG_0 Registers
          2. 11.2.5.3.2 DMASS_PSILSS_0 Registers
    3. 11.3 Peripheral DMA (PDMA)
      1. 11.3.1 PDMA Controller
        1. 11.3.1.1 PDMA Overview
          1. 11.3.1.1.1 PDMA Features
            1. 11.3.1.1.1.1 PDMA0 Features
            2. 11.3.1.1.1.2 PDMA1 Features
        2. 11.3.1.2 PDMA Integration
          1. 11.3.1.2.1 PDMA Integration in MAIN Domain
        3. 11.3.1.3 PDMA Functional Description
          1. 11.3.1.3.1 PDMA Functional Blocks
            1. 11.3.1.3.1.1 Scheduler
            2. 11.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 11.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 11.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 11.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 11.3.1.3.2 PDMA General Functionality
            1. 11.3.1.3.2.1 Operational States
            2. 11.3.1.3.2.2 Clock Stop
            3. 11.3.1.3.2.3 Emulation Control
          3. 11.3.1.3.3 PDMA Events and Flow Control
            1. 11.3.1.3.3.1 Channel Types
              1. 11.3.1.3.3.1.1 X-Y FIFO Mode
              2. 11.3.1.3.3.1.2 MCAN Mode
            2. 11.3.1.3.3.2 Channel Triggering
            3. 11.3.1.3.3.3 Completion Events
          4. 11.3.1.3.4 PDMA Transmit Operation
            1. 11.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 11.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 11.3.1.3.4.3 Destination Channel Initialization
              1. 11.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 11.3.1.3.4.3.2 Static Transfer Request Setup
              3. 11.3.1.3.4.3.3 PSI-L Destination Thread Enables
            4. 11.3.1.3.4.4 Data Transfer
              1. 11.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 11.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 11.3.1.3.4.4.2 MCAN Mode Channel
                1. 11.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 11.3.1.3.4.4.3 AASRC Mode Channel
            5. 11.3.1.3.4.5 Tx Pause
            6. 11.3.1.3.4.6 Tx Teardown
            7. 11.3.1.3.4.7 Tx Channel Reset
            8. 11.3.1.3.4.8 Tx Debug/State Registers
          5. 11.3.1.3.5 PDMA Receive Operation
            1. 11.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 11.3.1.3.5.2 Source Channel Initialization
              1. 11.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 11.3.1.3.5.2.2 Static Transfer Request Setup
              3. 11.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 11.3.1.3.5.3 Data Transfer
              1. 11.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 11.3.1.3.5.3.2 MCAN Mode Channel
                1. 11.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 11.3.1.3.5.3.3 AASRC Mode Channel
            4. 11.3.1.3.5.4 Rx Pause
            5. 11.3.1.3.5.5 Rx Teardown
            6. 11.3.1.3.5.6 Rx Channel Reset
            7. 11.3.1.3.5.7 Rx Debug/State Register
          6. 11.3.1.3.6 PDMA ECC Support
        4. 11.3.1.4 PDMA Registers
          1. 11.3.1.4.1 PDMA0 ECC Registers
          2. 11.3.1.4.2 PDMA1 ECC Registers
          3. 11.3.1.4.3 PDMA PSI-L TX Configuration Registers
          4. 11.3.1.4.4 PDMA PSI-L RX Configuration Registers
      2. 11.3.2 PDMA Sources
        1. 11.3.2.1 PDMA0 Event Map
        2. 11.3.2.2 PDMA1 Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MAIN Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in MCU Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 4200
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in MCU Domain
          2. 12.1.3.3.2 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.4.1 MCSPI Overview
          1. 12.1.4.1.1 SPI Features
          2. 12.1.4.1.2 SPI Not Supported Features
        2. 12.1.4.2 MCSPI Environment
          1. 12.1.4.2.1 Basic MCSPI Pins for Controller Mode
          2. 12.1.4.2.2 Basic MCSPI Pins for Peripheral Mode
          3. 12.1.4.2.3 MCSPI Protocol and Data Format
            1. 12.1.4.2.3.1 Transfer Format
          4. 12.1.4.2.4 MCSPI in Controller Mode
          5. 12.1.4.2.5 MCSPI in Peripheral Mode
        3. 12.1.4.3 MCSPI Integration
          1. 12.1.4.3.1 MCSPI Integration in MCU Domain
          2. 12.1.4.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.4.4 MCSPI Functional Description
          1. 12.1.4.4.1 SPI Block Diagram
          2. 12.1.4.4.2 MCSPI Reset
          3. 12.1.4.4.3 MCSPI Controller Mode
            1. 12.1.4.4.3.1 Controller Mode Features
            2. 12.1.4.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.4.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.4.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.4.4.3.5 Single-Channel Controller Mode
              1. 12.1.4.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.4.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.4.4.3.5.3 Turbo Mode
            6. 12.1.4.4.3.6 Start-Bit Mode
            7. 12.1.4.4.3.7 Chip-Select Timing Control
            8. 12.1.4.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.4.4.3.8.1 Clock Ratio Granularity
          4. 12.1.4.4.4 MCSPI Peripheral Mode
            1. 12.1.4.4.4.1 Dedicated Resources
            2. 12.1.4.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.4.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.4.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.4.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.4.4.6 MCSPI FIFO Buffer Management
            1. 12.1.4.4.6.1 Buffer Almost Full
            2. 12.1.4.4.6.2 Buffer Almost Empty
            3. 12.1.4.4.6.3 End of Transfer Management
            4. 12.1.4.4.6.4 Multiple MCSPI Word Access
            5. 12.1.4.4.6.5 First MCSPI Word Delay
          7. 12.1.4.4.7 MCSPI Interrupts
            1. 12.1.4.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.4.4.7.1.1 TXx_EMPTY
              2. 12.1.4.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.1.3 RXx_ FULL
              4. 12.1.4.4.7.1.4 End Of Word Count
            2. 12.1.4.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.4.4.7.2.1 TXx_EMPTY
              2. 12.1.4.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.2.3 RXx_FULL
              4. 12.1.4.4.7.2.4 RX0_OVERFLOW
              5. 12.1.4.4.7.2.5 End Of Word Count
            3. 12.1.4.4.7.3 Interrupt-Driven Operation
            4. 12.1.4.4.7.4 Polling
          8. 12.1.4.4.8 MCSPI DMA Requests
          9. 12.1.4.4.9 MCSPI Power Saving Management
            1. 12.1.4.4.9.1 Normal Mode
            2. 12.1.4.4.9.2 Idle Mode
              1. 12.1.4.4.9.2.1 Force-Idle Mode
        5. 12.1.4.5 MCSPI Programming Guide
          1. 12.1.4.5.1 MCSPI Global Initialization
            1. 12.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.4.5.1.2 MCSPI Global Initialization
              1. 12.1.4.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.4.5.2 MCSPI Operational Mode Configuration
            1. 12.1.4.5.2.1 MCSPI Operational Modes
              1. 12.1.4.5.2.1.1 Common Transfer Sequence
              2. 12.1.4.5.2.1.2 End of Transfer Sequences
              3. 12.1.4.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.4.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.4.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.4.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.4.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.4.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.4.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.4.5.2.1.7 Peripheral Receive-Only
              8. 12.1.4.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.4.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.4.5.2.1.8.5 Transmit-Only
                6. 12.1.4.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.4.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.4.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.4.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.4.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.4.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.4.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.4.6 MCSPI Registers
      5. 12.1.5 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.5.1 UART Overview
          1. 12.1.5.1.1 UART Features
          2. 12.1.5.1.2 IrDA Features
          3. 12.1.5.1.3 CIR Features
          4. 12.1.5.1.4 UART Not Supported Features
        2. 12.1.5.2 UART Environment
          1. 12.1.5.2.1 UART Functional Interfaces
            1. 12.1.5.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.5.2.1.2 UART Interface Description
            3. 12.1.5.2.1.3 UART Protocol and Data Format
            4. 12.1.5.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.5.2.2 RS-485 Functional Interfaces
            1. 12.1.5.2.2.1 System Using RS-485 Communication
            2. 12.1.5.2.2.2 RS-485 Interface Description
          3. 12.1.5.2.3 IrDA Functional Interfaces
            1. 12.1.5.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.5.2.3.2 IrDA Interface Description
            3. 12.1.5.2.3.3 IrDA Protocol and Data Format
              1. 12.1.5.2.3.3.1 SIR Mode
                1. 12.1.5.2.3.3.1.1 Frame Format
                2. 12.1.5.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.5.2.3.3.1.3 Abort Sequence
                4. 12.1.5.2.3.3.1.4 Pulse Shaping
                5. 12.1.5.2.3.3.1.5 Encoder
                6. 12.1.5.2.3.3.1.6 Decoder
                7. 12.1.5.2.3.3.1.7 IR Address Checking
              2. 12.1.5.2.3.3.2 SIR Free-Format Mode
              3. 12.1.5.2.3.3.3 MIR Mode
                1. 12.1.5.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.5.2.3.3.3.2 SIP Generation
              4. 12.1.5.2.3.3.4 FIR Mode
          4. 12.1.5.2.4 CIR Functional Interfaces
            1. 12.1.5.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.5.2.4.2 CIR Interface Description
            3. 12.1.5.2.4.3 CIR Protocol and Data Format
              1. 12.1.5.2.4.3.1 Carrier Modulation
              2. 12.1.5.2.4.3.2 Pulse Duty Cycle
              3. 12.1.5.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.5.3 UART Integration
          1. 12.1.5.3.1 UART Integration in MCU Domain
          2. 12.1.5.3.2 UART Integration in MAIN Domain
        4. 12.1.5.4 UART Functional Description
          1. 12.1.5.4.1 UART Block Diagram
          2. 12.1.5.4.2 UART Clock Configuration
          3. 12.1.5.4.3 UART Software Reset
            1. 12.1.5.4.3.1 Independent TX/RX
          4. 12.1.5.4.4 UART Power Management
            1. 12.1.5.4.4.1 UART Mode Power Management
              1. 12.1.5.4.4.1.1 Module Power Saving
              2. 12.1.5.4.4.1.2 System Power Saving
            2. 12.1.5.4.4.2 IrDA Mode Power Management
              1. 12.1.5.4.4.2.1 Module Power Saving
              2. 12.1.5.4.4.2.2 System Power Saving
            3. 12.1.5.4.4.3 CIR Mode Power Management
              1. 12.1.5.4.4.3.1 Module Power Saving
              2. 12.1.5.4.4.3.2 System Power Saving
            4. 12.1.5.4.4.4 Local Power Management
          5. 12.1.5.4.5 UART Interrupt Requests
            1. 12.1.5.4.5.1 UART Mode Interrupt Management
              1. 12.1.5.4.5.1.1 UART Interrupts
              2. 12.1.5.4.5.1.2 Wake-Up Interrupt
            2. 12.1.5.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.5.4.5.2.1 IrDA Interrupts
              2. 12.1.5.4.5.2.2 Wake-Up Interrupts
            3. 12.1.5.4.5.3 CIR Mode Interrupt Management
              1. 12.1.5.4.5.3.1 CIR Interrupts
              2. 12.1.5.4.5.3.2 Wake-Up Interrupts
          6. 12.1.5.4.6 UART FIFO Management
            1. 12.1.5.4.6.1 FIFO Trigger
              1. 12.1.5.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.5.4.6.1.2 Receive FIFO Trigger
            2. 12.1.5.4.6.2 FIFO Interrupt Mode
            3. 12.1.5.4.6.3 FIFO Polled Mode Operation
            4. 12.1.5.4.6.4 FIFO DMA Mode Operation
              1. 12.1.5.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.5.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.5.4.6.4.3 DMA Transmission
              4. 12.1.5.4.6.4.4 DMA Reception
          7. 12.1.5.4.7 UART Mode Selection
            1. 12.1.5.4.7.1 Register Access Modes
              1. 12.1.5.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.5.4.7.1.2 Register Access Submode
              3. 12.1.5.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.5.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.5.4.7.2.1 Registers Available for the UART Function
              2. 12.1.5.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.5.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.5.4.8 UART Protocol Formatting
            1. 12.1.5.4.8.1 UART Mode
              1. 12.1.5.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.5.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.1.3 UART Data Formatting
                1. 12.1.5.4.8.1.3.1 Frame Formatting
                2. 12.1.5.4.8.1.3.2 Hardware Flow Control
                3. 12.1.5.4.8.1.3.3 Software Flow Control
                  1. 1.5.4.8.1.3.3.1 Receive (RX)
                  2. 1.5.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.5.4.8.1.3.4 Autobauding Modes
                5. 12.1.5.4.8.1.3.5 Error Detection
                6. 12.1.5.4.8.1.3.6 Overrun During Receive
                7. 12.1.5.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.5.4.8.1.3.7.1 Time-Out Counter
                  2. 1.5.4.8.1.3.7.2 Break Condition
            2. 12.1.5.4.8.2 RS-485 Mode
              1. 12.1.5.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.5.4.8.3 IrDA Mode
              1. 12.1.5.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.5.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.3.3 IrDA Data Formatting
                1. 12.1.5.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.5.4.8.3.3.2  IrDA Reception Control
                3. 12.1.5.4.8.3.3.3  IR Address Checking
                4. 12.1.5.4.8.3.3.4  Frame Closing
                5. 12.1.5.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.5.4.8.3.3.6  Error Detection
                7. 12.1.5.4.8.3.3.7  Underrun During Transmission
                8. 12.1.5.4.8.3.3.8  Overrun During Receive
                9. 12.1.5.4.8.3.3.9  Status FIFO
                10. 12.1.5.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.5.4.8.3.3.11 Time-guard
              4. 12.1.5.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.5.4.8.3.4.1 Abort Sequence
                2. 12.1.5.4.8.3.4.2 Pulse Shaping
                3. 12.1.5.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.5.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.5.4.8.4 CIR Mode
              1. 12.1.5.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.5.4.8.4.2 CIR Data Formatting
                1. 12.1.5.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.5.4.8.4.2.2 CIR Transmission
                3. 12.1.5.4.8.4.2.3 CIR Reception
        5. 12.1.5.5 UART Programming Guide
          1. 12.1.5.5.1 UART Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 UART Module Global Initialization
          2. 12.1.5.5.2 UART Mode selection
          3. 12.1.5.5.3 UART Submode selection
          4. 12.1.5.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.5.5.4.1 DMA mode Settings
            2. 12.1.5.5.4.2 FIFO Trigger Settings
          5. 12.1.5.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.5.5.5.1 Baud rate settings
            2. 12.1.5.5.5.2 Interrupt settings
            3. 12.1.5.5.5.3 Protocol settings
            4. 12.1.5.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.5.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.5.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.5.5.6.1 Hardware Flow Control Configuration
            2. 12.1.5.5.6.2 Software Flow Control Configuration
          7. 12.1.5.5.7 IrDA Programming Model
            1. 12.1.5.5.7.1 SIR mode
              1. 12.1.5.5.7.1.1 Receive
              2. 12.1.5.5.7.1.2 Transmit
            2. 12.1.5.5.7.2 MIR mode
              1. 12.1.5.5.7.2.1 Receive
              2. 12.1.5.5.7.2.2 Transmit
            3. 12.1.5.5.7.3 FIR mode
              1. 12.1.5.5.7.3.1 Receive
              2. 12.1.5.5.7.3.2 Transmit
        6. 12.1.5.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet Switch (CPSW3G)
        1. 12.2.1.1 CPSW0 Overview
          1. 12.2.1.1.1 CPSW0 Features
          2. 12.2.1.1.2 CPSW0 Not Supported Features
          3. 12.2.1.1.3 CPSW Terminology
        2. 12.2.1.2 CPSW0 Environment
          1. 12.2.1.2.1 CPSW0 RMII Interface
          2. 12.2.1.2.2 CPSW0 RGMII Interface
        3. 12.2.1.3 CPSW0 Integration
        4. 12.2.1.4 CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_3G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1  Multicast Address Table Entry
                2. 12.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 12.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 12.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 12.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 12.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 12.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 12.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 12.2.1.4.6.1.9.9  EtherType Table Entry
                10. 12.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 12.2.1.4.6.1.9.11 IPv6 Table Entry High
                12. 12.2.1.4.6.1.9.12 IPv6 Table Entry Low
              10. 12.2.1.4.6.1.10 Multicast Address
                1. 12.2.1.4.6.1.10.1 Multicast Ranges
              11. 12.2.1.4.6.1.11 Aging and Auto Aging
              12. 12.2.1.4.6.1.12 ALE Policing and Classification
                1. 12.2.1.4.6.1.12.1 ALE Policing
                2. 12.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 12.2.1.4.6.1.12.3 ALE Classification
                  1. 2.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping
              13. 12.2.1.4.6.1.13 Mirroring
              14. 12.2.1.4.6.1.14 Trunking
              15. 12.2.1.4.6.1.15 DSCP
              16. 12.2.1.4.6.1.16 Packet Forwarding Processes
                1. 12.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.16.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.16.3 Egress Process
                4. 12.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 12.2.1.4.6.1.17 VLAN Aware Mode
              18. 12.2.1.4.6.1.18 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 12.2.1.4.6.10.1.1 CRC Insertion
                2. 12.2.1.4.6.10.1.2 MTXER
                3. 12.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 12.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 12.2.1.4.6.10.1.5 Back Off
                6. 12.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 12.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.1.4.6.18.8  Rx Cut Thru with No Delay
              9. 12.2.1.4.6.18.9  Rx Cut Thru with Delay
              10. 12.2.1.4.6.18.10 Rx Cut Thru Store-and-Forward
              11. 12.2.1.4.6.18.11 Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.11.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.1.4.6.18.11.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.1.4.6.18.11.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.1.4.6.18.11.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.1.4.6.18.11.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.1.4.6.18.11.6  Collisions (Offset = 3A048h)
                7. 12.2.1.4.6.18.11.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.1.4.6.18.11.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.1.4.6.18.11.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.1.4.6.18.11.10 Late Collisions (Offset = 3A058h)
                11. 12.2.1.4.6.18.11.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.1.4.6.18.11.12 Tx Octets (Offset = 3A064h)
                13. 12.2.1.4.6.18.11.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.1.4.6.18.11.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 12.2.1.4.6.18.11.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.1.4.6.18.11.16 IET Transmit Merge Hold Count (Offset = 3A150h)
                17. 12.2.1.4.6.18.11.17 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                18. 12.2.1.4.6.18.11.18 Tx CRC Errors
                19. 12.2.1.4.6.18.11.19 Tx Cut Thru
                20. 12.2.1.4.6.18.11.20 Tx Cut Thru Store-and-Forward
              12. 12.2.1.4.6.18.12 Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.12.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.1.4.6.18.12.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.1.4.6.18.12.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.1.4.6.18.12.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.1.4.6.18.12.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.1.4.6.18.12.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.1.4.6.18.12.7 Net Octets (Offset = 3A080h)
              13. 12.2.1.4.6.18.13 4714
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 4742
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_3G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_3G Ingress)
            3. 12.2.1.4.8.3 Cut-Thru
              1. 12.2.1.4.8.3.1 Host Port Cut-Thru Operations
              2. 12.2.1.4.8.3.2 Cut-Thru Error Packets
            4. 12.2.1.4.8.4 Port Speed
            5. 12.2.1.4.8.5 CPPI Checksum Offload
              1. 12.2.1.4.8.5.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.5.1.1 IPV4 UDP
                2. 12.2.1.4.8.5.1.2 IPV4 TCP
                3. 12.2.1.4.8.5.1.3 IPV6 UDP
                4. 12.2.1.4.8.5.1.4 IPV6 TCP
            6. 12.2.1.4.8.6 CPPI Receive Checksum Offload
            7. 12.2.1.4.8.7 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 CPSW0 Registers
          1. 12.2.1.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  CPSW0_MDIO Registers
          3. 12.2.1.6.3  CPSW0_CPTS Registers
          4. 12.2.1.6.4  CPSW0_CONTROL Registers
          5. 12.2.1.6.5  CPSW0_CPINT Registers
          6. 12.2.1.6.6  CPSW0_RAM Registers
          7. 12.2.1.6.7  CPSW0_STAT0 Registers
          8. 12.2.1.6.8  CPSW0_STATN Registers
          9. 12.2.1.6.9  CPSW0_ALE Registers
          10. 12.2.1.6.10 CPSW0_PCSR Registers
          11. 12.2.1.6.11 CPSW0_ECC Registers
      2. 12.2.2 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.2.1 PCIe Subsystem Overview
          1. 12.2.2.1.1 PCIe Subsystem Features
          2. 12.2.2.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.2.2 PCIe Subsystem Environment
        3. 12.2.2.3 PCIe Subsystem Integration
        4. 12.2.2.4 PCIe Subsystem Functional Description
          1. 12.2.2.4.1  PCIe Subsystem Block Diagram
            1. 12.2.2.4.1.1 PCIe PHY Interface
              1. 12.2.2.4.1.1.1 PCIe Core Module
            2. 12.2.2.4.1.2 Custom Logic
          2. 12.2.2.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.2.4.2.1 PCIe Conventional Reset
            2. 12.2.2.4.2.2 PCIe Function Level Reset
            3. 12.2.2.4.2.3 PCIe Reset Isolation
              1. 12.2.2.4.2.3.1 Root Complex Reset with Device Not Reset
              2. 12.2.2.4.2.3.2 Device Reset with Root Complex Not Reset
              3. 12.2.2.4.2.3.3 End Point Device Reset with Root Complex Not Reset
              4. 12.2.2.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.2.4.2.4 PCIe Reset Limitations
            5. 12.2.2.4.2.5 PCIe Reset Requirements
          3. 12.2.2.4.3  PCIe Subsystem Power Management
            1. 12.2.2.4.3.1 CBA Power Management
          4. 12.2.2.4.4  PCIe Subsystem Interrupts
            1. 12.2.2.4.4.1 Interrupts Aggregation
            2. 12.2.2.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.2.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.2.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.2.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.2.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.2.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.2.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.2.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.2.4.4.3.5 PTM Valid Interrupt
            4. 12.2.2.4.4.4 Interrupt Generation in RC Mode
            5. 12.2.2.4.4.5 Interrupt Reception in RC Mode
              1. 12.2.2.4.4.5.1 PCIe Legacy Interrupt Reception in RC Mode
              2. 12.2.2.4.4.5.2 MSI/MSI-X Interrupt Reception in RC Mode
              3. 12.2.2.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.2.4.4.6 Common Interrupt Reception in RC and EP Modes
              1. 12.2.2.4.4.6.1 PCIe Local Interrupt
              2. 12.2.2.4.4.6.2 PHY Interrupt
              3. 12.2.2.4.4.6.3 Link down Interrupt
              4. 12.2.2.4.4.6.4 Transaction Error Interrupts
              5. 12.2.2.4.4.6.5 Power Management Event Interrupt
            7. 12.2.2.4.4.7 ECC Aggregator Interrupts
            8. 12.2.2.4.4.8 CPTS Interrupt
          5. 12.2.2.4.5  PCIe Subsystem DMA Support
            1. 12.2.2.4.5.1 PCIe DMA Support in RC Mode
            2. 12.2.2.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.2.4.6  PCIe Subsystem Transactions
            1. 12.2.2.4.6.1 PCIe Supported Transactions
            2. 12.2.2.4.6.2 PCIe Transaction Limitations
          7. 12.2.2.4.7  PCIe Subsystem Address Translation
            1. 12.2.2.4.7.1 PCIe Inbound Address Translation
              1. 12.2.2.4.7.1.1 Root Complex Inbound PCIe to AXI Address Translation
              2. 12.2.2.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.2.4.7.2 PCIe Outbound Address Translation
              1. 12.2.2.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.2.4.8  PCIe Subsystem Quality-of-Service (QoS)
          9. 12.2.2.4.9  PCIe Subsystem Precision Time Measurement (PTM)
          10. 12.2.2.4.10 PCIe Subsystem Loopback
            1. 12.2.2.4.10.1 PCIe Loopback
              1. 12.2.2.4.10.1.1 PCIe Loopback Initiator Mode
              2. 12.2.2.4.10.1.2 PCIe Loopback Target Mode
          11. 12.2.2.4.11 PCIe Subsystem Error Handling
          12. 12.2.2.4.12 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.2.4.12.1 ECC Aggregators
            2. 12.2.2.4.12.2 RAM ECC Inversion
        5. 12.2.2.5 PCIe Subsystem Registers
          1. 12.2.2.5.1 PCIE Registers
      3. 12.2.3 Serializer/Deserializer (SerDes)
        1. 12.2.3.1 SerDes Overview
          1. 12.2.3.1.1 SerDes Features
          2. 12.2.3.1.2 Not Supported Features
          3. 12.2.3.1.3 Industry Standards Compatibility
        2. 12.2.3.2 SerDes Environment
          1. 12.2.3.2.1 SerDes I/Os
        3. 12.2.3.3 SerDes Integration
          1. 12.2.3.3.1 WIZ Settings
            1. 12.2.3.3.1.1 Interface Selection
            2. 12.2.3.3.1.2 Internal Reference Clock Selection
        4. 12.2.3.4 SerDes Functional Description
          1. 12.2.3.4.1 SerDes Block Diagram
      4. 12.2.4 Universal Serial Bus Subsystem (USBSS)
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
          1. 12.2.4.2.1 USB I/Os
          2. 12.2.4.2.2 USB Subsystem Application
          3. 12.2.4.2.3 VBUS Sense
        3. 12.2.4.3 USB Integration
          1. 12.2.4.3.1 Resets, Interrupts, and Clocks
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Controller Reset
          2. 12.2.4.4.2 Overcurrent Detection
          3. 12.2.4.4.3 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB_RAMS_INJ_CFG Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1.       4890
        2. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        3. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        4. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MAIN Domain
        5. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS Regions
            1. 12.3.1.4.2.1 FSS Regions Boot Size Configuration
          3. 12.3.1.4.3 FSS Memory Regions
        6. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Power Up/Down Sequence
        7. 12.3.1.6 FSS Registers
          1. 12.3.1.6.1 FSS Registers
          2. 12.3.1.6.2 FSS_FSAS_0 Registers
          3. 12.3.1.6.3 FSS_OSPI_0 Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1.       4911
        2. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        3. 12.3.2.2 OSPI Environment
        4. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MAIN Domain
        5. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
              4. 12.3.2.4.2.1.4 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        6. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        7. 12.3.2.6 OSPI Registers
      3. 12.3.3 General-Purpose Memory Controller (GPMC)
        1. 12.3.3.1 GPMC Overview
          1. 12.3.3.1.1 GPMC Features
          2. 12.3.3.1.2 GPMC Not Supported Features
        2. 12.3.3.2 GPMC Environment
          1. 12.3.3.2.1 GPMC Modes
          2. 12.3.3.2.2 GPMC I/O Signals
        3. 12.3.3.3 GPMC Integration
          1. 12.3.3.3.1 GPMC Integration in MAIN Domain
        4. 12.3.3.4 GPMC Functional Description
          1. 12.3.3.4.1  GPMC Block Diagram
          2. 12.3.3.4.2  GPMC Clock Configuration
          3. 12.3.3.4.3  GPMC Power Management
          4. 12.3.3.4.4  GPMC Interrupt Requests
          5. 12.3.3.4.5  GPMC Interconnect Port Interface
          6. 12.3.3.4.6  GPMC Address and Data Bus
            1. 12.3.3.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.3.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.3.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.3.4.7.2 Access Protocol
              1. 12.3.3.4.7.2.1 Supported Devices
              2. 12.3.3.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.3.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.3.4.7.3 External Signals
              1. 12.3.3.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.3.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.3.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.3.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.3.4.7.3.1.5 Wait With NAND Device
                6. 12.3.3.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.3.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.3.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.3.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.3.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.3.4.7.3.2 DIR Pin
              3. 12.3.3.4.7.3.3 Reset
              4. 12.3.3.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.3.4.7.4 Error Handling
          8. 12.3.3.4.8  GPMC Timing Setting
            1. 12.3.3.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.3.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.3.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.3.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.3.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.3.4.8.6  GPMC_CLKOUT
            7. 12.3.3.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.3.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.3.4.8.8.1 Access Time on Read Access
              2. 12.3.3.4.8.8.2 Access Time on Write Access
            9. 12.3.3.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.3.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.3.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.3.4.8.10 Bus Keeping Support
          9. 12.3.3.4.9  GPMC NOR Access Description
            1. 12.3.3.4.9.1 Asynchronous Access Description
              1. 12.3.3.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.3.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.3.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.3.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.3.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.3.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.3.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.3.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.3.4.9.2 Synchronous Access Description
              1. 12.3.3.4.9.2.1 Synchronous Single Read
              2. 12.3.3.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.3.4.9.2.3 Synchronous Single Write
              4. 12.3.3.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.3.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.3.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.3.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.3.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.3.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.3.4.9.4 Page and Burst Support
            5. 12.3.3.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.3.4.10 GPMC pSRAM Access Specificities
          11. 12.3.3.4.11 GPMC NAND Access Description
            1. 12.3.3.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.3.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.3.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.3.4.11.1.3 Command Latch Cycle
              4. 12.3.3.4.11.1.4 Address Latch Cycle
              5. 12.3.3.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.3.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.3.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.3.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.3.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.3.4.11.2 NAND Device-Ready Pin
              1. 12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.3.4.11.3 ECC Calculator
              1. 12.3.3.4.11.3.1 Hamming Code
                1. 12.3.3.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.3.4.11.3.1.2 ECC Enabling
                3. 12.3.3.4.11.3.1.3 ECC Computation
                4. 12.3.3.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.3.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.3.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.3.4.11.3.2 BCH Code
                1. 12.3.3.4.11.3.2.1 Requirements
                2. 12.3.3.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.3.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.3.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.3.4.11.3.2.2.3 Wrapping Modes
                    1. 3.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 3.4.11.3.2.2.3.2  Mode 0x1
                    3. 3.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 3.4.11.3.2.2.3.4  Mode 0x2
                    5. 3.4.11.3.2.2.3.5  Mode 0x3
                    6. 3.4.11.3.2.2.3.6  Mode 0x7
                    7. 3.4.11.3.2.2.3.7  Mode 0x8
                    8. 3.4.11.3.2.2.3.8  Mode 0x4
                    9. 3.4.11.3.2.2.3.9  Mode 0x9
                    10. 3.4.11.3.2.2.3.10 Mode 0x5
                    11. 3.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 3.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.3.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.3.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.3.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.3.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.3.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.3.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.3.4.11.4.2 Prefetch Mode
              3. 12.3.3.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.3.4.11.4.4 Write-Posting Mode
              5. 12.3.3.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.3.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.3.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.3.4.12 GPMC Memory Regions
          13. 12.3.3.4.13 GPMC Use Cases and Tips
            1. 12.3.3.4.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.3.4.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.3.4.13.1.2 Typical GPMC Setup
                1. 12.3.3.4.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.3.4.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.3.4.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.3.4.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.3.4.13.2.1 Supported Memories or Devices
                1. 12.3.3.4.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.3.4.13.2.1.2 NAND Interface Protocol
                3. 12.3.3.4.13.2.1.3 NOR Interface Protocol
                4. 12.3.3.4.13.2.1.4 Other Technologies
        5. 12.3.3.5 GPMC Basic Programming Model
          1. 12.3.3.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.3.5.2 GPMC Initialization
          3. 12.3.3.5.3 GPMC Configuration in NOR Mode
          4. 12.3.3.5.4 GPMC Configuration in NAND Mode
          5. 12.3.3.5.5 Set Memory Access
          6. 12.3.3.5.6 GPMC Timing Parameters
            1. 12.3.3.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.3.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.3.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.3.6 GPMC Registers
      4. 12.3.4 Error Location Module (ELM)
        1. 12.3.4.1 ELM Overview
          1. 12.3.4.1.1 ELM Features
          2. 12.3.4.1.2 ELM Not Supported Features
        2. 12.3.4.2 ELM Integration
          1. 12.3.4.2.1 ELM Integration in MAIN Domain
        3. 12.3.4.3 ELM Functional Description
          1. 12.3.4.3.1 ELM Software Reset
          2. 12.3.4.3.2 ELM Power Management
          3. 12.3.4.3.3 ELM Interrupt Requests
          4. 12.3.4.3.4 ELM Processing Initialization
          5. 12.3.4.3.5 ELM Processing Sequence
          6. 12.3.4.3.6 ELM Processing Completion
        4. 12.3.4.4 ELM Basic Programming Model
          1. 12.3.4.4.1 ELM Low-Level Programming Model
            1. 12.3.4.4.1.1 Processing Initialization
            2. 12.3.4.4.1.2 Read Results
            3. 12.3.4.4.1.3 5138
          2. 12.3.4.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.4.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.4.5 ELM Registers
      5. 12.3.5 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.5.1 MMCSD Overview
          1. 12.3.5.1.1 MMCSD Features
          2. 12.3.5.1.2 MMCSD Not Supported Features
        2. 12.3.5.2 MMCSD Environment
          1. 12.3.5.2.1 Protocol and Data Format
            1. 12.3.5.2.1.1 Protocol
            2. 12.3.5.2.1.2 Data Format
              1. 12.3.5.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.5.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.5.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.5.3 MMCSD Integration
          1. 12.3.5.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.5.4 MMCSD Functional Description
          1. 12.3.5.4.1 Block Diagram
          2. 12.3.5.4.2 Memory Regions
          3. 12.3.5.4.3 Interrupt Requests
          4. 12.3.5.4.4 ECC Support
            1. 12.3.5.4.4.1 ECC Aggregator
          5. 12.3.5.4.5 Advanced DMA
        5. 12.3.5.5 MMCSD Programming Guide
          1. 12.3.5.5.1 Sequences
            1. 12.3.5.5.1.1  SD Card Detection
            2. 12.3.5.5.1.2  SD Clock Control
              1. 12.3.5.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.5.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.5.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.5.5.1.3  SD Bus Power Control
            4. 12.3.5.5.1.4  Changing Bus Width
            5. 12.3.5.5.1.5  Timeout Setting on DAT Line
            6. 12.3.5.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.5.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.5.5.1.7  SD Transaction Generation
              1. 12.3.5.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.5.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.5.5.1.7.1.3 5178
              2. 12.3.5.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.2.1 Not using DMA
                2. 12.3.5.5.1.7.2.2 Using SDMA
                3. 12.3.5.5.1.7.2.3 Using ADMA
            8. 12.3.5.5.1.8  Abort Transaction
              1. 12.3.5.5.1.8.1 Asynchronous Abort
              2. 12.3.5.5.1.8.2 Synchronous Abort
            9. 12.3.5.5.1.9  Changing Bus Speed Mode
            10. 12.3.5.5.1.10 Error Recovery
              1. 12.3.5.5.1.10.1 Error Interrupt Recovery
              2. 12.3.5.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.5.5.1.11 Wakeup Control (Optional)
            12. 12.3.5.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.5.5.1.12.1 Suspend Sequence
              2. 12.3.5.5.1.12.2 Resume Sequence
              3. 12.3.5.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.5.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.5.5.2 Driver Flow Sequence
            1. 12.3.5.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.5.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.5.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.5.5.2.2 Boot Operation
              1. 12.3.5.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.5.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.5.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.5.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.5.5.2.3.1 Sampling Clock Tuning
              2. 12.3.5.5.2.3.2 Tuning Modes
              3. 12.3.5.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.5.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.5.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.5.5.2.4.2 Task Issuance Sequence
              3. 12.3.5.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.5.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.5.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.5.6 MMCSD Registers
          1. 12.3.5.6.1 MMCSD0 Subsystem Registers
          2. 12.3.5.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.5.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.5.6.4 MMCSD0 Host Controller Registers
          5. 12.3.5.6.5 MMCSD1 Subsystem Registers
          6. 12.3.5.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.5.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.5.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Modular Controller Area Network (MCAN)
        1. 12.4.1.1 MCAN Overview
          1. 12.4.1.1.1 MCAN Features
          2. 12.4.1.1.2 MCAN Not Supported Features
        2. 12.4.1.2 MCAN Environment
          1. 12.4.1.2.1 CAN Network Basics
        3. 12.4.1.3 MCAN Integration
          1. 12.4.1.3.1 MCAN Integration in MAIN Domain
        4. 12.4.1.4 MCAN Functional Description
          1. 12.4.1.4.1  Module Clocking Requirements
          2. 12.4.1.4.2  Interrupt and DMA Requests
            1. 12.4.1.4.2.1 Interrupt Requests
            2. 12.4.1.4.2.2 DMA Requests
          3. 12.4.1.4.3  Operating Modes
            1. 12.4.1.4.3.1 Software Initialization
            2. 12.4.1.4.3.2 Normal Operation
            3. 12.4.1.4.3.3 CAN FD Operation
            4. 12.4.1.4.3.4 Transmitter Delay Compensation
              1. 12.4.1.4.3.4.1 Description
              2. 12.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.1.4.3.5 Restricted Operation Mode
            6. 12.4.1.4.3.6 Bus Monitoring Mode
            7. 12.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.1.4.3.8 Power Down (Sleep Mode)
              1. 12.4.1.4.3.8.1 External Clock Stop Mode
              2. 12.4.1.4.3.8.2 Suspend Mode
              3. 12.4.1.4.3.8.3 Wakeup request
            9. 12.4.1.4.3.9 Test Modes
              1. 12.4.1.4.3.9.1 Internal Loopback Mode
          4. 12.4.1.4.4  Timestamp Generation
            1. 12.4.1.4.4.1 External Timestamp Counter
          5. 12.4.1.4.5  Timeout Counter
          6. 12.4.1.4.6  ECC Support
            1. 12.4.1.4.6.1 ECC Wrapper
            2. 12.4.1.4.6.2 ECC Aggregator
          7. 12.4.1.4.7  Rx Handling
            1. 12.4.1.4.7.1 Acceptance Filtering
              1. 12.4.1.4.7.1.1 Range Filter
              2. 12.4.1.4.7.1.2 Filter for specific IDs
              3. 12.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.1.4.7.1.4 Standard Message ID Filtering
              5. 12.4.1.4.7.1.5 Extended Message ID Filtering
            2. 12.4.1.4.7.2 Rx FIFOs
              1. 12.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.1.4.7.3 Dedicated Rx Buffers
              1. 12.4.1.4.7.3.1 Rx Buffer Handling
            4. 12.4.1.4.7.4 Debug on CAN Support
          8. 12.4.1.4.8  Tx Handling
            1. 12.4.1.4.8.1 Transmit Pause
            2. 12.4.1.4.8.2 Dedicated Tx Buffers
            3. 12.4.1.4.8.3 Tx FIFO
            4. 12.4.1.4.8.4 Tx Queue
            5. 12.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.1.4.8.7 Transmit Cancellation
            8. 12.4.1.4.8.8 Tx Event Handling
          9. 12.4.1.4.9  FIFO Acknowledge Handling
          10. 12.4.1.4.10 Message RAM
            1. 12.4.1.4.10.1 Message RAM Configuration
            2. 12.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.1.4.10.3 Tx Buffer Element
            4. 12.4.1.4.10.4 Tx Event FIFO Element
            5. 12.4.1.4.10.5 Standard Message ID Filter Element
            6. 12.4.1.4.10.6 Extended Message ID Filter Element
        5. 12.4.1.5 MCAN Registers
          1. 12.4.1.5.1 MCAN Subsystem Registers
          2. 12.4.1.5.2 MCAN Core Registers
          3. 12.4.1.5.3 MCAN ECC Aggregator Registers
      2. 12.4.2 Enhanced Capture (ECAP) Module
        1. 12.4.2.1 ECAP Overview
          1. 12.4.2.1.1 ECAP Features
        2. 12.4.2.2 ECAP Environment
          1. 12.4.2.2.1 ECAP I/O Interface
        3. 12.4.2.3 ECAP Integration
          1. 12.4.2.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.2.4 ECAP Functional Description
          1. 12.4.2.4.1 Capture and APWM Operating Modes
            1. 12.4.2.4.1.1 ECAP Capture Mode Description
              1. 12.4.2.4.1.1.1 ECAP Event Prescaler
              2. 12.4.2.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.2.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.2.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.2.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.2.4.1.1.6 ECAP Interrupt Control
              7. 12.4.2.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.2.4.1.2 ECAP APWM Mode Operation
          2. 12.4.2.4.2 Summary of ECAP Functional Registers
        5. 12.4.2.5 ECAP Use Cases
          1. 12.4.2.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.2.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.2.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.2.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.2.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.2.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.2.5.5 Application of the APWM Mode
            1. 12.4.2.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.2.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.2.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.2.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.2.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.2.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.2.6 ECAP Registers
      3. 12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.3.1 EPWM Overview
          1. 12.4.3.1.1 EPWM Features
          2. 12.4.3.1.2 EPWM Not Supported Features
          3. 12.4.3.1.3 Multiple EPWM Module Details
        2. 12.4.3.2 EPWM Environment
        3. 12.4.3.3 EPWM Integration
          1. 12.4.3.3.1 EPWM Additional Integration Details
            1. 12.4.3.3.1.1 EPWM Tripzone Connectivity
            2. 12.4.3.3.1.2 Daisy-Chain Connectivity between EPWM Modules
            3. 12.4.3.3.1.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
            4. 12.4.3.3.1.4 EPWM Modules Time-Base Clock Gating
        4. 12.4.3.4 EPWM Functional Description
          1. 12.4.3.4.1  EPWM Submodule Features
            1. 12.4.3.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.3.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.3.4.2.1 Overview
            2. 12.4.3.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.3.4.2.3 Calculating PWM Period and Frequency
              1. 12.4.3.4.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.3.4.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.3.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.3.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.3.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.3.4.3.1 Overview
            2. 12.4.3.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.3.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.3.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.3.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.3.4.4.1 Overview
            2. 12.4.3.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.3.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.3.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.3.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.3.4.5.1 Overview
            2. 12.4.3.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.3.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.3.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.3.4.6.1 Overview
            2. 12.4.3.4.6.2 5369
            3. 12.4.3.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.3.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.3.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.3.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.3.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.3.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.3.4.7.1 Overview
            2. 12.4.3.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.3.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.3.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.3.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.3.4.8.1 Overview
            2. 12.4.3.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.3.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.3.4.8.4 Operation Overview of the EPWM SOCx Pulse Generator
          9. 12.4.3.4.9  EPWM Functional Register Groups
          10. 12.4.3.4.10 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.3.5 EPWM Registers
      4. 12.4.4 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.4.1 EQEP Overview
          1. 12.4.4.1.1 EQEP Features
          2. 12.4.4.1.2 EQEP Not Supported Features
        2. 12.4.4.2 EQEP Environment
          1. 12.4.4.2.1 EQEP I/O Interface
        3. 12.4.4.3 EQEP Integration
          1. 12.4.4.3.1 Device Specific EQEP Features
        4. 12.4.4.4 EQEP Functional Description
          1. 12.4.4.4.1 EQEP Inputs
          2. 12.4.4.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.4.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.4.4.2.1.1 Quadrature Count Mode
              2. 12.4.4.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.4.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.4.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.4.4.2.2 EQEP Input Polarity Selection
            3. 12.4.4.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.4.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.4.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.4.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.4.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.4.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.4.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.4.4.3.2 EQEP Position Counter Latch
              1. 12.4.4.4.3.2.1 Index Event Latch
              2. 12.4.4.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.4.4.3.3 EQEP Position Counter Initialization
            4. 12.4.4.4.3.4 EQEP Position-Compare Unit
          4. 12.4.4.4.4 EQEP Edge Capture Unit
          5. 12.4.4.4.5 EQEP Watchdog
          6. 12.4.4.4.6 Unit Timer Base
          7. 12.4.4.4.7 EQEP Interrupt Structure
          8. 12.4.4.4.8 Summary of EQEP Functional Registers
        5. 12.4.4.5 EQEP Registers
      5. 12.4.5 Fast Serial Interface (FSI)
        1. 12.4.5.1 FSI Overview
          1. 12.4.5.1.1 FSI Features
          2. 12.4.5.1.2 FSI Not Supported Featurs
        2. 12.4.5.2 FSI Environment
          1. 12.4.5.2.1 Signal Description
        3. 12.4.5.3 FSI Integration
          1. 12.4.5.3.1 FSI Interrupts
            1. 12.4.5.3.1.1 Transmitter Interrupts
            2. 12.4.5.3.1.2 Receiver Interrupts
            3. 12.4.5.3.1.3 Configuring Interrupts
            4. 12.4.5.3.1.4 Handling Interrupts
        4. 12.4.5.4 FSI Functional Description
          1. 12.4.5.4.1 FSI Functional Description
          2. 12.4.5.4.2 FSI Transmitter Module (FSI_TX)
            1. 12.4.5.4.2.1 Initialization
            2. 12.4.5.4.2.2 FSI_TX Clocking
            3. 12.4.5.4.2.3 Transmitting Frames
              1. 12.4.5.4.2.3.1 Software Triggered Frames
              2. 12.4.5.4.2.3.2 Ping Frame Generation
                1. 12.4.5.4.2.3.2.1 Automatic Ping Frames
                2. 12.4.5.4.2.3.2.2 Software Triggered Ping Frame
            4. 12.4.5.4.2.4 Transmit Buffer Management
            5. 12.4.5.4.2.5 CRC Submodule
            6. 12.4.5.4.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
            7. 12.4.5.4.2.7 Reset
          3. 12.4.5.4.3 FSI Receiver Module (FSI_RX)
            1. 12.4.5.4.3.1  Initialization
            2. 12.4.5.4.3.2  FSI_RX Clocking
            3. 12.4.5.4.3.3  Receiving Frames
            4. 12.4.5.4.3.4  Ping Frame Watchdog
            5. 12.4.5.4.3.5  Frame Watchdog
            6. 12.4.5.4.3.6  Delay Line Control
            7. 12.4.5.4.3.7  Buffer Management
            8. 12.4.5.4.3.8  CRC Submodule
            9. 12.4.5.4.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 12.4.5.4.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 12.4.5.4.3.11 FSI_RX Reset
          4. 12.4.5.4.4 Frame Format
            1. 12.4.5.4.4.1 FSI Frame Phases
            2. 12.4.5.4.4.2 Frame Types
              1. 12.4.5.4.4.2.1 Ping Frames
              2. 12.4.5.4.4.2.2 Error Frames
              3. 12.4.5.4.4.2.3 Data Frames
            3. 12.4.5.4.4.3 Multi-Lane Transmission
          5. 12.4.5.4.5 Flush Sequence
          6. 12.4.5.4.6 Internal Loopback
          7. 12.4.5.4.7 CRC Generation
          8. 12.4.5.4.8 ECC Module
          9. 12.4.5.4.9 FSI-SPI Compatibility Mode
            1. 12.4.5.4.9.1 Available SPI Modes
              1. 12.4.5.4.9.1.1 FSITX as SPI Controller, Transmit Only
                1. 12.4.5.4.9.1.1.1 Initialization
                2. 12.4.5.4.9.1.1.2 Operation
              2. 12.4.5.4.9.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 12.4.5.4.9.1.2.1 Initialization
                2. 12.4.5.4.9.1.2.2 Operation
              3. 12.4.5.4.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 12.4.5.4.9.1.3.1 Initialization
                2. 12.4.5.4.9.1.3.2 Operation
        5. 12.4.5.5 FSI Programing Guide
          1. 12.4.5.5.1 Establishing the Communication Link
            1. 12.4.5.5.1.1 Establishing the Communication Link from the Main Device
            2. 12.4.5.5.1.2 Establishing the Communication Link from the Remote Device
          2. 12.4.5.5.2 Register Protection
          3. 12.4.5.5.3 Emulation Mode
        6. 12.4.5.6 FSI Registers
          1. 12.4.5.6.1 FSITX Registers
          2. 12.4.5.6.2 FSIRX Registers
    5. 12.5 Timer Modules
      1. 12.5.1 Global Timebase Counter (GTC)
        1. 12.5.1.1 Global Timebase Counter (GTC)
          1. 12.5.1.1.1 GTC Overview
            1. 12.5.1.1.1.1 GTC Features
            2. 12.5.1.1.1.2 GTC Not Supported Features
          2. 12.5.1.1.2 GTC Integration
        2. 12.5.1.2 GTC Functional Description
          1. 12.5.1.2.1 GTC Block Diagram
          2. 12.5.1.2.2 GTC Counter
          3. 12.5.1.2.3 GTC Register Partitioning
        3. 12.5.1.3 GTC Registers
          1. 12.5.1.3.1  GTC_CFG0_GTC_PID Registers
          2. 12.5.1.3.2  GTC_CFG0_GTC_GTC_PID Registers
          3. 12.5.1.3.3  GTC_CFG0_GTC_PUSHEVT Registers
          4. 12.5.1.3.4  GTC_CFG1_GTC_CNTCR Registers
          5. 12.5.1.3.5  GTC_CFG1_GTC_CNTSR Registers
          6. 12.5.1.3.6  GTC_CFG1_GTC_CNTCV_LO Registers
          7. 12.5.1.3.7  GTC_CFG1_GTC_CNTCV_HI Registers
          8. 12.5.1.3.8  GTC_CFG1_GTC_CNTFID0 Registers
          9. 12.5.1.3.9  GTC_CFG1_GTC_CNTFID1 Registers
          10. 12.5.1.3.10 GTC_CFG2_GTC_CNTCVS_LO Registers
          11. 12.5.1.3.11 GTC_CFG2_GTC_CNTCVS_HI Registers
          12. 12.5.1.3.12 GTC_CFG3_GTC_CNTTIDR Registers
          13. 12.5.1.3.13 Access Table
      2. 12.5.2 RTI-Windowed Watchdog Timer (WWDT)
        1. 12.5.2.1 RTI Overview
          1. 12.5.2.1.1 RTI Features
          2. 12.5.2.1.2 RTI Not Supported Features
        2. 12.5.2.2 RTI Integration
          1. 12.5.2.2.1 RTI Integration in MCU Domain
          2. 12.5.2.2.2 RTI Integration in MAIN Domain
        3. 12.5.2.3 RTI Functional Description
          1. 12.5.2.3.1 RTI Digital Windowed Watchdog
            1. 12.5.2.3.1.1 RTI Debug Mode Behavior
            2. 12.5.2.3.1.2 RTI Low Power Mode Operation
          2. 12.5.2.3.2 RTI Digital Watchdog
          3. 12.5.2.3.3 RTI Counter Operation
        4. 12.5.2.4 RTI Registers
      3. 12.5.3 Timers
        1. 12.5.3.1 Timers Overview
          1. 12.5.3.1.1 Timers Features
          2. 12.5.3.1.2 Timers Not Supported Features
        2. 12.5.3.2 Timers Environment
          1. 12.5.3.2.1 Timer External System Interface
        3. 12.5.3.3 Timers Integration
          1. 12.5.3.3.1 Timers Integration in MCU Domain
          2. 12.5.3.3.2 Timers Integration in MAIN Domain
        4. 12.5.3.4 Timers Functional Description
          1. 12.5.3.4.1  Timer Block Diagram
          2. 12.5.3.4.2  Timer Power Management
            1. 12.5.3.4.2.1 Wake-Up Capability
          3. 12.5.3.4.3  Timer Software Reset
          4. 12.5.3.4.4  Timer Interrupts
          5. 12.5.3.4.5  Timer Mode Functionality
            1. 12.5.3.4.5.1 1-ms Tick Generation
          6. 12.5.3.4.6  Timer Capture Mode Functionality
          7. 12.5.3.4.7  Timer Compare Mode Functionality
          8. 12.5.3.4.8  Timer Prescaler Functionality
          9. 12.5.3.4.9  Timer Pulse-Width Modulation
          10. 12.5.3.4.10 Timer Counting Rate
          11. 12.5.3.4.11 Timer Under Emulation
          12. 12.5.3.4.12 Accessing Timer Registers
            1. 12.5.3.4.12.1 Writing to Timer Registers
              1. 12.5.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.5.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.5.3.4.12.2 Reading From Timer Counter Registers
              1. 12.5.3.4.12.2.1 Read Posted
              2. 12.5.3.4.12.2.2 Read Non-Posted
          13. 12.5.3.4.13 Timer Posted Mode Selection
        5. 12.5.3.5 Timers Low-Level Programming Models
          1. 12.5.3.5.1 Timer Global Initialization
            1. 12.5.3.5.1.1 Main Sequence – Timer Module Global Initialization
          2. 12.5.3.5.2 Timer Operational Mode Configuration
            1. 12.5.3.5.2.1 Timer Mode
              1. 12.5.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.5.3.5.2.2 Timer Compare Mode
              1. 12.5.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.5.3.5.2.3 Timer Capture Mode
              1. 12.5.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.5.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.5.3.5.2.3.3 Subsequence – Detect Event
            4. 12.5.3.5.2.4 Timer PWM Mode
              1. 12.5.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.5.3.6 Timers Registers
    6. 12.6 Internal Diagnostics Modules
      1. 12.6.1 Dual Clock Comparator (DCC)
        1. 12.6.1.1 DCC Overview
          1. 12.6.1.1.1 DCC Features
          2. 12.6.1.1.2 DCC Not Supported Features
        2. 12.6.1.2 DCC Integration
          1. 12.6.1.2.1 DCC Integration in MCU Domain
            1. 12.6.1.2.1.1 MCU DCC Input Source Clock Mapping
          2. 12.6.1.2.2 DCC Integration in MAIN Domain
            1. 12.6.1.2.2.1 DCC Input Source Clock Mapping
        3. 12.6.1.3 DCC Functional Description
          1. 12.6.1.3.1 DCC Counter Operation
          2. 12.6.1.3.2 DCC Low Power Mode Operation
          3. 12.6.1.3.3 DCC Suspend Mode Behavior
          4. 12.6.1.3.4 DCC Single-Shot Mode
          5. 12.6.1.3.5 DCC Continuous mode
            1. 12.6.1.3.5.1 DCC Continue on Error
            2. 12.6.1.3.5.2 DCC Error Count
          6. 12.6.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.6.1.3.7 DCC Error Trajectory record
            1. 12.6.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.6.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.6.1.3.7.3 DCC FIFO Details
            4. 12.6.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.6.1.3.8 DCC Count read registers
        4. 12.6.1.4 DCC Registers
      2. 12.6.2 Error Signaling Module (ESM)
        1. 12.6.2.1 ESM Overview
          1. 12.6.2.1.1 ESM Features
        2. 12.6.2.2 ESM Environment
        3. 12.6.2.3 ESM Integration
          1. 12.6.2.3.1 ESM Integration in MCU Domain
          2. 12.6.2.3.2 ESM Integration in MAIN Domain
        4. 12.6.2.4 ESM Functional Description
          1. 12.6.2.4.1 ESM Interrupt Requests
            1. 12.6.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.6.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.6.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.6.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.6.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.6.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.6.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.6.2.4.2 ESM Error Event Inputs
          3. 12.6.2.4.3 ESM Error Pin Output
          4. 12.6.2.4.4 PWM Mode
          5. 12.6.2.4.5 ESM Minimum Time Interval
          6. 12.6.2.4.6 ESM Protection for Registers
          7. 12.6.2.4.7 ESM Clock Stop
        5. 12.6.2.5 ESM Registers
      3. 12.6.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.6.3.1 MCRC Overview
          1. 12.6.3.1.1 MCRC Features
          2. 12.6.3.1.2 MCRC Not Supported Features
        2. 12.6.3.2 MCRC Integration
        3. 12.6.3.3 MCRC Functional Description
          1. 12.6.3.3.1  MCRC Block Diagram
          2. 12.6.3.3.2  MCRC General Operation
          3. 12.6.3.3.3  MCRC Modes of Operation
            1. 12.6.3.3.3.1 AUTO Mode
            2. 12.6.3.3.3.2 Semi-CPU Mode
            3. 12.6.3.3.3.3 Full-CPU Mode
          4. 12.6.3.3.4  PSA Signature Register
          5. 12.6.3.3.5  PSA Sector Signature Register
          6. 12.6.3.3.6  CRC Value Register
          7. 12.6.3.3.7  Raw Data Register
          8. 12.6.3.3.8  Example DMA Controller Setup
            1. 12.6.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.6.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.6.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.6.3.3.9  Pattern Count Register
          10. 12.6.3.3.10 Sector Count Register/Current Sector Register
          11. 12.6.3.3.11 Interrupts
            1. 12.6.3.3.11.1 Overrun Interrupt
            2. 12.6.3.3.11.2 Timeout Interrupt
            3. 12.6.3.3.11.3 Underrun Interrupt
            4. 12.6.3.3.11.4 Compression Complete Interrupt
            5. 12.6.3.3.11.5 Interrupt Offset Register
            6. 12.6.3.3.11.6 Error Handling
          12. 12.6.3.3.12 Power Down Mode
          13. 12.6.3.3.13 Emulation
        4. 12.6.3.4 MCRC Programming Examples
          1. 12.6.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.6.3.4.1.1 DMA Setup
            2. 12.6.3.4.1.2 Timer Setup
            3. 12.6.3.4.1.3 CRC Setup
          2. 12.6.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.6.3.4.2.1 DMA Setup
            2. 12.6.3.4.2.2 CRC Setup
          3. 12.6.3.4.3 Example: Semi-CPU Mode
            1. 12.6.3.4.3.1 DMA Setup
            2. 12.6.3.4.3.2 Timer Setup
            3. 12.6.3.4.3.3 CRC Setup
          4. 12.6.3.4.4 Example: Full-CPU Mode
            1. 12.6.3.4.4.1 CRC Setup
        5. 12.6.3.5 MCRC Registers
      4. 12.6.4 ECC Aggregator
        1. 12.6.4.1 ECC Aggregator Overview
          1. 12.6.4.1.1 ECC Aggregator Features
        2. 12.6.4.2 ECC Aggregator Integration
        3. 12.6.4.3 ECC Aggregator Functional Description
          1. 12.6.4.3.1 ECC Aggregator Block Diagram
          2. 12.6.4.3.2 ECC Aggregator Register Groups
          3. 12.6.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.6.4.3.4 Serial Write Operation
          5. 12.6.4.3.5 Interrupts
          6. 12.6.4.3.6 Inject Only Mode
        4. 12.6.4.4 ECC Aggregators Interconnect
        5. 12.6.4.5 ECC Aggregator Registers
  15. 13On-Chip Debug
    1. 13.1 On-Chip Debug Overview
    2. 13.2 On-Chip Debug Features
    3.     5688
    4. 13.3 On-Chip Debug Functional Description
      1. 13.3.1  On-Chip Debug Block Diagram
      2. 13.3.2  Device Interfaces
        1. 13.3.2.1 JTAG Interface
        2. 13.3.2.2 Trigger and Debug Boot Mode Interface
        3. 13.3.2.3 Trace Port Interface
      3. 13.3.3  Debug and Boundary Scan Access and Control
      4. 13.3.4  Debug Boot Modes and Boundary Scan Compliance
      5. 13.3.5  Power, Reset, Clock Management
      6. 13.3.6  Debug Cross Triggering
      7. 13.3.7  R5FSS0/R5FSS1 Debug
      8. 13.3.8  DMSC Debug
      9. 13.3.9  A53SS0 Debug
      10. 13.3.10 PRU_ICSSG0/PRU_ICSSG1 Debug
      11. 13.3.11 SoC Debug and Trace
        1. 13.3.11.1 Software messaging trace
        2. 13.3.11.2 Debug-Aware Peripherals
        3. 13.3.11.3 Traffic Monitoring With Bus Probes
        4. 13.3.11.4 Global timestamping for trace
      12. 13.3.12 Trace Traffic
        1. 13.3.12.1 Trace Sources
        2. 13.3.12.2 Trace Infrasctructure
        3. 13.3.12.3 Trace Sinks
      13. 13.3.13 Application Support
  16. 14Revision History
12.4.1.5.2 MCAN Core Registers

Table 12-4140 lists the memory-mapped registers for the MCAN Core. All register offset addresses not listed in Table 12-4140 should be considered as reserved locations and the register contents should not be modified.

Table 12-4139 MCAN Core Instances
InstanceBase Address
MCAN0_CFG2070 1000h
MCAN1_CFG2071 1000h
Table 12-4140 MCAN Core Registers
OffsetAcronymRegister NameMCAN0_CFG Physical AddressMCAN1_CFG Physical Address
0hMCAN_CRELCore Release Register2070 1000h2071 1000h
4hMCAN_ENDNEndian Register2070 1004h2071 1004h
ChMCAN_DBTPData Bit Timing & Prescaler Register2070 100Ch2071 100Ch
10hMCAN_TESTTest Register2070 1010h2071 1010h
14hMCAN_RWDRAM Watchdog2070 1014h2071 1014h
18hMCAN_CCCRCC Control Register2070 1018h2071 1018h
1ChMCAN_NBTPNominal Bit Timing & Prescaler Register2070 101Ch2071 101Ch
20hMCAN_TSCCTimestamp Counter Configuration2070 1020h2071 1020h
24hMCAN_TSCVTimestamp Counter Value2070 1024h2071 1024h
28hMCAN_TOCCTimeout Counter Configuration2070 1028h2071 1028h
2ChMCAN_TOCVTimeout Counter Value2070 102Ch2071 102Ch
40hMCAN_ECRError Counter Register2070 1040h2071 1040h
44hMCAN_PSRProtocol Status Register2070 1044h2071 1044h
48hMCAN_TDCRTransmitter Delay Compensation Register2070 1048h2071 1048h
50hMCAN_IRInterrupt Register2070 1050h2071 1050h
54hMCAN_IEInterrupt Enable2070 1054h2071 1054h
58hMCAN_ILSInterrupt Line Select2070 1058h2071 1058h
5ChMCAN_ILEInterrupt Line Enable2070 105Ch2071 105Ch
80hMCAN_GFCGlobal Filter Configuration2070 1080h2071 1080h
84hMCAN_SIDFCStandard ID Filter Configuration2070 1084h2071 1084h
88hMCAN_XIDFCExtended ID Filter Configuration2070 1088h2071 1088h
90hMCAN_XIDAMExtended ID AND Mask2070 1090h2071 1090h
94hMCAN_HPMSHigh Priority Message Status2070 1094h2071 1094h
98hMCAN_NDAT1New Data 12070 1098h2071 1098h
9ChMCAN_NDAT2New Data 22070 109Ch2071 109Ch
A0hMCAN_RXF0CRx FIFO 0 Configuration2070 10A0h2071 10A0h
A4hMCAN_RXF0SRx FIFO 0 Status2070 10A4h2071 10A4h
A8hMCAN_RXF0ARx FIFO 0 Acknowledge2070 10A8h2071 10A8h
AChMCAN_RXBCRx Buffer Configuration2070 10ACh2071 10ACh
B0hMCAN_RXF1CRx FIFO 1 Configuration2070 10B0h2071 10B0h
B4hMCAN_RXF1SRx FIFO 1 Status2070 10B4h2071 10B4h
B8hMCAN_RXF1ARx FIFO 1 Acknowledge2070 10B8h2071 10B8h
BChMCAN_RXESCRx Buffer / FIFO Element Size Configuration2070 10BCh2071 10BCh
C0hMCAN_TXBCTx Buffer Configuration2070 10C0h2071 10C0h
C4hMCAN_TXFQSTx FIFO/Queue Status2070 10C4h2071 10C4h
C8hMCAN_TXESCTx Buffer Element Size Configuration2070 10C8h2071 10C8h
CChMCAN_TXBRPTx Buffer Request Pending2070 10CCh2071 10CCh
D0hMCAN_TXBARTx Buffer Add Request2070 10D0h2071 10D0h
D4hMCAN_TXBCRTx Buffer Cancellation Request2070 10D4h2071 10D4h
D8hMCAN_TXBTOTx Buffer Transmission Occurred2070 10D8h2071 10D8h
DChMCAN_TXBCFTx Buffer Cancellation Finished2070 10DCh2071 10DCh
E0hMCAN_TXBTIETx Buffer Transmission Interrupt Enable2070 10E0h2071 10E0h
E4hMCAN_TXBCIETx Buffer Cancellation Finished Interrupt Enable2070 10E4h2071 10E4h
F0hMCAN_TXEFCTx Event FIFO Configuration2070 10F0h2071 10F0h
F4hMCAN_TXEFSTx Event FIFO Status2070 10F4h2071 10F4h
F8hMCAN_TXEFATx Event FIFO Acknowledge2070 10F8h2071 10F8h

1.5.2.1 MCAN_CREL Register (Offset = 0h) [reset = 32380608h]

MCAN_CREL is shown in Figure 12-2132 and described in Table 12-4142.

Return to Summary Table.

Core Release Register
Release dependent constant (version + date).

Table 12-4141 MCAN_CREL Instances
InstancePhysical Address
MCAN0_CFG2070 1000h
MCAN1_CFG2071 1000h
Figure 12-2132 MCAN_CREL Register
31302928272625242322212019181716
RELSTEPSUBSTEPYEAR
R-3hR-2hR-3hR-8h
1514131211109876543210
MONDAY
R-6hR-8h
LEGEND: R = Read Only; -n = value after reset
Table 12-4142 MCAN_CREL Register Field Descriptions
BitFieldTypeResetDescription
31-28RELR3h

Core Release

One digit, BCD-coded.

27-24STEPR2h

Step of Core Release

One digit, BCD-coded.

23-20SUBSTEPR3h

Sub-step of Core Release

One digit, BCD-coded.

19-16YEARR8h

Time Stamp Year

One digit, BCD-coded.

15-8MONR6h

Time Stamp Month

Two digits, BCD-coded.

7-0DAYR8h

Time Stamp Day

Two digits, BCD-coded.

1.5.2.2 MCAN_ENDN Register (Offset = 4h) [reset = 8765 4321h]

MCAN_ENDN is shown in Figure 12-2133 and described in Table 12-4144.

Return to Summary Table.

Endian Register
Constant 8765 4321h.

Table 12-4143 MCAN_ENDN Instances
InstancePhysical Address
MCAN0_CFG2070 1004h
MCAN1_CFG2071 1004h
Figure 12-2133 MCAN_ENDN Register
313029282726252423222120191817161514131211109876543210
ETV
R-8765 4321h
LEGEND: R = Read Only; -n = value after reset
Table 12-4144 MCAN_ENDN Register Field Descriptions
BitFieldTypeResetDescription
31-0ETVR8765 4321h

Endianness Test Value

The endianness test value is 8765 4321h.

1.5.2.3 MCAN_DBTP Register (Offset = Ch) [reset = A33h]

MCAN_DBTP is shown in Figure 12-2134 and described in Table 12-4146.

Return to Summary Table.

Data Bit Timing & Prescaler Register
Configuration of data phase bit timing, transmitter delay compensation enable.

This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 49 time quanta. The CAN time quantum may be programmed in the range of 1 to 32 MCAN functional clock periods. tq = (MCAN_DBTP[20-16] DBRP + 1) mtq (minimum time quantum = CAN clock period (MCAN functional clock)).

The MCAN_DBTP[12-8] DTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The MCAN_DBTP[7-4] DTSEG2 field is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [MCAN_DBTP[12-8] DTSEG1 + MCAN_DBTP[7-4] DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0000 0A33h configures the MCAN module for a data phase bit rate of 500 kbit/s.

Note: The bit rate configured for the CAN FD data phase via the MCAN_DBTP register must be higher or equal to the bit rate configured for the arbitration phase via the MCAN_DBTP register.

Table 12-4145 MCAN_DBTP Instances
InstancePhysical Address
MCAN0_CFG2070 100Ch
MCAN1_CFG2071 100Ch
Figure 12-2134 MCAN_DBTP Register
3130292827262524
RESERVED
R-0h
2322212019181716
TDCRESERVEDDBRP
R/W-0hR-0hR/W-0h
15141312111098
RESERVEDDTSEG1
R-0hR/W-Ah
76543210
DTSEG2DSJW
R/W-3hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4146 MCAN_DBTP Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23TDCR/W0h

Transmitter Delay Compensation

0h = Transmitter Delay Compensation disabled

1h = Transmitter Delay Compensation enabled

22-21RESERVEDR0h

Reserved

20-16DBRPR/W0h

Data Baud Rate Prescaler

The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta.

Valid values for the Baud Rate Prescaler are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

15-13RESERVEDR0h

Reserved

12-8DTSEG1R/WAh

Data time segment before sample point

Valid values are 0 to 31 (0h-1Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

7-4DTSEG2R/W3h

Data time segment after sample point

Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

3-0DSJWR/W3h

Data (Re)Synchronization Jump Width

Valid values are 0 to 15 (0h-Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

1.5.2.4 MCAN_TEST Register (Offset = 10h) [reset = 0h]

MCAN_TEST is shown in Figure 12-2135 and described in Table 12-4148.

Return to Summary Table.

Test Register
Test mode selection.

Write access to the MCAN_TEST register has to be enabled by setting the MCAN_CCCR[7] TEST bit. All MCAN_TEST register functions are set to their reset values when the MCAN_CCCR[7] TEST bit is reset.

Loopback Mode and software control of the MCAN TX pin are hardware test modes. Programming of the MCAN_TEST[6-5] TX field ≠ 00 may disturb the message transfer on the CAN bus.

Table 12-4147 MCAN_TEST Instances
InstancePhysical Address
MCAN0_CFG2070 1010h
MCAN1_CFG2071 1010h
Figure 12-2135 MCAN_TEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RXTXLBCKRESERVED
R-0hR/W-0hR/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4148 MCAN_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7RXR0h

Receive Pin

Monitors the actual value of the MCAN RX pin

0h = The CAN bus is dominant (MCAN RX = 0h)

1h = The CAN bus is recessive (MCAN RX = 1h)

6-5TXR/W0h

Control of Transmit Pin

0h = Reset value, the MCAN TX pin controlled by the CAN Core, updated at the end of the CAN bit time

1h = Sample Point can be monitored at the MCAN TX pin

2h = Dominant ('0') level at the MCAN TX pin

3h = Recessive ('1') at the MCAN TX pin

4LBCKR/W0h

Loopback Mode

0h = Reset value, Loopback Mode is disabled

1h = Loopback Mode is enabled


(see Test Modes)
3-0RESERVEDR0h

Reserved

1.5.2.5 MCAN_RWD Register (Offset = 14h) [reset = 0h]

MCAN_RWD is shown in Figure 12-2136 and described in Table 12-4150.

RAM Watchdog
Monitors the READY output of the Message RAM.

The RAM Watchdog monitors the READY output of the Message RAM . A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the MCAN_RWD[7-0] WDC field. The counter is reloaded with the MCAN_RWD[7-0] WDC field when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to zero, the counter stops and interrupt flag MCAN_IR[26] WDI is set. The RAM Watchdog Counter is clocked by the Host clock (MCAN interface clock).

Table 12-4149 MCAN_RWD Instances
InstancePhysical Address
MCAN0_CFG2070 1014h
MCAN1_CFG2071 1014h
Figure 12-2136 MCAN_RWD Register
313029282726252423222120191817161514131211109876543210
RESERVEDWDVWDC
R-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4150 MCAN_RWD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15-8WDVR0h

Watchdog Value

Actual Message RAM Watchdog Counter Value.

7-0WDCR/W0h

Watchdog Configuration

Start value of the Message RAM Watchdog Counter. With the reset value of 0h the counter is disabled.

1.5.2.6 MCAN_CCCR Register (Offset = 18h) [reset = 1h]

MCAN_CCCR is shown in Figure 12-2137 and described in Table 12-4152.

Return to Summary Table.

CC Control Register
Operation mode configuration.

For details about setting and resetting of single bits, see Software Initialization.

Table 12-4151 MCAN_CCCR Instances
InstancePhysical Address
MCAN0_CFG2070 1018h
MCAN1_CFG2071 1018h
Figure 12-2137 MCAN_CCCR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NISOTXPEFBIPXHDRESERVEDBRSEFDOE
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
TESTDARMONCSRCSAASMCCEINIT
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4152 MCAN_CCCR Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15NISOR/W0h

Non ISO Operation

0h = CAN FD frame format according to ISO 11898-1:2015.

1h = CAN FD frame format according to Bosch CAN FD Specification 1.0.

14TXPR/W0h

Transmit Pause

If this bit is set, the MCAN module pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame


(see Tx Handling) .

0h = Transmit pause disabled

1h = Transmit pause enabled

13EFBIR/W0h

Edge Filtering during Bus Integration

0h = Edge filtering disabled

1h = Two consecutive dominant tq required to detect an edge for hard synchronization

12PXHDR/W0h

Protocol Exception Handling Disable

0h = Protocol exception handling enabled

1h = Protocol exception handling disabled

Note: When protocol exception handling is disabled, the MCAN module will transmit an error frame when it detects a protocol exception condition.
11-10RESERVEDR0h

Reserved

9BRSER/W0h

Bit Rate Switch Enable

0h = Bit rate switching for transmissions disabled

1h = Bit rate switching for transmissions enabled

Note: When CAN FD operation is disabled the MCAN_CCCR[8] FDOE = 0h, the MCAN_CCCR[9] BRSE bit is not evaluated.
8FDOER/W0h

FD Operation Enable

0h = FD operation disabled

1h = FD operation enabled

7TESTR/W0h

Test Mode Enable

0h = Normal operation. The MCAN_TEST register holds reset values.

1h = Test Mode. Write access to the MCAN_TEST register enabled.

6DARR/W0h

Disable Automatic Retransmission

0h = Automatic retransmission of messages not transmitted successfully enabled

1h = Automatic retransmission disabled

5MONR/W0h

Bus Monitoring Mode

The MCAN_CCCR[5] MON bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time.

0h = Bus Monitoring Mode is disabled

1h = Bus Monitoring Mode is enabled

4CSRR/W0h

Clock Stop Request

0h = No clock stop is requested

1h = Clock stop requested. When clock stop is requested, first the MCAN_CCCR[0] INIT bit and then the MCAN_CCCR[3] CSA bit will be set after all pending transfer requests have been completed and the CAN bus reached idle.

3CSAR0h

Clock Stop Acknowledge

0h = No clock stop acknowledged

1h = The MCAN module may be set in power down by stopping MCAN interface clock and MCAN functional clock

2ASMR/W0h

Restricted Operation Mode

The MCAN_CCCR[2] ASM bit can only be set by the Host CPU when both MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set to 1. The bit can be reset by the Host CPU at any time. For a description of the Restricted Operation Mode, see Restricted Operation Mode.

0h = Normal CAN operation

1h = Restricted Operation Mode active

1CCER/W0h

Configuration Change Enable

0h = The Host CPU has no write access to the protected configuration registers

1h = The Host CPU has write access to the protected configuration registers (while the MCAN_CCCR[0] INIT = 1h)

0INITR/W1h

Initialization

0h = Normal Operation

1h = Initialization is started

Note: Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to the MCAN_CCCR[0] INIT bit can be read back. Therefore the software has to assure that the previous value written to the MCAN_CCCR[0] INIT bit has been accepted by reading the MCAN_CCCR[0] INIT bit before setting the MCAN_CCCR[0] INIT bit to a new value.

1.5.2.7 MCAN_NBTP Register (Offset = 1Ch) [reset = 06000A03h]

MCAN_NBTP is shown in Figure 12-2138 and described in Table 12-4154.

Return to Summary Table.

Nominal Bit Timing & Prescaler Register
Configuration of arbitration phase bit timing.

This register is only writable if the MCAN_CCCR[1] CCE and MCAN_CCCR[0] INIT bits are set. The CAN bit time may be programed in the range of 4 to 385 time quanta. The CAN time quantum may be programmed in the range of 1 to 512 MCAN functional clock periods. tq = (MCAN_NBTP[24-16] NBRP + 1) mtq. The MCAN_NBTP[15-8] NTSEG1 field is the sum of Prop_Seg and Phase_Seg1. The MCAN_NBTP[6-0] NTSEG2 field is Phase_Seg2.

Therefore the length of the bit time is (programmed values) [MCAN_NBTP[15-8] NTSEG1 + MCAN_NBTP[6-0] NTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.

The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Table 12-4153 MCAN_NBTP Instances
InstancePhysical Address
MCAN0_CFG2070 101Ch
MCAN1_CFG2071 101Ch
Figure 12-2138 MCAN_NBTP Register
3130292827262524
NSJWNBRP
R/W-3hR/W-0h
2322212019181716
NBRP
R/W-0h
15141312111098
NTSEG1
R/W-Ah
76543210
RESERVEDNTSEG2
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4154 MCAN_NBTP Register Field Descriptions
BitFieldTypeResetDescription
31-25NSJWR/W3h

Nominal (Re)Synchronization Jump Width

Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

24-16NBRPR/W0h

Nominal Baud Rate Prescaler

The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 511 (0h-1FFh). The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

15-8NTSEG1R/WAh

Nominal Time segment before sample point

Valid values are 1 to 255 (1h-FFh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

7RESERVEDR0h

Reserved

6-0NTSEG2R/W3h

Nominal Time segment after sample point

Valid values are 0 to 127 (0h-7Fh). The actual interpretation by the hardware of this value is such that one more than the programmed value is used.

Note: With a CAN clock (MCAN functional clock) of 8 MHz, the reset value of 0600 0A03h configures the MCAN module for a bit rate of 500 kbit/s.

1.5.2.8 MCAN_TSCC Register (Offset = 20h) [reset = 0h]

MCAN_TSCC is shown in Figure 12-2139 and described in Table 12-4156.

Return to Summary Table.

Timestamp Counter Configuration
Timestamp counter prescaler setting, selection of internal/external timestamp vector.

For a description of the Timestamp Counter, see Timestamp Generation.

Table 12-4155 MCAN_TSCC Instances
InstancePhysical Address
MCAN0_CFG2070 1020h
MCAN1_CFG2071 1020h
Figure 12-2139 MCAN_TSCC Register
31302928272625242322212019181716
RESERVEDTCP
R-0hR/W-0h
1514131211109876543210
RESERVEDTSS
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4156 MCAN_TSCC Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h

Reserved

19-16TCPR/W0h

Timestamp Counter Prescaler

Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1-16 (0h-Fh)]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.

Note: With CAN FD an external counter is required for timestamp generation (MCAN_TSCC[1-0] TSS = 2h)
15-2RESERVEDR0h

Reserved

1-0TSSR/W0h

Timestamp Select

0h = Timestamp counter value always 0h

1h = Timestamp counter value incremented according to the MCAN_TSCC[19-16] TCP field

2h = External timestamp counter value used

3h = Same as 0h

1.5.2.9 MCAN_TSCV Register (Offset = 24h) [reset = 0h]

MCAN_TSCV is shown in Figure 12-2140 and described in Table 12-4158.

Return to Summary Table.

Timestamp Counter Value
Read/reset timestamp counter.

Table 12-4157 MCAN_TSCV Instances
InstancePhysical Address
MCAN0_CFG2070 1024h
MCAN1_CFG2071 1024h
Figure 12-2140 MCAN_TSCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTSC
R-0hRWTC-0h
LEGEND: R = Read Only; RWTC = Read/Write to Clear Field; -n = value after reset
Table 12-4158 MCAN_TSCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15-0TSCRWTC0h

Timestamp Counter

The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).

When the MCAN_TSCC[1-0] TSS = 1h, the Timestamp Counter is incremented in multiples of CAN bit times

[1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. A wrap around sets interrupt flag MCAN_IR[16] TSW.

Write access resets the counter to zero. When the MCAN_TSCC[1-0] TSS = 2h, the MCAN_TSCV[15-0] TSC field reflects the external Timestamp Counter value. A write access has no impact.

Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to the MCAN_TSCV register.

1.5.2.10 MCAN_TOCC Register (Offset = 28h) [reset = FFFF0000h]

MCAN_TOCC is shown in Figure 12-2141 and described in Table 12-4160.

Return to Summary Table.

Timeout Counter Configuration
Configuration of timeout period, selection of timeout counter operation mode.

For a description of the Timeout Counter, see Timeout Counter.

Table 12-4159 MCAN_TOCC Instances
InstancePhysical Address
MCAN0_CFG2070 1028h
MCAN1_CFG2071 1028h
Figure 12-2141 MCAN_TOCC Register
3130292827262524
TOP
R/W-FFFFh
2322212019181716
TOP
R/W-FFFFh
15141312111098
RESERVED
R-0h
76543210
RESERVEDTOSETOC
R-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4160 MCAN_TOCC Register Field Descriptions
BitFieldTypeResetDescription
31-16TOPR/WFFFFh

Timeout Period

Start value of the Timeout Counter (down-counter). Configures the Timeout Period.

15-3RESERVEDR0h

Reserved

2-1TOSR/W0h

Timeout Select

When operating in Continuous mode, a write to the MCAN_TOCV[15-0] TOC field presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by the MCAN_TOCC[31-16] TOP field. Down-counting is started when the first FIFO element is stored.

0h = Continuous operation

1h = Timeout controlled by Tx Event FIFO

2h = Timeout controlled by Rx FIFO 0

3h = Timeout controlled by Rx FIFO 1

0ETOCR/W0h

Enable Timeout Counter

0h = Timeout Counter disabled

1h = Timeout Counter enabled

1.5.2.11 MCAN_TOCV Register (Offset = 2Ch) [reset = FFFFh]

MCAN_TOCV is shown in Figure 12-2142 and described in Table 12-4162.

Return to Summary Table.

Timeout Counter Value
Read/reset timeout counter.

Table 12-4161 MCAN_TOCV Instances
InstancePhysical Address
MCAN0_CFG2070 102Ch
MCAN1_CFG2071 102Ch
Figure 12-2142 MCAN_TOCV Register
313029282726252423222120191817161514131211109876543210
RESERVEDTOC
R-0hRWTC-FFFFh
LEGEND: R = Read Only; RWTC = Read/Write to Clear Field; -n = value after reset
Table 12-4162 MCAN_TOCV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15-0TOCRWTCFFFFh

Timeout Counter

The Timeout Counter is decremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. When decremented to zero, interrupt flag MCAN_IR[18] TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via the MCAN_TOCC[2-1] TOS field.

1.5.2.12 MCAN_ECR Register (Offset = 40h) [reset = 0h]

MCAN_ECR is shown in Figure 12-2143 and described in Table 12-4164.

Return to Summary Table.

Error Counter Register
State of Rx/Tx Error Counter, CAN Error Logging.

Table 12-4163 MCAN_ECR Instances
InstancePhysical Address
MCAN0_CFG2070 1040h
MCAN1_CFG2071 1040h
Figure 12-2143 MCAN_ECR Register
31302928272625242322212019181716
RESERVEDCEL
R-0hR-0h
1514131211109876543210
RPRECTEC
R-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4164 MCAN_ECR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23-16CELR0h

CAN Error Logging

The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh; the next increment of the MCAN_ECR[7-0] TEC or MCAN_ECR[14-8] REC fields sets interrupt flag MCAN_IR[22] ELO.

15RPR0h

Receive Error Passive

0h = The Receive Error Counter is below the error passive level of 128

1h = The Receive Error Counter has reached the error passive level of 128

14-8RECR0h

Receive Error Counter

Actual state of the Receive Error Counter, values between 0 and 127.

7-0TECR0h

Transmit Error Counter

Actual state of the Transmit Error Counter, values between 0 and 255.

Note: When the MCAN_CCCR[2] ASM bit is set, the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN protocol error is detected, but the MCAN_ECR[23-16] CEL field is still incremented.

1.5.2.13 MCAN_PSR Register (Offset = 44h) [reset = 707h]

MCAN_PSR is shown in Figure 12-2144 and described in Table 12-4166.

Return to Summary Table.

Protocol Status Register
CAN protocol controller status, transmitter delay compensation value.

Table 12-4165 MCAN_PSR Instances
InstancePhysical Address
MCAN0_CFG2070 1044h
MCAN1_CFG2071 1044h
Figure 12-2144 MCAN_PSR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTDCV
R-0hR-0h
15141312111098
RESERVEDPXERFDFRBRSRESIDLEC
R-0hR-0hR-0hR-0hR-0hR-7h
76543210
BOEWEPACTLEC
R-0hR-0hR-0hR-0hR-7h
LEGEND: R = Read Only; -n = value after reset
Table 12-4166 MCAN_PSR Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h

Reserved

22-16TDCVR0h

Transmitter Delay Compensation Value

Position of the secondary sample point, defined by the sum of the measured delay from the MCAN TX to MCAN RX pins and the MCAN_TDCR[14-8] TDCO field. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh).

15RESERVEDR0h

Reserved

14PXER0h

Protocol Exception Event

0h = No protocol exception event occurred since last read access

1h = Protocol exception event occurred

13RFDFR0h

Received a CAN FD Message

This bit is set independent of acceptance filtering.

0h = Since this bit was reset by the Host CPU, no CAN FD message has been received

1h = Message in CAN FD format with FDF flag set has been received

12RBRSR0h

BRS flag of last received CAN FD Message

This bit is set together with the MCAN_PSR[13] RFDF bit, independent of acceptance filtering.

0h = Last received CAN FD message did not have its BRS flag set

1h = Last received CAN FD message had its BRS flag set

11RESIR0h

ESI flag of last received CAN FD Message

This bit is set together with the MCAN_PSR[13] RFDF bit, independent of acceptance filtering.

0h = Last received CAN FD message did not have its ESI flag set

1h = Last received CAN FD message had its ESI flag set

10-8DLECR7h

Data Phase Last Error Code

Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.

Coding is the same as for the MCAN_PSR[2-0] LEC field. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.

7BOR0h

Bus_Off Status

0h = The MCAN module is not Bus_Off

1h = The MCAN module is in Bus_Off state

6EWR0h

Warning Status

0h = Both error counters are below the Error_Warning limit of 96

1h = At least one of error counter has reached the Error_Warning limit of 96

5EPR0h

Error Passive

0h = The MCAN module is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected

1h = The MCAN module is in the Error_Passive state

4-3ACTR0h

Activity

Monitors the module's CAN communication state.

0h = Synchronizing - node is synchronizing on CAN communication

1h = Idle - node is neither receiver nor transmitter

2h = Receiver - node is operating as receiver

3h = Transmitter - node is operating as transmitter

Note: ACT is set to 0h by a Protocol Exception Event.
2-0LECR7h

Last Error Code

The MCAN_PSR[2-0] LEC field indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0h when a message has been transferred (reception or transmission) without error.

0h = No Error: No error occurred since the MCAN_PSR[2-0] LEC field has been reset by successful reception or transmission.

1h = Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

2h = Form Error: A fixed format part of a received frame has the wrong format.

3h = AckError: The message transmitted by the MCAN module was not acknowledged by another node.

4h = Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.

5h = Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the Host CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

6h = CRCError: The CRC check sum of a received message was incorrect. The CRC of an incom-ing message does not match with the CRC calculated from the received data.

7h = NoChange: Any read access to the Protocol Status Register re-initializes the MCAN_PSR[2-0] LEC field to 7h. When the MCAN_PSR[2-0] LEC field shows the value 7h, no CAN bus event was detected since the last Host CPU read access to the Protocol Status Register.

Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in the MCAN_PSR[10-8] DLEC field instead of the MCAN_PSR[2-0] LEC field. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error.

1.5.2.14 MCAN_TDCR Register (Offset = 48h) [reset = 0h]

MCAN_TDCR is shown in Figure 12-2145 and described in Table 12-4168.

Return to Summary Table.

Transmitter Delay Comensation Register
Configuration of transmitter delay compensation offset and filter window length.

Table 12-4167 MCAN_TDCR Instances
InstancePhysical Address
MCAN0_CFG2070 1048h
MCAN1_CFG2071 1048h
Figure 12-2145 MCAN_TDCR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTDCO
R-0hR/W-0h
76543210
RESERVEDTDCF
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4168 MCAN_TDCR Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h

Reserved

14-8TDCOR/W0h

Transmitter Delay Compensation Offset

Offset value defining the distance between the measured delay from the MCAN RX and MCAN TX pins and the secondary sample point. Valid values are 0 to 127 mtq (0h-7Fh).

7RESERVEDR0h

Reserved

6-0TDCFR/W0h

Transmitter Delay Compensation Filter Window Length

Defines the minimum value for the SSP position, dominant edges on the MCAN RX pin that would result in an earlier SSP position are ignored for transmitter delay measure-ment. The feature is enabled when the MCAN_TDCR[6-0] TDCF field is configured to a value greater than the MCAN_TDCR[14-8] TDCO field. Valid values are 0 to 127 mtq (0h-7Fh).

1.5.2.15 MCAN_IR Register (Offset = 50h) [reset = 0h]

MCAN_IR is shown in Figure 12-2146 and described in Table 12-4170.

Return to Summary Table.

Interrupt Register

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register. The configuration of the MCAN_IE register controls whether an interrupt is generated. The configuration of the MCAN_ILS register controls on which interrupt line an interrupt is signalled.

Table 12-4169 MCAN_IR Instances
InstancePhysical Address
MCAN0_CFG2070 1050h
MCAN1_CFG2071 1050h
Figure 12-2146 MCAN_IR Register
3130292827262524
RESERVEDARAPEDPEAWDIBOEW
R-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
2322212019181716
EPELOBEURESERVEDDRXTOOMRAFTSW
RW1TC-0hRW1TC-0hRW1TC-0hR-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
15141312111098
TEFLTEFFTEFWTEFNTFETCFTCHPM
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
76543210
RF1LRF1FRF1WRF1NRF0LRF0FRF0WRF0N
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
LEGEND: R = Read Only; RW1TC = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4170 MCAN_IR Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29ARARW1TC0h

Access to Reserved Address

0h = No access to reserved address occurred

1h = Access to reserved address occurred

28PEDRW1TC0h

Protocol Error in Data Phase

0h = No protocol error in data phase

1h = Protocol error in data phase detected (MCAN_PSR[10-8] DLEC ≠ 0.7)

27PEARW1TC0h

Protocol Error in Arbitration Phase

0h = No protocol error in arbitration phase

1h = Protocol error in arbitration phase detected (MCAN_PSR[2-0] LEC ≠ 0.7)

26WDIRW1TC0h

Watchdog Interrupt

0h = No Message RAM Watchdog event occurred

1h = Message RAM Watchdog event due to missing READY

25BORW1TC0h

Bus_Off Status

0h = Bus_Off status unchanged

1h = Bus_Off status changed

24EWRW1TC0h

Warning Status

0h = Error_Warning status unchanged

1h = Error_Warning status changed

23EPRW1TC0h

Error Passive

0h = Error_Passive status unchanged

1h = Error_Passive status changed

22ELORW1TC0h

Error Logging Overflow

0h = CAN Error Logging Counter did not overflow

1h = Overflow of CAN Error Logging Counter occurred

21BEURW1TC0h

Bit Error Uncorrected

Message RAM bit error detected, uncorrected. Controlled by input signal generated by parity/ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets the MCAN_CCCR[0] INIT bit to 1. This is done to avoid transmission of corrupted data.

0h = No bit error detected when reading from Message RAM

1h = Bit error detected, uncorrected (example: parity logic)

20RESERVEDR0h

Reserved

19DRXRW1TC0h

Message stored to Dedicated Rx Buffer

The flag is set whenever a received message has been stored into a dedicated Rx Buffer.

0h = No Rx Buffer updated

1h = At least one received message stored into an Rx Buffer

18TOORW1TC0h

Timeout Occurred

0h = No timeout

1h = Timeout reached

17MRAFRW1TC0h

Message RAM Access Failure

The flag is set, when the Rx Handler:

a) has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.

b) was not able to write a message to the Message RAM. In this case message storage is aborted.

In both cases the FIFO put index is not updated respectively the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.

The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the MCAN module is switched into Restricted Operation Mode (see Restricted Operation Mode). To leave Restricted Operation Mode, the Host CPU has to reset the MCAN_CCCR[2] ASM bit.

0h = No Message RAM access failure occurred

1h = Message RAM access failure occurred

16TSWRW1TC0h

Timestamp Wraparound

0h = No timestamp counter wrap-around

1h = Timestamp counter wrapped around

15TEFLRW1TC0h

Tx Event FIFO Element Lost

0h = No Tx Event FIFO element lost

1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero

14TEFFRW1TC0h

Tx Event FIFO Full

0h = Tx Event FIFO not full

1h = Tx Event FIFO full

13TEFWRW1TC0h

Tx Event FIFO Watermark Reached

0h = Tx Event FIFO fill level below watermark

1h = Tx Event FIFO fill level reached watermark

12TEFNRW1TC0h

Tx Event FIFO New Entry

0h = Tx Event FIFO unchanged

1h = Tx Handler wrote Tx Event FIFO element

11TFERW1TC0h

Tx FIFO Empty

0h = Tx FIFO non-empty

1h = Tx FIFO empty

10TCFRW1TC0h

Transmission Cancellation Finished

0h = No transmission cancellation finished

1h = Transmission cancellation finished

9TCRW1TC0h

Transmission Completed

0h = No transmission completed

1h = Transmission completed

8HPMRW1TC0h

High Priority Message

0h = No high priority message received

1h = High priority message received

7RF1LRW1TC0h

Rx FIFO 1 Message Lost

0h = No Rx FIFO 1 message lost

1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

6RF1FRW1TC0h

Rx FIFO 1 Full

0h = Rx FIFO 1 not full

1h = Rx FIFO 1 full

5RF1WRW1TC0h

Rx FIFO 1 Watermark Reached

0h = Rx FIFO 1 fill level below watermark

1h = Rx FIFO 1 fill level reached watermark

4RF1NRW1TC0h

Rx FIFO 1 New Message

0h = No new message written to Rx FIFO 1

1h = New message written to Rx FIFO 1

3RF0LRW1TC0h

Rx FIFO 0 Message Lost

0h = No Rx FIFO 0 message lost

1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

2RF0FRW1TC0h

Rx FIFO 0 Full

0h = Rx FIFO 0 not full

1h = Rx FIFO 0 full

1RF0WRW1TC0h

Rx FIFO 0 Watermark Reached

0h = Rx FIFO 0 fill level below watermark

1h = Rx FIFO 0 fill level reached watermark

0RF0NRW1TC0h

Rx FIFO 0 New Message

0h = No new message written to Rx FIFO 0

1h = New message written to Rx FIFO 0

1.5.2.16 MCAN_IE Register (Offset = 54h) [reset = 0h]

MCAN_IE is shown in Figure 12-2147 and described in Table 12-4172.

Return to Summary Table.

Interrupt Enable

The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line.

Table 12-4171 MCAN_IE Instances
InstancePhysical Address
MCAN0_CFG2070 1054h
MCAN1_CFG2071 1054h
Figure 12-2147 MCAN_IE Register
3130292827262524
RESERVEDARAEPEDEPEAEWDIEBOEEWE
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPEELOEBEUEBECEDRXTOOEMRAFETSWE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLETEFFETEFWETEFNETFEETCFETCEHPME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LERF1FERF1WERF1NERF0LERF0FERF0WERF0NE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4172 MCAN_IE Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29ARAER/W0h

Access to Reserved Address Enable

0h = Interrupt disabled

1h = Interrupt enabled

28PEDER/W0h

Protocol Error in Data Phase Enable

0h = Interrupt disabled

1h = Interrupt enabled

27PEAER/W0h

Protocol Error in Arbitration Phase Enable

0h = Interrupt disabled

1h = Interrupt enabled

26WDIER/W0h

Watchdog Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

25BOER/W0h

Bus_Off Status Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

24EWER/W0h

Warning Status Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

23EPER/W0h

Error Passive Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

22ELOER/W0h

Error Logging Overflow Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

21BEUER/W0h

Bit Error Uncorrected Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

20BECER/W0h

Bit Error Corrected Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

19DRXR/W0h

Message stored to Dedicated Rx Buffer Interrupt Enable

18TOOER/W0h

Timeout Occurred Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

17MRAFER/W0h

Message RAM Access Failure Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

16TSWER/W0h

Timestamp Wraparound Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

15TEFLER/W0h

Tx Event FIFO Event Lost Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

14TEFFER/W0h

Tx Event FIFO Full Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

13TEFWER/W0h

Tx Event FIFO Watermark Reached Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

12TEFNER/W0h

Tx Event FIFO New Entry Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

11TFEER/W0h

Tx FIFO Empty Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

10TCFER/W0h

Transmission Cancellation Finished Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

9TCER/W0h

Transmission Completed Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

8HPMER/W0h

High Priority Message Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

7RF1LER/W0h

Rx FIFO 1 Message Lost Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

6RF1FER/W0h

Rx FIFO 1 Full Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

5RF1WER/W0h

Rx FIFO 1 Watermark Reached Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

4RF1NER/W0h

Rx FIFO 1 New Message Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

3RF0LER/W0h

Rx FIFO 0 Message Lost Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

2RF0FER/W0h

Rx FIFO 0 Full Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

1RF0WER/W0h

Rx FIFO 0 Watermark Reached Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

0RF0NER/W0h

Rx FIFO 0 New Message Interrupt Enable

0h = Interrupt disabled

1h = Interrupt enabled

1.5.2.17 MCAN_ILS Register (Offset = 58h) [reset = 0h]

MCAN_ILS is shown in Figure 12-2148 and described in Table 12-4174.

Return to Summary Table.

Interrupt Line Select

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the MCAN_IR register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via the MCAN_ILE[0] EINT0 and MCAN_ILE[1] EINT1 bits.

Table 12-4173 MCAN_ILS Instances
InstancePhysical Address
MCAN0_CFG2070 1058h
MCAN1_CFG2071 1058h
Figure 12-2148 MCAN_ILS Register
3130292827262524
RESERVEDARALPEDLPEALWDILBOLEWL
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
EPLELOLBEULBECLDRXLTOOLMRAFLTSWL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TEFLLTEFFLTEFWLTEFNLTFELTCFLTCLHPML
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RF1LLRF1FLRF1WLRF1NLRF0LLRF0FLRF0WLRF0NL
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4174 MCAN_ILS Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29ARALR/W0h

Access to Reserved Address Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

28PEDLR/W0h

Protocol Error in Data Phase Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

27PEALR/W0h

Protocol Error in Arbitration Phase Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

26WDILR/W0h

Watchdog Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

25BOLR/W0h

Bus_Off Status Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

24EWLR/W0h

Warning Status Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

23EPLR/W0h

Error Passive Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

22ELOLR/W0h

Error Logging Overflow Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

21BEULR/W0h

Bit Error Uncorrected Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

20BECLR/W0h

Bit Error Corrected Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

19DRXLR/W0h

Message stored to Dedicated Rx Buffer Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

18TOOLR/W0h

Timeout Occurred Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

17MRAFLR/W0h

Message RAM Access Failure Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

16TSWLR/W0h

Timestamp Wraparound Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

15TEFLLR/W0h

Tx Event FIFO Event Lost Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

14TEFFLR/W0h

Tx Event FIFO Full Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

13TEFWLR/W0h

Tx Event FIFO Watermark Reached Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

12TEFNLR/W0h

Tx Event FIFO New Entry Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

11TFELR/W0h

Tx FIFO Empty Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

10TCFLR/W0h

Transmission Cancellation Finished Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

9TCLR/W0h

Transmission Completed Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

8HPMLR/W0h

High Priority Message Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

7RF1LLR/W0h

Rx FIFO 1 Message Lost Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

6RF1FLR/W0h

Rx FIFO 1 Full Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

5RF1WLR/W0h

Rx FIFO 1 Watermark Reached Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

4RF1NLR/W0h

Rx FIFO 1 New Message Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

3RF0LLR/W0h

Rx FIFO 0 Message Lost Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

2RF0FLR/W0h

Rx FIFO 0 Full Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

1RF0WLR/W0h

Rx FIFO 0 Watermark Reached Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

0RF0NLR/W0h

Rx FIFO 0 New Message Interrupt Line

0h = Interrupt assigned to interrupt line INT0

1h = Interrupt assigned to interrupt line INT1

1.5.2.18 MCAN_ILE Register (Offset = 5Ch) [reset = 0h]

MCAN_ILE is shown in Figure 12-2149 and described in Table 12-4176.

Return to Summary Table.

Interrupt Line Enable
Enable/disable interrupt lines INT0/INT1.

Each of the two interrupt lines to the Host CPU can be enabled/disabled separately by programming the MCAN_ILE[0] EINT0 and MCAN_ILE[1] EINT1 bits.

Table 12-4175 MCAN_ILE Instances
InstancePhysical Address
MCAN0_CFG2070 105Ch
MCAN1_CFG2071 105Ch
Figure 12-2149 MCAN_ILE Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEINT1EINT0
R-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4176 MCAN_ILE Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1EINT1R/W0h

Enable Interrupt Line 1

0h = Interrupt line INT1 disabled

1h = Interrupt line INT1 enabled

0EINT0R/W0h

Enable Interrupt Line 0

0h = Interrupt line INT0 disabled

1h = Interrupt line INT0 enabled

1.5.2.19 MCAN_GFC Register (Offset = 80h) [reset = 0h]

MCAN_GFC is shown in Figure 12-2150 and described in Table 12-4178.

Return to Summary Table.

Global Filter Configuration
Handling of non-matching frames and remote frames.

Global settings for Message ID filtering. The MCAN_GFC register controls the filter path for standard and extended messages (see Figure 12-2109 and Figure 12-2110).

Table 12-4177 MCAN_GFC Instances
InstancePhysical Address
MCAN0_CFG2070 1080h
MCAN1_CFG2071 1080h
Figure 12-2150 MCAN_GFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDANFSANFERRFSRRFE
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4178 MCAN_GFC Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-4ANFSR/W0h

Accept Non-matching Frames Standard

Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated.

0h = Accept in Rx FIFO 0

1h = Accept in Rx FIFO 1

2h = Reject

3h = Reject

3-2ANFER/W0h

Accept Non-matching Frames Extended

Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated.

0h = Accept in Rx FIFO 0

1h = Accept in Rx FIFO 1

2h = Reject

3h = Reject

1RRFSR/W0h

Reject Remote Frames Standard

0h = Filter remote frames with 11-bit standard IDs

1h = Reject all remote frames with 11-bit standard IDs

0RRFER/W0h

Reject Remote Frames Extended

0h = Filter remote frames with 29-bit extended IDs

1h = Reject all remote frames with 29-bit extended IDs

1.5.2.20 MCAN_SIDFC Register (Offset = 84h) [reset = 0h]

MCAN_SIDFC is shown in Figure 12-2151 and described in Table 12-4180.

Return to Summary Table.

Standard ID Filter Configuration
Number of filter elements, pointer to start of filter list.

Settings for 11-bit standard Message ID filtering. The Standard ID Filter Configuration controls the filter path for standard messages (see Figure 12-2109).

Table 12-4179 MCAN_SIDFC Instances
InstancePhysical Address
MCAN0_CFG2070 1084h
MCAN1_CFG2071 1084h
Figure 12-2151 MCAN_SIDFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
LSS
R/W-0h
15141312111098
FLSSA
R/W-0h
76543210
FLSSARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4180 MCAN_SIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23-16LSSR/W0h

List Size Standard

0h = No standard Message ID filter

1h-80h (1-128) = Number of standard Message ID filter elements

> 80h (128) = Values greater than 128 are interpreted as 128

15-2FLSSAR/W0h

Filter List Standard Start Address

Start address of standard Message ID filter list (32-bit word address, see Message RAM Configuration).

1-0RESERVEDR0h

Reserved

1.5.2.21 MCAN_XIDFC Register (Offset = 88h) [reset = 0h]

MCAN_XIDFC is shown in Figure 12-2152 and described in Table 12-4182.

Return to Summary Table.

Extended ID Filter Configuration
Number of filter elements, pointer to start of filter list.

Settings for 29-bit extended Message ID filtering. The Extended ID Filter Configuration controls the filter path for standard messages (see Figure 12-2110).

Table 12-4181 MCAN_XIDFC Instances
InstancePhysical Address
MCAN0_CFG2070 1088h
MCAN1_CFG2071 1088h
Figure 12-2152 MCAN_XIDFC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLSE
R-0hR/W-0h
15141312111098
FLESA
R/W-0h
76543210
FLESARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4182 MCAN_XIDFC Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0h

Reserved

22-16LSER/W0h

List Size Extended

0h = No extended Message ID filter

1h-40h (1-64) = Number of extended Message ID filter elements

> 40h (64) = Values greater than 64 are interpreted as 64

15-2FLESAR/W0h

Filter List Extended Start Address

Start address of extended Message ID filter list (32-bit word address, see Message RAM Configuration).

1-0RESERVEDR0h

Reserved

1.5.2.22 MCAN_XIDAM Register (Offset = 90h) [reset = 1FFFFFFFh]

MCAN_XIDAM is shown in Figure 12-2153 and described in Table 12-4184.

Return to Summary Table.

Extended ID AND Mask
29-bit logical AND mask for J1939.

Table 12-4183 MCAN_XIDAM Instances
InstancePhysical Address
MCAN0_CFG2070 1090h
MCAN1_CFG2071 1090h
Figure 12-2153 MCAN_XIDAM Register
31302928272625242322212019181716
RESERVEDEIDM
R-0hR/W-1FFFFFFFh
1514131211109876543210
EIDM
R/W-1FFFFFFFh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4184 MCAN_XIDAM Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h

Reserved

28-0EIDMR/W1FFFFFFFh

Extended ID Mask

For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active.

1.5.2.23 MCAN_HPMS Register (Offset = 94h) [reset = 0h]

MCAN_HPMS is shown in Figure 12-2154 and described in Table 12-4186.

Return to Summary Table.

High Priority Message Status
Status monitoring of incoming high priority messages.

This register is updated every time a Message ID filter element configured to generate a priority event matches. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Table 12-4185 MCAN_HPMS Instances
InstancePhysical Address
MCAN0_CFG2070 1094h
MCAN1_CFG2071 1094h
Figure 12-2154 MCAN_HPMS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
FLSTFIDX
R-0hR-0h
76543210
MSIBIDX
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4186 MCAN_HPMS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15FLSTR0h

Filter List

Indicates the filter list of the matching filter element.

0h = Standard Filter List

1h = Extended Filter List

14-8FIDXR0h

Filter Index

Index of matching filter element. Range is 0 to MCAN_SIDFC[23-16] LSS - 1 respectively MCAN_XIDFC[22-16] LSE - 1.

7-6MSIR0h

Message Storage Indicator

0h = No FIFO selected

1h = FIFO message lost

2h = Message stored in FIFO 0

3h = Message stored in FIFO 1

5-0BIDXR0h

Buffer Index

Index of Rx FIFO element to which the message was stored. Only valid when the MCAN_HPMS[7-6] MSI = 1h.

1.5.2.24 MCAN_NDAT1 Register (Offset = 98h) [reset = 0h]

MCAN_NDAT1 is shown in Figure 12-2155 and described in Table 12-4188.

Return to Summary Table.

New Data 1
NewDat flags of dedicated Rx buffers 0-31.

The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. Aflag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register.

Table 12-4187 MCAN_NDAT1 Instances
InstancePhysical Address
MCAN0_CFG2070 1098h
MCAN1_CFG2071 1098h
Figure 12-2155 MCAN_NDAT1 Register
3130292827262524
ND31ND30ND29ND28ND27ND26ND25ND24
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
2322212019181716
ND23ND22ND21ND20ND19ND18ND17ND16
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
15141312111098
ND15ND14ND13ND12ND11ND10ND9ND8
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
76543210
ND7ND6ND5ND4ND3ND2ND1ND0
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4188 MCAN_NDAT1 Register Field Descriptions
BitFieldTypeResetDescription
31ND31RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

30ND30RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

29ND29RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

28ND28RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

27ND27RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

26ND26RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

25ND25RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

24ND24RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

23ND23RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

22ND22RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

21ND21RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

20ND20RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

19ND19RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

18ND18RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

17ND17RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

16ND16RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

15ND15RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

14ND14RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

13ND13RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

12ND12RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

11ND11RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

10ND10RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

9ND9RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

8ND8RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

7ND7RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

6ND6RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

5ND5RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

4ND4RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

3ND3RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

2ND2RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

1ND1RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

0ND0RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

1.5.2.25 MCAN_NDAT2 Register (Offset = 9Ch) [reset = 0h]

MCAN_NDAT2 is shown in Figure 12-2156 and described in Table 12-4190.

Return to Summary Table.

New Data 2
NewDat flags of dedicated Rx buffers 32-63.

The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host CPU clears them. A flag is cleared by writing a 1h to the corresponding bit position. Writing a 0h has no effect. A hard reset will clear the register.

Table 12-4189 MCAN_NDAT2 Instances
InstancePhysical Address
MCAN0_CFG2070 109Ch
MCAN1_CFG2071 109Ch
Figure 12-2156 MCAN_NDAT2 Register
3130292827262524
ND63ND62ND61ND60ND59ND58ND57ND56
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
2322212019181716
ND55ND54ND53ND52ND51ND50ND49ND48
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
15141312111098
ND47ND46ND45ND44ND43ND42ND41ND40
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
76543210
ND39ND38ND37ND36ND35ND34ND33ND32
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4190 MCAN_NDAT2 Register Field Descriptions
BitFieldTypeResetDescription
31ND63RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

30ND62RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

29ND61RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

28ND60RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

27ND59RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

26ND58RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

25ND57RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

24ND56RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

23ND55RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

22ND54RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

21ND53RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

20ND52RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

19ND51RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

18ND50RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

17ND49RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

16ND48RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

15ND47RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

14ND46RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

13ND45RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

12ND44RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

11ND43RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

10ND42RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

9ND41RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

8ND40RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

7ND39RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

6ND38RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

5ND37RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

4ND36RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

3ND35RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

2ND34RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

1ND33RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

0ND32RW1TC0h

New Data

0h = Rx Buffer not updated

1h = Rx Buffer updated from new message

1.5.2.26 MCAN_RXF0C Register (Offset = A0h) [reset = 0h]

MCAN_RXF0C is shown in Figure 12-2157 and described in Table 12-4192.

Return to Summary Table.

Rx FIFO 0 Configuration
FIFO 0 operation mode, watermark, size and start address.

Table 12-4191 MCAN_RXF0C Instances
InstancePhysical Address
MCAN0_CFG2070 10A0h
MCAN1_CFG2071 10A0h
Figure 12-2157 MCAN_RXF0C Register
3130292827262524
F0OMF0WM
R/W-0hR/W-0h
2322212019181716
RESERVEDF0S
R-0hR/W-0h
15141312111098
F0SA
R/W-0h
76543210
F0SARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4192 MCAN_RXF0C Register Field Descriptions
BitFieldTypeResetDescription
31F0OMR/W0h

FIFO 0 Operation Mode

FIFO 0 can be operated in blocking or in overwrite mode (see Rx FIFOs).

0h = FIFO 0 blocking mode

1h = FIFO 0 overwrite mode

30-24F0WMR/W0h

Rx FIFO 0 Watermark

0h = Watermark interrupt disabled

1h-40h (1-64) = Level for Rx FIFO 0 watermark interrupt (MCAN_IR[1] RF0W)

> 40h (64) = Watermark interrupt disabled

23RESERVEDR0h

Reserved

22-16F0SR/W0h

Rx FIFO 0 Size

0h = No Rx FIFO 0

1h-40h (1-64) = Number of Rx FIFO 0 elements

> 40h (64) = Values greater than 64 are interpreted as 64

The Rx FIFO 0 elements are indexed from 0 to MCAN_RXF0C[22-16] F0S - 1.

15-2F0SAR/W0h

Rx FIFO 0 Start Address

Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Message RAM Configuration).

1-0RESERVEDR0h

Reserved

1.5.2.27 MCAN_RXF0S Register (Offset = A4h) [reset = 0h]

MCAN_RXF0S is shown in Figure 12-2158 and described in Table 12-4194.

Return to Summary Table.

Rx FIFO 0 Status
FIFO 0 message lost/full indication, put index, get index and fill level.

Table 12-4193 MCAN_RXF0S Instances
InstancePhysical Address
MCAN0_CFG2070 10A4h
MCAN1_CFG2071 10A4h
Figure 12-2158 MCAN_RXF0S Register
3130292827262524
RESERVEDRF0LF0F
R-0hR-0hR-0h
2322212019181716
RESERVEDF0PI
R-0hR-0h
15141312111098
RESERVEDF0GI
R-0hR-0h
76543210
RESERVEDF0FL
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4194 MCAN_RXF0S Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h

Reserved

25RF0LR0h

Rx FIFO 0 Message Lost

This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset, this bit is also reset.

0h = No Rx FIFO 0 message lost

1h = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero

Note: Overwriting the oldest message when the MCAN_RXF0C[31] F0OM = 1h will not set this flag.
24F0FR0h

Rx FIFO 0 Full

0h = Rx FIFO 0 not full

1h = Rx FIFO 0 full

23-22RESERVEDR0h

Reserved

21-16F0PIR0h

Rx FIFO 0 Put Index

Rx FIFO 0 write index pointer, range 0 to 63.

15-14RESERVEDR0h

Reserved

13-8F0GIR0h

Rx FIFO 0 Get Index

Rx FIFO 0 read index pointer, range 0 to 63.

7RESERVEDR0h

Reserved

6-0F0FLR0h

Rx FIFO 0 Fill Level

Number of elements stored in Rx FIFO 0, range 0 to 64.

1.5.2.28 MCAN_RXF0A Register (Offset = A8h) [reset = 0h]

MCAN_RXF0A is shown in Figure 12-2159 and described in Table 12-4196.

Return to Summary Table.

Rx FIFO 0 Acknowledge
FIFO 0 acknowledge last index of read buffers, updates get index and fill level.

Table 12-4195 MCAN_RXF0A Instances
InstancePhysical Address
MCAN0_CFG2070 10A8h
MCAN1_CFG2071 10A8h
Figure 12-2159 MCAN_RXF0A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF0AI
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4196 MCAN_RXF0A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0F0AIR/W0h

Rx FIFO 0 Acknowledge Index

After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get Index MCAN_RXF0S[13-8] F0GI field to the MCAN_RXF0A[5-0] F0AI field + 1 and update the FIFO 0 Fill Level MCAN_RXF0S[6-0] F0FL field.

1.5.2.29 MCAN_RXBC Register (Offset = ACh) [reset = 0h]

MCAN_RXBC is shown in Figure 12-2160 and described in Table 12-4198.

Return to Summary Table.

Rx Buffer Configuration
Start address of Rx buffer section.

Table 12-4197 MCAN_RXBC Instances
InstancePhysical Address
MCAN0_CFG2070 10ACh
MCAN1_CFG2071 10ACh
Figure 12-2160 MCAN_RXBC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RBSA
R/W-0h
76543210
RBSARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4198 MCAN_RXBC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15-2RBSAR/W0h

Rx Buffer Start Address

Configures the start address of the Rx Buffers section in the Message RAM


(32-bit word address, see Figure 12-2115).

Also used to reference debug messages A, B, C.

Note: Debug feature is not supported.
1-0RESERVEDR0h

Reserved

1.5.2.30 MCAN_RXF1C Register (Offset = B0h) [reset = 0h]

MCAN_RXF1C is shown in Figure 12-2161 and described in Table 12-4200.

Return to Summary Table.

Rx FIFO 1 Configuration
FIFO 1 operation mode, watermark, size and start address.

Table 12-4199 MCAN_RXF1C Instances
InstancePhysical Address
MCAN0_CFG2070 10B0h
MCAN1_CFG2071 10B0h
Figure 12-2161 MCAN_RXF1C Register
3130292827262524
F1OMF1WM
R/W-0hR/W-0h
2322212019181716
RESERVEDF1S
R-0hR/W-0h
15141312111098
F1SA
R/W-0h
76543210
F1SARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4200 MCAN_RXF1C Register Field Descriptions
BitFieldTypeResetDescription
31F1OMR/W0h

FIFO 1 Operation Mode

FIFO 1 can be operated in blocking or in overwrite mode (see Rx FIFOs).

0h = FIFO 1 blocking mode

1h = FIFO 1 overwrite mode

30-24F1WMR/W0h

Rx FIFO 1 Watermark

0h = Watermark interrupt disabled

1h-40h (1-64) = Level for Rx FIFO 1 watermark interrupt (MCAN_IR[5] RF1W)

> 40h (64) = Watermark interrupt disabled

23RESERVEDR0h

Reserved

22-16F1SR/W0h

Rx FIFO 1 Size

0h = No Rx FIFO 1

1h-40h (1-64) = Number of Rx FIFO 1 elements

> 40h (64) = Values greater than 64 are interpreted as 64

The Rx FIFO 1 elements are indexed from 0 to MCAN_RXF1C[22-16] F1S - 1.

15-2F1SAR/W0h

Rx FIFO 1 Start Address

Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Message RAM Configuration).

1-0RESERVEDR0h

Reserved

1.5.2.31 MCAN_RXF1S Register (Offset = B4h) [reset = 0h]

MCAN_RXF1S is shown in Figure 12-2162 and described in Table 12-4202.

Return to Summary Table.

Rx FIFO 1 Status
FIFO 1 message lost/full indication, put index, get index and fill level.

Table 12-4201 MCAN_RXF1S Instances
InstancePhysical Address
MCAN0_CFG2070 10B4h
MCAN1_CFG2071 10B4h
Figure 12-2162 MCAN_RXF1S Register
3130292827262524
DMSRESERVEDRF1LF1F
R-0hR-0hR-0hR-0h
2322212019181716
RESERVEDF1PI
R-0hR-0h
15141312111098
RESERVEDF1GI
R-0hR-0h
76543210
RESERVEDF1FL
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4202 MCAN_RXF1S Register Field Descriptions
BitFieldTypeResetDescription
31-30DMSR0h

Debug Message Status

0h = Idle state, wait for reception of debug messages, DMA request is cleared

1h = Debug message A received

2h = Debug messages A, B received

3h = Debug messages A, B, C received, DMA request is set

Note: Debug feature is not supported.
29-26RESERVEDR0h

Reserved

25RF1LR0h

Rx FIFO 1 Message Lost

This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset, this bit is also reset.

0h = No Rx FIFO 1 message lost

1h = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero

Note: Overwriting the oldest message when the MCAN_RXF1C[31] F1OM = 1h will not set this flag.
24F1FR0h

Rx FIFO 1 Full

0h = Rx FIFO 1 not full

1h = Rx FIFO 1 full

23-22RESERVEDR0h

Reserved

21-16F1PIR0h

Rx FIFO 1 Put Index

Rx FIFO 1 write index pointer, range 0 to 63.

15-14RESERVEDR0h

Reserved

13-8F1GIR0h

Rx FIFO 1 Get Index

Rx FIFO 1 read index pointer, range 0 to 63.

7RESERVEDR0h

Reserved

6-0F1FLR0h

Rx FIFO 1 Fill Level

Number of elements stored in Rx FIFO 1, range 0 to 64.

1.5.2.32 MCAN_RXF1A Register (Offset = B8h) [reset = 0h]

MCAN_RXF1A is shown in Figure 12-2163 and described in Table 12-4204.

Return to Summary Table.

Rx FIFO 1 Acknowledge
FIFO 1 acknowledge last index of read buffers, updates get index and fill level.

Table 12-4203 MCAN_RXF1A Instances
InstancePhysical Address
MCAN0_CFG2070 10B8h
MCAN1_CFG2071 10B8h
Figure 12-2163 MCAN_RXF1A Register
313029282726252423222120191817161514131211109876543210
RESERVEDF1AI
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4204 MCAN_RXF1A Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0F1AIR/W0h

Rx FIFO 1 Acknowledge Index

After the Host CPU has read a message or a sequence of messages from Rx FIFO 1 it has to write the

buffer index of the last element read from Rx FIFO 1 to the MCAN_RXF1A[5-0] F1AI field. This will set the Rx FIFO 1 Get Index MCAN_RXF1S[13-8] F1GI field to the MCAN_RXF1A[5-0] F1AI field + 1 and update the FIFO 1 Fill Level MCAN_RXF1S[6-0] F1FL field.

1.5.2.33 MCAN_RXESC Register (Offset = BCh) [reset = 0h]

MCAN_RXESC is shown in Figure 12-2164 and described in Table 12-4206.

Return to Summary Table.

Rx Buffer/FIFO Element Size Configuration
Configure data field size for storage of accepted frames.

Table 12-4205 MCAN_RXESC Instances
InstancePhysical Address
MCAN0_CFG2070 10BCh
MCAN1_CFG2071 10BCh
Figure 12-2164 MCAN_RXESC Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRBDS
R-0hR/W-0h
76543210
RESERVEDF1DSRESERVEDF0DS
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4206 MCAN_RXESC Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h

Reserved

10-8RBDSR/W0h

Rx Buffer Data Field Size

0h = 8 byte data field

1h = 12 byte data field

2h = 16 byte data field

3h = 20 byte data field

4h = 24 byte data field

5h = 32 byte data field

6h = 48 byte data field

7h = 64 byte data field

7RESERVEDR0h

Reserved

6-4F1DSR/W0h

Rx FIFO 1 Data Field Size

0h = 8 byte data field

1h = 12 byte data field

2h = 16 byte data field

3h = 20 byte data field

4h = 24 byte data field

5h = 32 byte data field

6h = 48 byte data field

7h = 64 byte data field

3RESERVEDR0h

Reserved

2-0F0DSR/W0h

Rx FIFO 0 Data Field Size

0h = 8 byte data field

1h = 12 byte data field

2h = 16 byte data field

3h = 20 byte data field

4h = 24 byte data field

5h = 32 byte data field

6h = 48 byte data field

7h = 64 byte data field

Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by the MCAN_RXESC register are stored to the Rx Buffer respectively Rx FIFO element. The rest of the frame's data field is ignored.

1.5.2.34 MCAN_TXBC Register (Offset = C0h) [reset = 0h]

MCAN_TXBC is shown in Figure 12-2165 and described in Table 12-4208.

Return to Summary Table.

Tx Buffer Configuration
Configure Tx FIFO/Queue mode, Tx FIFO/Queue size, number of dedicated Tx buffers, Tx buffer start address.

Table 12-4207 MCAN_TXBC Instances
InstancePhysical Address
MCAN0_CFG2070 10C0h
MCAN1_CFG2071 10C0h
Figure 12-2165 MCAN_TXBC Register
3130292827262524
RESERVEDTFQMTFQS
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDNDTB
R-0hR/W-0h
15141312111098
TBSA
R/W-0h
76543210
TBSARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4208 MCAN_TXBC Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h

Reserved

30TFQMR/W0h

Tx FIFO/Queue Mode

0h = Tx FIFO operation

1h = Tx Queue operation

29-24TFQSR/W0h

Transmit FIFO/Queue Size

0h = No Tx FIFO/Queue

1h-20h (1-32) = Number of Tx Buffers used for Tx FIFO/Queue

> 20h (32) = Values greater than 32 are interpreted as 32

23-22RESERVEDR0h

Reserved

21-16NDTBR/W0h

Number of Dedicated Transmit Buffers

0h = No Dedicated Tx Buffers

1h-20h (1-32) = Number of Dedicated Tx Buffers

> 20h (32) = Values greater than 32 are interpreted as 32

15-2TBSAR/W0h

Tx Buffers Start Address

Start address of Tx Buffers section in Message RAM (32-bit word address, see Message RAM Configuration).

Note: Be aware that the sum of the MCAN_TXBC[29-24] TFQS and MCAN_TXBC[21-16] NDTB fields may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers.
1-0RESERVEDR0h

Reserved

1.5.2.35 MCAN_TXFQS Register (Offset = C4h) [reset = 0h]

MCAN_TXFQS is shown in Figure 12-2166 and described in Table 12-4210.

Return to Summary Table.

Tx FIFO/Queue Status
Tx FIFO/Queue full indication and put index, Tx FIFO get index and fill level.

The Tx FIFO/Queue status is related to the pending Tx requests listed in the MCAN_TXBRP register. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (the MCAN_TXBRP register not yet updated).

Table 12-4209 MCAN_TXFQS Instances
InstancePhysical Address
MCAN0_CFG2070 10C4h
MCAN1_CFG2071 10C4h
Figure 12-2166 MCAN_TXFQS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTFQFTFQPI
R-0hR-0hR-0h
15141312111098
RESERVEDTFGI
R-0hR-0h
76543210
RESERVEDTFFL
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4210 MCAN_TXFQS Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h

Reserved

21TFQFR0h

Tx FIFO/Queue Full

0h = Tx FIFO/Queue not full

1h = Tx FIFO/Queue full

20-16TFQPIR0h

Tx FIFO/Queue Put Index

Tx FIFO/Queue write index pointer, range 0 to 31.

15-13RESERVEDR0h

Reserved

12-8TFGIR0h

Tx FIFO Get Index

Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1h).

7-6RESERVEDR0h

Reserved

5-0TFFLR0h

Tx FIFO Free Level

Number of consecutive free Tx FIFO elements starting from the MCAN_TXFQS[12-8] TFGI field, range 0 to 32. Read as zero when Tx Queue operation is configured (MCAN_TXBC[30] TFQM = 1h).

Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.

1.5.2.36 MCAN_TXESC Register (Offset = C8h) [reset = 0h]

MCAN_TXESC is shown in Figure 12-2167 and described in Table 12-4212.

Return to Summary Table.

Tx Buffer Element Size Configuration
Configure data field size for frame transmission.

Configures the number of data bytes belonging to a Tx Buffer element. Data field sizes > 8 bytes are intended for CAN FD operation only.

Table 12-4211 MCAN_TXESC Instances
InstancePhysical Address
MCAN0_CFG2070 10C8h
MCAN1_CFG2071 10C8h
Figure 12-2167 MCAN_TXESC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTBDS
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4212 MCAN_TXESC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0TBDSR/W0h

Tx Buffer Data Field Size

0h = 8 byte data field

1h = 12 byte data field

2h = 16 byte data field

3h = 20 byte data field

4h = 24 byte data field

5h = 32 byte data field

6h = 48 byte data field

7h = 64 byte data field

Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size MCAN_TXESC[2-0] TBDS, the bytes not defined by the Tx Buffer are transmitted as CCh (padding bytes).

1.5.2.37 MCAN_TXBRP Register (Offset = CCh) [reset = 0h]

MCAN_TXBRP is shown in Figure 12-2168 and described in Table 12-4214.

Return to Summary Table.

Tx Buffer Request Pending
Tx buffers with pending transmission request.

Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via the MCAN_TXBAR register. The bits are reset after a requested transmission has completed or has been cancelled via the MCAN_TXBCR register.

The MCAN_TXBRP bits are set only for those Tx Buffers configured via the MCAN_TXBC register. After a MCAN_TXBRP bit has been set, a Tx scan (see Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID).

A cancellation request resets the corresponding transmission request pending bit of register the MCAN_TXBRP register. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding MCAN_TXBRP bit has been reset.

After a cancellation has been requested, a finished cancellation is signalled via the MCAN_TXBCF flag

• after successful transmission together with the corresponding MCAN_TXBTO bit

• when the transmission has not yet been started at the point of cancellation

• when the transmission has been aborted due to lost arbitration

• when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding MCAN_TXBCF bit is set for all unsuccessful transmissions.

Note: The MCAN_TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding MCAN_TXBRP bit is reset.

Table 12-4213 MCAN_TXBRP Instances
InstancePhysical Address
MCAN0_CFG2070 10CCh
MCAN1_CFG2071 10CCh
Figure 12-2168 MCAN_TXBRP Register
3130292827262524
TRP31TRP30TRP29TRP28TRP27TRP26TRP25TRP24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TRP23TRP22TRP21TRP20TRP19TRP18TRP17TRP16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TRP15TRP14TRP13TRP12TRP11TRP10TRP9TRP8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TRP7TRP6TRP5TRP4TRP3TRP2TRP1TRP0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4214 MCAN_TXBRP Register Field Descriptions
BitFieldTypeResetDescription
31TRP31R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

30TRP30R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

29TRP29R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

28TRP28R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

27TRP27R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

26TRP26R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

25TRP25R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

24TRP24R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

23TRP23R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

22TRP22R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

21TRP21R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

20TRP20R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

19TRP19R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

18TRP18R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

17TRP17R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

16TRP16R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

15TRP15R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

14TRP14R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

13TRP13R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

12TRP12R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

11TRP11R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

10TRP10R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

9TRP9R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

8TRP8R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

7TRP7R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

6TRP6R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

5TRP5R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

4TRP4R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

3TRP3R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

2TRP2R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

1TRP1R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

0TRP0R0h

Transmission Request Pending

0h = No transmission request pending

1h = Transmission request pending

1.5.2.38 MCAN_TXBAR Register (Offset = D0h) [reset = 0h]

MCAN_TXBAR is shown in Figure 12-2169 and described in Table 12-4216.

Return to Summary Table.

Tx Buffer Add Request
Add transmission requests.

Each Tx Buffer has its own Add Request bit. Writing 1h will set the corresponding Add Request bit; writing a 0h has no impact. This enables the Host CPU to set transmission requests for multiple Tx Buffers with one write to the MCAN_TXBAR register. The MCAN_TXBAR bits are set only for those Tx Buffers configured via the MCAN_TXBC register. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed.

Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding MCAN_TXBRP bit already set), this add request is ignored.

Table 12-4215 MCAN_TXBAR Instances
InstancePhysical Address
MCAN0_CFG2070 10D0h
MCAN1_CFG2071 10D0h
Figure 12-2169 MCAN_TXBAR Register
3130292827262524
AR31AR30AR29AR28AR27AR26AR25AR24
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
2322212019181716
AR23AR22AR21AR20AR19AR18AR17AR16
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
15141312111098
AR15AR14AR13AR12AR11AR10AR9AR8
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
76543210
AR7AR6AR5AR4AR3AR2AR1AR0
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4216 MCAN_TXBAR Register Field Descriptions
BitFieldTypeResetDescription
31AR31RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

30AR30RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

29AR29RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

28AR28RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

27AR27RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

26AR26RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

25AR25RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

24AR24RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

23AR23RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

22AR22RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

21AR21RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

20AR20RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

19AR19RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

18AR18RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

17AR17RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

16AR16RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

15AR15RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

14AR14RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

13AR13RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

12AR12RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

11AR11RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

10AR10RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

9AR9RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

8AR8RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

7AR7RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

6AR6RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

5AR5RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

4AR4RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

3AR3RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

2AR2RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

1AR1RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

0AR0RW1TC0h

Add Request

0h = No transmission request added

1h = Transmission requested added

1.5.2.39 MCAN_TXBCR Register (Offset = D4h) [reset = 0h]

MCAN_TXBCR is shown in Figure 12-2170 and described in Table 12-4218.

Return to Summary Table.

Tx Buffer Cancellation Request
Request cancellation of pending transmissions.

Each Tx Buffer has its own Cancellation Request bit. Writing a 1h will set the corresponding Cancellation Request bit; writing a 0h has no impact. This enables the Host CPU to set cancellation requests for multiple Tx Buffers with one write to the MCAN_TXBCR register. The MCAN_TXBCR bits are set only for those Tx Buffers configured via the MCAN_TXBC register. The bits remain set until the corresponding bit of the MCAN_TXBRP register is reset.

Table 12-4217 MCAN_TXBCR Instances
InstancePhysical Address
MCAN0_CFG2070 10D4h
MCAN1_CFG2071 10D4h
Figure 12-2170 MCAN_TXBCR Register
3130292827262524
CR31CR30CR29CR28CR27CR26CR25CR24
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
2322212019181716
CR23CR22CR21CR20CR19CR18CR17CR16
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
15141312111098
CR15CR14CR13CR12CR11CR10CR9CR8
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
76543210
CR7CR6CR5CR4CR3CR2CR1CR0
RW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0hRW1TC-0h
LEGEND: RW1TC = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4218 MCAN_TXBCR Register Field Descriptions
BitFieldTypeResetDescription
31CR31RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

30CR30RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

29CR29RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

28CR28RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

27CR27RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

26CR26RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

25CR25RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

24CR24RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

23CR23RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

22CR22RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

21CR21RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

20CR20RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

19CR19RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

18CR18RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

17CR17RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

16CR16RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

15CR15RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

14CR14RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

13CR13RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

12CR12RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

11CR11RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

10CR10RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

9CR9RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

8CR8RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

7CR7RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

6CR6RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

5CR5RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

4CR4RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

3CR3RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

2CR2RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

1CR1RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

0CR0RW1TC0h

Cancellation Request

0h = No cancellation pending

1h = Cancellation pending

1.5.2.40 MCAN_TXBTO Register (Offset = D8h) [reset = 0h]

MCAN_TXBTO is shown in Figure 12-2171 and described in Table 12-4220.

Return to Summary Table.

Tx Buffer Transmission Occurred
Signals successful transmissions, set when corresponding MCAN_TXBRP flag is cleared.

Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding MCAN_TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of register the MCAN_TXBAR register.

Table 12-4219 MCAN_TXBTO Instances
InstancePhysical Address
MCAN0_CFG2070 10D8h
MCAN1_CFG2071 10D8h
Figure 12-2171 MCAN_TXBTO Register
3130292827262524
TO31TO30TO29TO28TO27TO26TO25TO24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
TO23TO22TO21TO20TO19TO18TO17TO16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TO15TO14TO13TO12TO11TO10TO9TO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TO7TO6TO5TO4TO3TO2TO1TO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4220 MCAN_TXBTO Register Field Descriptions
BitFieldTypeResetDescription
31TO31R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

30TO30R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

29TO29R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

28TO28R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

27TO27R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

26TO26R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

25TO25R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

24TO24R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

23TO23R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

22TO22R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

21TO21R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

20TO20R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

19TO19R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

18TO18R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

17TO17R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

16TO16R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

15TO15R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

14TO14R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

13TO13R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

12TO12R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

11TO11R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

10TO10R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

9TO9R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

8TO8R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

7TO7R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

6TO6R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

5TO5R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

4TO4R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

3TO3R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

2TO2R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

1TO1R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

0TO0R0h

Transmission Occurred

0h = No transmission occurred

1h = Transmission occurred

1.5.2.41 MCAN_TXBCF Register (Offset = DCh) [reset = 0h]

MCAN_TXBCF is shown in Figure 12-2172 and described in Table 12-4222.

Return to Summary Table.

Tx Buffer Cancellation Finished
Signals successful transmit cancellation, set when corresponding MCAN_TXBRP flag is cleared after cancellation request.

Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding MCAN_TXBRP bit is cleared after a cancellation was requested via the MCAN_TXBCR register. In case the corresponding MCAN_TXBRP bit was not set at the point of cancellation, MCAN_TXBCF[n] CF bit is set immediately. The bits are reset when a new transmission is requested by writing a 1h to the corresponding bit of the MCAN_TXBAR register.

Table 12-4221 MCAN_TXBCF Instances
InstancePhysical Address
MCAN0_CFG2070 10DCh
MCAN1_CFG2071 10DCh
Figure 12-2172 MCAN_TXBCF Register
3130292827262524
CF31CF30CF29CF28CF27CF26CF25CF24
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
CF23CF22CF21CF20CF19CF18CF17CF16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
CF15CF14CF13CF12CF11CF10CF9CF8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
CF7CF6CF5CF4CF3CF2CF1CF0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4222 MCAN_TXBCF Register Field Descriptions
BitFieldTypeResetDescription
31CF31R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

30CF30R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

29CF29R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

28CF28R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

27CF27R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

26CF26R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

25CF25R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

24CF24R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

23CF23R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

22CF22R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

21CF21R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

20CF20R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

19CF19R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

18CF18R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

17CF17R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

16CF16R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

15CF15R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

14CF14R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

13CF13R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

12CF12R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

11CF11R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

10CF10R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

9CF9R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

8CF8R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

7CF7R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

6CF6R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

5CF5R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

4CF4R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

3CF3R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

2CF2R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

1CF1R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

0CF0R0h

Cancellation Finished

0h = No transmit buffer cancellation

1h = Transmit buffer cancellation finished

1.5.2.42 MCAN_TXBTIE Register (Offset = E0h) [reset = 0h]

MCAN_TXBTIE is shown in Figure 12-2173 and described in Table 12-4224.

Return to Summary Table.

Tx Buffer Transmission Interrupt Enable
Enable transmit interrupts for selected Tx buffers.

Table 12-4223 MCAN_TXBTIE Instances
InstancePhysical Address
MCAN0_CFG2070 10E0h
MCAN1_CFG2071 10E0h
Figure 12-2173 MCAN_TXBTIE Register
3130292827262524
TIE31TIE30TIE29TIE28TIE27TIE26TIE25TIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
TIE23TIE22TIE21TIE20TIE19TIE18TIE17TIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIE15TIE14TIE13TIE12TIE11TIE10TIE9TIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TIE7TIE6TIE5TIE4TIE3TIE2TIE1TIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4224 MCAN_TXBTIE Register Field Descriptions
BitFieldTypeResetDescription
31TIE31R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

30TIE30R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

29TIE29R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

28TIE28R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

27TIE27R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

26TIE26R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

25TIE25R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

24TIE24R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

23TIE23R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

22TIE22R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

21TIE21R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

20TIE20R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

19TIE19R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

18TIE18R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

17TIE17R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

16TIE16R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

15TIE15R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

14TIE14R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

13TIE13R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

12TIE12R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

11TIE11R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

10TIE10R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

9TIE9R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

8TIE8R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

7TIE7R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

6TIE6R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

5TIE5R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

4TIE4R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

3TIE3R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

2TIE2R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

1TIE1R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

0TIE0R/W0h

Transmission Interrupt Enable

0h = Transmission interrupt disabled

1h = Transmission interrupt enable

1.5.2.43 MCAN_TXBCIE Register (Offset = E4h) [reset = 0h]

MCAN_TXBCIE is shown in Figure 12-2174 and described in Table 12-4226.

Return to Summary Table.

Tx Buffer Cancellation Finished Interrupt Enable
Enable cancellation finished interrupts for selected Tx buffers.

Table 12-4225 MCAN_TXBCIE Instances
InstancePhysical Address
MCAN0_CFG2070 10E4h
MCAN1_CFG2071 10E4h
Figure 12-2174 MCAN_TXBCIE Register
3130292827262524
CFIE31CFIE30CFIE29CFIE28CFIE27CFIE26CFIE25CFIE24
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CFIE23CFIE22CFIE21CFIE20CFIE19CFIE18CFIE17CFIE16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CFIE15CFIE14CFIE13CFIE12CFIE11CFIE10CFIE9CFIE8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CFIE7CFIE6CFIE5CFIE4CFIE3CFIE2CFIE1CFIE0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4226 MCAN_TXBCIE Register Field Descriptions
BitFieldTypeResetDescription
31CFIE31R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

30CFIE30R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

29CFIE29R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

28CFIE28R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

27CFIE27R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

26CFIE26R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

25CFIE25R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

24CFIE24R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

23CFIE23R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

22CFIE22R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

21CFIE21R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

20CFIE20R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

19CFIE19R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

18CFIE18R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

17CFIE17R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

16CFIE16R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

15CFIE15R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

14CFIE14R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

13CFIE13R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

12CFIE12R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

11CFIE11R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

10CFIE10R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

9CFIE9R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

8CFIE8R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

7CFIE7R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

6CFIE6R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

5CFIE5R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

4CFIE4R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

3CFIE3R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

2CFIE2R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

1CFIE1R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

0CFIE0R/W0h

Cancellation Finished Interrupt Enable

0h = Cancellation finished interrupt disabled

1h = Cancellation finished interrupt enabled

1.5.2.44 MCAN_TXEFC Register (Offset = F0h) [reset = 0h]

MCAN_TXEFC is shown in Figure 12-2175 and described in Table 12-4228.

Return to Summary Table.

Tx Event FIFO Configuration
Tx event FIFO watermark, size and start address.

Table 12-4227 MCAN_TXEFC Instances
InstancePhysical Address
MCAN0_CFG2070 10F0h
MCAN1_CFG2071 10F0h
Figure 12-2175 MCAN_TXEFC Register
3130292827262524
RESERVEDEFWM
R-0hR/W-0h
2322212019181716
RESERVEDEFS
R-0hR/W-0h
15141312111098
EFSA
R/W-0h
76543210
EFSARESERVED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4228 MCAN_TXEFC Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29-24EFWMR/W0h

Event FIFO Watermark

0h = Watermark interrupt disabled

1h-20h (1-32) = Level for Tx Event FIFO watermark interrupt (MCAN_IR[13] TEFW)

> 20h (32) = Watermark interrupt disabled

23-22RESERVEDR0h

Reserved

21-16EFSR/W0h

Event FIFO Size

0h = Tx Event FIFO disabled

1h-20h (1-32) = Number of Tx Event FIFO elements

> 20h (32) = Values greater than 32 are interpreted as 32

The Tx Event FIFO elements are indexed from 0 to MCAN_TXEFC[21-16] EFS field - 1.

15-2EFSAR/W0h

Event FIFO Start Address

Start address of Tx Event FIFO in Message RAM (32-bit word address, see Message RAM Configuration).

1-0RESERVEDR0h

Reserved

1.5.2.45 MCAN_TXEFS Register (Offset = F4h) [reset = 0h]

MCAN_TXEFS is shown in Figure 12-2176 and described in Table 12-4230.

Return to Summary Table.

Tx Event FIFO Status
Tx event FIFO element lost/full indication, put index, get index, and fill level.

Table 12-4229 MCAN_TXEFS Instances
InstancePhysical Address
MCAN0_CFG2070 10F4h
MCAN1_CFG2071 10F4h
Figure 12-2176 MCAN_TXEFS Register
3130292827262524
RESERVEDTEFLEFF
R-0hR-0hR-0h
2322212019181716
RESERVEDEFPI
R-0hR-0h
15141312111098
RESERVEDEFGI
R-0hR-0h
76543210
RESERVEDEFFL
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4230 MCAN_TXEFS Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h

Reserved

25TEFLR0h

This bit is a copy of interrupt flag MCAN_IR[15] TEFL. When the MCAN_IR[15] TEFL flag is reset, this bit is also reset.

0h = No Tx Event FIFO element lost

1h = Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.

24EFFR0h

Event FIFO Full

0h = Tx Event FIFO not full

1h = Tx Event FIFO full

23-21RESERVEDR0h

Reserved

20-16EFPIR0h

Event FIFO Put Index

Tx Event FIFO write index pointer, range 0 to 31.

15-13RESERVEDR0h

Reserved

12-8EFGIR0h

Event FIFO Get Index

Tx Event FIFO read index pointer, range 0 to 31.

7-6RESERVEDR0h

Reserved

5-0EFFLR0h

Event FIFO Fill Level

Number of elements stored in Tx Event FIFO, range 0 to 32.

1.5.2.46 MCAN_TXEFA Register (Offset = F8h) [reset = 0h]

MCAN_TXEFA is shown in Figure 12-2177 and described in Table 12-4232.

Return to Summary Table.

Tx Event FIFO Acknowledge
Tx event FIFO acknowledge last index of read elements, updates get index and fill level.

Table 12-4231 MCAN_TXEFA Instances
InstancePhysical Address
MCAN0_CFG2070 10F8h
MCAN1_CFG2071 10F8h
Figure 12-2177 MCAN_TXEFA Register
313029282726252423222120191817161514131211109876543210
RESERVEDEFAI
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4232 MCAN_TXEFA Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0EFAIR/W0h

After the Host CPU has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to the MCAN_TXEFA[4-0] EFAI field. This will set the Tx Event FIFO Get Index MCAN_TXEFS[12-8] EFGI field to the MCAN_TXEFA[4-0] EFAI field + 1 and update the Event FIFO Fill Level MCAN_TXEFS[5-0] EFFL field.