SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 6-500 through Table 6-502 lists the memory-mapped control registers for the PRU_ICSSG PRU0/PRU1, RTU_PRU0/RTU_PRU1 and TX_PRU0/TX_PRU1 cores. All register offset addresses not listed in Table 6-500 through Table 6-502 should be considered as reserved locations and the register contents should not be modified.
PDSP in instance names is equivalent to the PRU processor.
Instance | Base Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2000h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4000h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2000h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4000h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3000h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3800h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3000h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3800h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5000h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5800h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5000h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5800h |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_PDSP0_IRAM Physical Address | PRU_ICSSG0_PR1_PDSP1_IRAM Physical Address | PRU_ICSSG1_PR1_PDSP0_IRAM Physical Address | PRU_ICSSG1_PR1_PDSP1_IRAM Physical Address |
---|---|---|---|---|---|---|
0h | ICSSG_PRU_CONTROL | Control Register | 3002 2000h | 3002 4000h | 300A 2000h | 300A 4000h |
4h | ICSSG_PRU_STATUS | Status Register | 3002 2004h | 3002 4004h | 300A 2004h | 300A 4004h |
8h | ICSSG_PRU_WAKEUP_EN | Wakeup Enable Register | 3002 2008h | 3002 4008h | 300A 2008h | 300A 4008h |
Ch | ICSSG_PRU_CYCLE | Cycle Count | 3002 200Ch | 3002 400Ch | 300A 200Ch | 300A 400Ch |
10h | ICSSG_PRU_STALL | Stall Count | 3002 2010h | 3002 4010h | 300A 2010h | 300A 4010h |
20h | ICSSG_PRU_CTBIR0 | Constant Table Block Index Register 0 | 3002 2020h | 3002 4020h | 300A 2020h | 300A 4020h |
24h | ICSSG_PRU_CTBIR1 | Constant Table Block Index Register 1 | 3002 2024h | 3002 4024h | 300A 2024h | 300A 4024h |
28h | ICSSG_PRU_CTPPR0 | Constant Table Programmable Pointer Register 0 | 3002 2028h | 3002 4028h | 300A 2028h | 300A 4028h |
2Ch | ICSSG_PRU_CTPPR1 | Constant Table Programmable Pointer Register 1 | 3002 202Ch | 3002 402Ch | 300A 202Ch | 300A 402Ch |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM Physical Address | PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM Physical Address | PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM Physical Address | PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM Physical Address |
---|---|---|---|---|---|---|
0h | ICSSG_PRU_CONTROL | Control Register | 3002 3000h | 3002 3800h | 300A 3000h | 300A 3800h |
4h | ICSSG_PRU_STATUS | Status Register | 3002 3004h | 3002 3804h | 300A 3004h | 300A 3804h |
8h | ICSSG_PRU_WAKEUP_EN | Wakeup Enable Register | 3002 3008h | 3002 3808h | 300A 3008h | 300A 3808h |
Ch | ICSSG_PRU_CYCLE | Cycle Count | 3002 300Ch | 3002 380Ch | 300A 300Ch | 300A 380Ch |
10h | ICSSG_PRU_STALL | Stall Count | 3002 3010h | 3002 3810h | 300A 3010h | 300A 3810h |
20h | ICSSG_PRU_CTBIR0 | Constant Table Block Index Register 0 | 3002 3020h | 3002 3820h | 300A 3020h | 300A 3820h |
24h | ICSSG_PRU_CTBIR1 | Constant Table Block Index Register 1 | 3002 3024h | 3002 3824h | 300A 3024h | 300A 3824h |
28h | ICSSG_PRU_CTPPR0 | Constant Table Programmable Pointer Register 0 | 3002 3028h | 3002 3828h | 300A 3028h | 300A 3828h |
2Ch | ICSSG_PRU_CTPPR1 | Constant Table Programmable Pointer Register 1 | 3002 302Ch | 3002 382Ch | 300A 302Ch | 300A 382Ch |
Offset | Acronym | Register Name | PRU_ICSSG0_PR1_TX_PDSP0_IRAM Physical Address | PRU_ICSSG0_PR1_TX_PDSP1_IRAM Physical Address | PRU_ICSSG1_PR1_TX_PDSP0_IRAM Physical Address | PRU_ICSSG1_PR1_TX_PDSP1_IRAM Physical Address |
---|---|---|---|---|---|---|
0h | ICSSG_PRU_CONTROL | Control Register | 3002 5000h | 3002 5800h | 300A 5000h | 300A 5800h |
4h | ICSSG_PRU_STATUS | Status Register | 3002 5004h | 3002 5804h | 300A 5004h | 300A 5804h |
8h | ICSSG_PRU_WAKEUP_EN | Wakeup Enable Register | 3002 5008h | 3002 5808h | 300A 5008h | 300A 5808h |
Ch | ICSSG_PRU_CYCLE | Cycle Count | 3002 500Ch | 3002 580Ch | 300A 500Ch | 300A 580Ch |
10h | ICSSG_PRU_STALL | Stall Count | 3002 5010h | 3002 5810h | 300A 5010h | 300A 5810h |
20h | ICSSG_PRU_CTBIR0 | Constant Table Block Index Register 0 | 3002 5020h | 3002 5820h | 300A 5020h | 300A 5820h |
24h | ICSSG_PRU_CTBIR1 | Constant Table Block Index Register 1 | 3002 5024h | 3002 5824h | 300A 5024h | 300A 5824h |
28h | ICSSG_PRU_CTPPR0 | Constant Table Programmable Pointer Register 0 | 3002 5028h | 3002 5828h | 300A 5028h | 300A 5828h |
2Ch | ICSSG_PRU_CTPPR1 | Constant Table Programmable Pointer Register 1 | 3002 502Ch | 3002 582Ch | 300A 502Ch | 300A 582Ch |
PRU_CONTROL is shown in Figure 6-269 and described in Table 6-504.
PRU Control Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2000h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4000h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2000h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4000h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3000h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3800h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3000h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3800h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5000h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5800h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5000h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5800h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PCOUNTER_RST_VAL | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PCOUNTER_RST_VAL | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RUNSTATE | RESERVED | TS_ENABLE | RESERVED | SINGLE_STEP | |||
R-0h | R-0h | R-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | COUNTER_ENABLE | SLEEPING | ENABLE | SOFT_RST_N | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R-1h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | PCOUNTER_RST_VAL | R/W | 0h | Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset. |
15 | RUNSTATE | R | 0h | Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. |
14 | RESERVED | Reserved | ||
13 | TS_ENABLE | R | 0h | Task Swapping Enable: This bit indicates the current state of the internal task swapping enable flag. When this bit is clear, the PRU will ignore requests which are presented on the Task Swap Request interface. When this bit is set, the PRU will gracefully complete any multi-cycle instruction and will then issue an XCHG instruction using the 22 LSBs as provided on the task swap request interface. |
12-9 | RESERVED | R | 0h | Reserved |
8 | SINGLE_STEP | R/W | 0h | Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. |
7-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | Reserved | ||
3 | COUNTER_ENABLE | R/W | 0h | PRU Cycle Counter Enable: Enables PRU cycle counters. |
2 | SLEEPING | R/W | 0h | PRU Sleep Indicator: This bit indicates whether or
not the PRU is currently asleep. |
1 | ENABLE | R/W | 0h | Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The [15]RUNSTATE bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream. |
0 | SOFT_RST_N | R/W | 1h | Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1h on the next cycle after it has been cleared. |
PRU_STATUS is shown in Figure 6-270 and described in Table 6-506.
PRU Status Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2004h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4004h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2004h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4004h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3004h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3804h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3004h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3804h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5004h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5804h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5004h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5804h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PCOUNTER | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | PCOUNTER | R | 0h | Program Counter: This field is a registered (1
cycle delayed) reflection of the PRU program counter. |
PRU_WAKEUP_EN is shown in Figure 6-271 and described in Table 6-508.
PRU Wakeup Enable Register.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2008h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4008h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2008h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4008h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3008h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3808h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3008h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3808h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5008h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5808h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5008h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5808h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BITWISE_ENABLES | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BITWISE_ENABLES | R/W | 0h | Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core. |
PRU_CYCLE is shown in Figure 6-272 and described in Table 6-510.
PRU Cycle Count. This register counts the number of cycles for which the PRU has been enabled.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 200Ch |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 400Ch |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 200Ch |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 400Ch |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 300Ch |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 380Ch |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 300Ch |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 380Ch |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 500Ch |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 580Ch |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 500Ch |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 580Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CYCLECOUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CYCLECOUNT | R/W | 0h | This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in the ICSSG_PRU_CONTROL register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the [3]COUNTER_ENABLE bit in the ICSSG_PRU_CONTROL register when the count reaches FFFFFFFFh. (Count does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register (ICSSG_PRU_STALL). |
PRU_STALL is shown in Figure 6-273 and described in Table 6-512.
PRU Stall Count Register. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (ICSSG_PRU_CYCLE, offset: 0Ch) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2010h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4010h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2010h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4010h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3010h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3810h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3010h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3810h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5010h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5810h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5010h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5810h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STALLCOUNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STALLCOUNT | R | 0h | This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits [1]ENABLE and [3]COUNTER_ENABLE set in the ICSSG_PRU_CONTROL register), and the PRU was unable to fetch a new instruction for any reason. Counting halts while the PRU is disabled or the counter is disabled, and resumes when re-enabled. The register can be read at any time. The register is cleared when PRU Cycle Count Register (ICSSG_PRU_CYCLE) is cleared. |
PRU_CTBIR0 is shown in Figure 6-274 and described in Table 6-514.
Constant Table Block Index Register 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2020h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4020h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2020h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4020h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3020h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3820h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3020h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3820h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5020h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5820h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5020h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5820h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | C25_BLK_INDEX | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | C24_BLK_INDEX | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | C25_BLK_INDEX | R/W | 0h | PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 15:8 of entry 25 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 26. |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | C24_BLK_INDEX | R/W | 0h | PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 15:8 of entry 24 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 25. |
PRU_CTBIR1 is shown in Figure 6-275 and described in Table 6-516.
Constant Table Block Index Register 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2024h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4024h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2024h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4024h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3024h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3824h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3024h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3824h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5024h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5824h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5024h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5824h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | C27_BLK_INDEX | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | C26_BLK_INDEX | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | C27_BLK_INDEX | R/W | 0h | PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 15:8 of entry 27 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 28. |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | C26_BLK_INDEX | R/W | 0h | PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 15:8 of entry 26 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 27. |
PRU_CTPPR0 is shown in Figure 6-276 and described in Table 6-518.
Constant Table Programmable Pointer Register 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 2028h |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 4028h |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 2028h |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 4028h |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 3028h |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 3828h |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 3028h |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 3828h |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 5028h |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 5828h |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 5028h |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 5828h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C29_POINTER | C28_POINTER | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | C29_POINTER | R/W | 0h | PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits [23-8] of entry 29 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 30. |
15-0 | C28_POINTER | R/W | 0h | PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits [23-8] of entry 28 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 29. |
PRU_CTPPR1 is shown in Figure 6-277 and described in Table 6-520.
Constant Table Programmable Pointer Register 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table.
Instance | Physical Address |
---|---|
PRU_ICSSG0_PR1_PDSP0_IRAM | 3002 202Ch |
PRU_ICSSG0_PR1_PDSP1_IRAM | 3002 402Ch |
PRU_ICSSG1_PR1_PDSP0_IRAM | 300A 202Ch |
PRU_ICSSG1_PR1_PDSP1_IRAM | 300A 402Ch |
PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM | 3002 302Ch |
PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM | 3002 382Ch |
PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM | 300A 302Ch |
PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM | 300A 382Ch |
PRU_ICSSG0_PR1_TX_PDSP0_IRAM | 3002 502Ch |
PRU_ICSSG0_PR1_TX_PDSP1_IRAM | 3002 582Ch |
PRU_ICSSG1_PR1_TX_PDSP0_IRAM | 300A 502Ch |
PRU_ICSSG1_PR1_TX_PDSP1_IRAM | 300A 582Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
C31_POINTER | C30_POINTER | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | C31_POINTER | R/W | 0h | PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits [23-8] of entry 31 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 32. |
15-0 | C30_POINTER | R/W | 0h | PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits [23-8] of entry 30 in the PRU Constant Table. This field while always present is only used if the ctreg_cnt configuration value is less than 31. |