SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There are six RTI modules integrated in the device MAIN domain. Figure 12-2423 shows their integration in the device.
Table 12-4620 through Table 12-4623 summarize the integration of RTIi (where i = 0, 1, 8, 9, 10, 11) in device MAIN domain.
Each RTIi instance is supplied by dedicated RTICLKi mux.
Module Instance | Attributes | |||
---|---|---|---|---|
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
RTI0 | PSC0 | PD2 | LPSC22 | CBASS0 |
RTI1 | PSC0 | PD3 | LPSC23 | CBASS0 |
RTI8 | PSC0 | PD4 | LPSC24 | CBASS0 |
RTI9 | PSC0 | PD4 | LPSC25 | CBASS0 |
RTI10 | PSC0 | PD5 | LPSC27 | CBASS0 |
RTI11 | PSC0 | PD5 | LPSC28 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
RTI0 | RTI0_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI0 Interface Clock |
RTI0_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI0 Functional Clock. For more information about clock multiplexing in RTICLK0 MUX, see CTRLMMR_WWD0_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K | ||||
RTI1 | RTI1_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI1 Interface Clock |
RTI1_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI1 Functional Clock. For more information about clock multiplexing in RTICLK1 MUX, see CTRLMMR_WWD1_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K | ||||
RTI8 | RTI8_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI8 Interface Clock |
RTI8_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI8 Functional Clock. For more information about clock multiplexing in RTICLK8 MUX, see CTRLMMR_WWD8_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K | ||||
RTI9 | RTI9_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI9 Interface Clock |
RTI9_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI9 Functional Clock. For more information about clock multiplexing in RTICLK9 MUX, see CTRLMMR_WWD9_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K | ||||
RTI10 | RTI10_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI10 Interface Clock |
RTI10_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI10 Functional Clock. For more information about clock multiplexing in RTICLK10 MUX, see CTRLMMR_WWD10_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K | ||||
RTI11 | RTI11_ICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | RTI11 Interface Clock |
RTI11_FCLK | MCU_HFOSC0_CLKOUT | MCU_HFOSC0 | RTI11 Functional Clock. For more information about clock multiplexing in RTICLK11 MUX, see CTRLMMR_WWD11_CLKSEL[1-0] CLK_SEL in Section 5.1, Control Module (CTRL_MMR). | |
MCU_HFOSC0_CLKOUT_32K | ||||
MCU_CLK_12M_RC | MCU_RC_OSC_12M | |||
CLK_32K |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
RTI0 | RTI0_RST | MOD_G_RST | LPSC22 | RTI0 Asynchronous Reset |
RTI0_POR_RST | MOD_POR_RST | LPSC22 | RTI0 Power-On Reset | |
RTI1 | RTI1_RST | MOD_G_RST | LPSC23 | RTI1 Asynchronous Reset |
RTI1_POR_RST | MOD_POR_RST | LPSC23 | RTI1 Power-On Reset | |
RTI8 | RTI8_RST | MOD_G_RST | LPSC24 | RTI8 Asynchronous Reset |
RTI8_POR_RST | MOD_POR_RST | LPSC24 | RTI8 Power-On Reset | |
RTI9 | RTI9_RST | MOD_G_RST | LPSC25 | RTI9 Asynchronous Reset |
RTI9_POR_RST | MOD_POR_RST | LPSC25 | RTI9 Power-On Reset | |
RTI10 | RTI10_RST | MOD_G_RST | LPSC27 | RTI10 Asynchronous Reset |
RTI10_POR_RST | MOD_POR_RST | LPSC27 | RTI10 Power-On Reset | |
RTI11 | RTI11_RST | MOD_G_RST | LPSC28 | RTI11 Asynchronous Reset |
RTI11_POR_RST | MOD_POR_RST | LPSC28 | RTI11 Power-On Reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
RTI0 | RTI0_INTR_WWD_0 | GICSS0_SPI_IN_169 | COMPUTE_CLUSTER0 | RTI0 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_160 | ESM0 | ||||
RTI1 | RTI1_INTR_WWD_0 | GICSS0_SPI_IN_170 | COMPUTE_CLUSTER0 | RTI1 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_161 | ESM0 | ||||
RTI8 | RTI28_INTR_WWD_0 | R5FSS0_CORE0_INTR_IN_0 | R5FSS0_CORE0 | RTI8 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_162 | ESM0 | ||||
RTI9 | RTI29_INTR_WWD_0 | R5FSS0_CORE1_INTR_IN_0 | R5FSS0_CORE1 | RTI9 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_163 | ESM0 | ||||
RTI10 | RTI30_INTR_WWD_0 | R5FSS1_CORE0_INTR_IN_0 | R5FSS1_CORE0 | RTI10 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_164 | ESM0 | ||||
RTI11 | RTI15_INTR_WWD_0 | R5FSS1_CORE0_INTR_IN_0 | R5FSS1_CORE1 | RTI11 window watchdog violation interrupt | Pulse |
ESM0_PLS_IN_165 | ESM0 |
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.