SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-4234 lists the memory-mapped registers for the MCAN ECC Aggregator. All register offset addresses not listed in Table 12-4234 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCAN0_ECC_AGGR | 2401 8000h |
MCAN1_ECC_AGGR | 2401 9000h |
Offset | Acronym | Register Name | MCAN0_ECC_AGGR Physical Address | MCAN1_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 2401 8000h | 2401 9000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 2401 8008h | 2401 9008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 2401 800Ch | 2401 900Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 2401 803Ch | 2401 903Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 2401 8040h | 2401 9040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 2401 8080h | 2401 9080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 2401 80C0h | 2401 90C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 2401 813Ch | 2401 913Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 2401 8140h | 2401 9140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 2401 8180h | 2401 9180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 2401 81C0h | 2401 91C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 2401 8200h | 2401 9200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 2401 8204h | 2401 9204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 2401 8208h | 2401 9208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 2401 820Ch | 2401 920Ch |
MCANSS_ECC_REV is shown in Figure 12-2178 and described in Table 12-4236.
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Aggregator Revision Register
The Aggregator Revision Register contains the revision parameters for the ECC Aggregator.
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8000h |
MCAN1_ECC_AGGR | 2401 9000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MCANSS_ECC_VECTOR is shown in Figure 12-2179 and described in Table 12-4238.
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ECC Vector Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8008h |
MCAN1_ECC_AGGR | 2401 9008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MCANSS_ECC_STAT is shown in Figure 12-2180 and described in Table 12-4240.
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Misc Status Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 800Ch |
MCAN1_ECC_AGGR | 2401 900Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-2h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 2h | Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator. |
MCANSS_ECC_SEC_EOI_REG is shown in Figure 12-2181 and described in Table 12-4242.
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SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 803Ch |
MCAN1_ECC_AGGR | 2401 903Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | Single Error Correction End Of Interrupt (SEC EOI) |
MCANSS_ECC_SEC_STATUS_REG0 is shown in Figure 12-2182 and described in Table 12-4244.
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SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8040h |
MCAN1_ECC_AGGR | 2401 9040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_PEND | MSGMEM_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_PEND | R/W1S | 0h | Interrupt Pending Status for MSGMEM_PEND |
MCANSS_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2183 and described in Table 12-4246.
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SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8080h |
MCAN1_ECC_AGGR | 2401 9080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_SET | MSGMEM_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for MSGMEM_PEND |
MCANSS_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2184 and described in Table 12-4248.
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SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 80C0h |
MCAN1_ECC_AGGR | 2401 90C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_CLR | MSGMEM_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for MSGMEM_PEND |
MCANSS_ECC_DED_EOI_REG is shown in Figure 12-2185 and described in Table 12-4250.
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DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 813Ch |
MCAN1_ECC_AGGR | 2401 913Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | Double Error Correction End Of Interrupt (DED EOI) |
MCANSS_ECC_DED_STATUS_REG0 is shown in Figure 12-2186 and described in Table 12-4252.
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DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8140h |
MCAN1_ECC_AGGR | 2401 9140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_PEND | MSGMEM_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_PEND | R/W1S | 0h | Interrupt Pending Status for MSGMEM_PEND |
MCANSS_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2187 and described in Table 12-4254.
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DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8180h |
MCAN1_ECC_AGGR | 2401 9180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_SET | MSGMEM_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for MSGMEM_PEND |
MCANSS_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2188 and described in Table 12-4256.
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DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 81C0h |
MCAN1_ECC_AGGR | 2401 91C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_CLR | MSGMEM_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for MSGMEM_PEND |
MCANSS_ECC_AGGR_ENABLE_SET is shown in Figure 12-2189 and described in Table 12-4258.
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Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8200h |
MCAN1_ECC_AGGR | 2401 9200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt Enable Set for Serial ECC Interface Timeout Errors |
0 | PARITY | R/W1S | 0h | Interrupt Enable Set for Parity Errors |
MCANSS_ECC_AGGR_ENABLE_CLR is shown in Figure 12-2190 and described in Table 12-4260.
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Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8204h |
MCAN1_ECC_AGGR | 2401 9204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt Enable Clear for Serial ECC Interface Timeout Errors |
0 | PARITY | R/W1C | 0h | Interrupt Enable Clear for Parity Errors |
MCANSS_ECC_AGGR_STATUS_SET is shown in Figure 12-2191 and described in Table 12-4262.
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Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 8208h |
MCAN1_ECC_AGGR | 2401 9208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt Status Set for Serial ECC Interface Timeout Errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt Status Set for Parity Errors |
MCANSS_ECC_AGGR_STATUS_CLR is shown in Figure 12-2192 and described in Table 12-4264.
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Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MCAN0_ECC_AGGR | 2401 820Ch |
MCAN1_ECC_AGGR | 2401 920Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt Status Clear for Serial ECC Interface Timeout Errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt Status Clear for Parity Errors |