SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Table 12-1067 lists the memory-mapped registers for the CPSW0_CPINT. All register offset addresses not listed in Table 12-1067 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_NUSS_CPINT | 0800 0000h |
Offset | Acronym | Register Name | CPSW0_NUSS_CPINT Physical Address |
---|---|---|---|
1000h | CPSW_INT_REVISION | Revision Register | 0800 1000h |
1010h | CPSW_INT_EOI_REG | End of Interrupt Register | 0800 1010h |
1014h | CPSW_INT_INTR_VECTOR_REG | Interrupt Vector Register | 0800 1014h |
1100h | CPSW_INT_ENABLE_REG_OUT_PULSE_0 | Enable Register 0 | 0800 1100h |
1300h | CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 | Enable Clear Register 0 | 0800 1300h |
1500h | CPSW_INT_STATUS_REG_OUT_PULSE_0 | Status Register 0 | 0800 1500h |
1A80h | CPSW_INT_INTR_VECTOR_REG_OUT_PULSE | Interrupt Vector for out_pulse | 0800 1A80h |
CPSW_INT_REVISION is shown in Figure 12-562 and described in Table 12-1069.
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CPSW_INT_REVISION Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNCTION | |||||||||||||
R-1h | R-2h | R-690h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTLVER | MAJREV | CUSTOM | MINREV | ||||||||||||
R-14h | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNCTION | R | 690h | Module ID |
15-11 | RTLVER | R | 14h | RTL revisions |
10-8 | MAJREV | R | 2h | Major revision |
7-6 | CUSTOM | R | 0h | Custom revision |
5-0 | MINREV | R | 0h | Minor revision |
CPSW_INT_EOI_REG is shown in Figure 12-563 and described in Table 12-1071.
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End of Interrupt Register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | EOI_VECTOR | R/W | 0h | End of Interrupt Vector. |
CPSW_INT_INTR_VECTOR_REG is shown in Figure 12-564 and described in Table 12-1073.
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Interrupt Vector Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_VECTOR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | INTR_VECTOR | R | 0h | Interrupt Vector Register |
CPSW_INT_ENABLE_REG_OUT_PULSE_0 is shown in Figure 12-565 and described in Table 12-1075.
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Enable Register 0.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_OUT_PULSE_EN_STAT_PENDA | ENABLE_OUT_PULSE_EN_MDIO_PENDA | ENABLE_OUT_PULSE_EN_EVNT_PENDA | ||||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2 | ENABLE_OUT_PULSE_EN_STAT_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_stat_penda. |
1 | ENABLE_OUT_PULSE_EN_MDIO_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_mdio_penda. |
0 | ENABLE_OUT_PULSE_EN_EVNT_PENDA | R/W1S | 0h | Enable Set for out_pulse_en_evnt_penda. |
CPSW_INT_ENABLE_CLR_REG_OUT_PULSE_0 is shown in Figure 12-566 and described in Table 12-1077.
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Enable Clear Register 0.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR | ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR | ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR | ||||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2 | ENABLE_OUT_PULSE_EN_STAT_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_stat_penda. |
1 | ENABLE_OUT_PULSE_EN_MDIO_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_mdio_penda. |
0 | ENABLE_OUT_PULSE_EN_EVNT_PENDA_CLR | R/W1C | 0h | Enable Clear for out_pulse_en_evnt_penda. |
CPSW_INT_STATUS_REG_OUT_PULSE_0 is shown in Figure 12-567 and described in Table 12-1079.
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Status Register 0.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1500h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATUS_OUT_PULSE_STAT_PENDA | STATUS_OUT_PULSE_MDIO_PENDA | STATUS_OUT_PULSE_EVNT_PENDA | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | X | |
2 | STATUS_OUT_PULSE_STAT_PENDA | R | 0h | Status for out_pulse_en_stat_penda. |
1 | STATUS_OUT_PULSE_MDIO_PENDA | R | 0h | Status for out_pulse_en_mdio_penda. |
0 | STATUS_OUT_PULSE_EVNT_PENDA | R | 0h | Status for out_pulse_en_evnt_penda. |
CPSW_INT_INTR_VECTOR_REG_OUT_PULSE is shown in Figure 12-568 and described in Table 12-1081.
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Interrupt Vector for out_pulse.
Instance | Physical Address |
---|---|
CPSW0_NUSS_CPINT | 0800 1A80h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTR_VECTOR_OUT_PULSE | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | INTR_VECTOR_OUT_PULSE | R | 0h | Interrupt Vector. |