SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
These 32-bit registers are fed by the 32-bit counter timer bus, CTR[0-31] and are loaded (capture a time-stamp) when their respective LD inputs are strobed.
Loading of the capture registers can be inhibited via the control ECAP_ECCTL[8] CAPLDEN bit. During one-shot operation, this bit is cleared (loading is inhibited) automatically when a stop condition occurs, StopValue = Mod4.
The ECAP_CAP1 and ECAP_CAP2 registers become the active period and compare registers, respectively, in APWM mode.
The ECAP_CAP3 and ECAP_CAP4 registers become the respective shadow registers (APRD and ACMP) for the ECAP_CAP1 and ECAP_CAP2 registers during APWM operation.