Table 6-530 lists the memory-mapped registers for the PRU_ICSSG_ECC_AGGR registers. All register offset addresses not listed in Table 6-530 should be considered as reserved locations and the register contents should not be modified.
Table 6-529 PRU_ICSSG_ECC_AGGR InstancesInstance | Base Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A000h |
PRU_ICSSG1_ECC_AGGR | 3F00 B000h |
Table 6-530 PRU_ICSSG_ECC_AGGR Registers 4.14.3.1 ICSSG_REV Register (Offset = 0h) [reset = 66A0E200h]
ICSSG_REV is shown in Figure 6-280 and described in Table 6-532.
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Revision parameters
Table 6-531 ICSSG_REV InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A000h |
PRU_ICSSG1_ECC_AGGR | 3F00 B000h |
Figure 6-280 ICSSG_REV Register LEGEND: R = Read Only; -n = value after reset |
Table 6-532 ICSSG_REV Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Ch | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
4.14.3.2 ICSSG_VECTOR Register (Offset = 8h) [reset = X]
ICSSG_VECTOR is shown in Figure 6-281 and described in Table 6-534.
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ECC Vector Register
Table 6-533 ICSSG_VECTOR InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A008h |
PRU_ICSSG1_ECC_AGGR | 3F00 B008h |
Figure 6-281 ICSSG_VECTOR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-534 ICSSG_VECTOR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
4.14.3.3 ICSSG_STAT Register (Offset = Ch) [reset = X]
ICSSG_STAT is shown in Figure 6-282 and described in Table 6-536.
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Misc Status
Table 6-535 ICSSG_STAT InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A00Ch |
PRU_ICSSG1_ECC_AGGR | 3F00 B00Ch |
Figure 6-282 ICSSG_STAT Register LEGEND: R = Read Only; -n = value after reset |
Table 6-536 ICSSG_STAT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 9h | Indicates the number of RAMS serviced by the ECC aggregator |
4.14.3.4 ICSSG_SEC_EOI_REG Register (Offset = 3Ch) [reset = X]
ICSSG_SEC_EOI_REG is shown in Figure 6-283 and described in Table 6-538.
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EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 6-537 ICSSG_SEC_EOI_REG InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A03Ch |
PRU_ICSSG1_ECC_AGGR | 3F00 B03Ch |
Figure 6-283 ICSSG_SEC_EOI_REG Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-538 ICSSG_SEC_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
4.14.3.5 ICSSG_SEC_STATUS_REG0 Register (Offset = 40h) [reset = X]
ICSSG_SEC_STATUS_REG0 is shown in Figure 6-284 and described in Table 6-540.
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Interrupt Status Register 0
Table 6-539 ICSSG_SEC_STATUS_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A040h |
PRU_ICSSG1_ECC_AGGR | 3F00 B040h |
Figure 6-284 ICSSG_SEC_STATUS_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-540 ICSSG_SEC_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_dram1_pend |
0 | PR1_DRAM0_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_dram0_pend |
4.14.3.6 ICSSG_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = X]
ICSSG_SEC_ENABLE_SET_REG0 is shown in Figure 6-285 and described in Table 6-542.
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Interrupt Enable Set Register 0
Table 6-541 ICSSG_SEC_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A080h |
PRU_ICSSG1_ECC_AGGR | 3F00 B080h |
Figure 6-285 ICSSG_SEC_ENABLE_SET_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-542 ICSSG_SEC_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_dram1_pend |
0 | PR1_DRAM0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_dram0_pend |
4.14.3.7 ICSSG_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = X]
ICSSG_SEC_ENABLE_CLR_REG0 is shown in Figure 6-286 and described in Table 6-544.
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Interrupt Enable Clear Register 0
Table 6-543 ICSSG_SEC_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A0C0h |
PRU_ICSSG1_ECC_AGGR | 3F00 B0C0h |
Figure 6-286 ICSSG_SEC_ENABLE_CLR_REG0 Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 6-544 ICSSG_SEC_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_dram1_pend |
0 | PR1_DRAM0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_dram0_pend |
4.14.3.8 ICSSG_DED_EOI_REG Register (Offset = 13Ch) [reset = X]
ICSSG_DED_EOI_REG is shown in Figure 6-287 and described in Table 6-546.
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EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 6-545 ICSSG_DED_EOI_REG InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A13Ch |
PRU_ICSSG1_ECC_AGGR | 3F00 B13Ch |
Figure 6-287 ICSSG_DED_EOI_REG Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-546 ICSSG_DED_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
4.14.3.9 ICSSG_DED_STATUS_REG0 Register (Offset = 140h) [reset = X]
ICSSG_DED_STATUS_REG0 is shown in Figure 6-288 and described in Table 6-548.
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Interrupt Status Register 0
Table 6-547 ICSSG_DED_STATUS_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A140h |
PRU_ICSSG1_ECC_AGGR | 3F00 B140h |
Figure 6-288 ICSSG_DED_STATUS_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-548 ICSSG_DED_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_dram1_pend |
0 | PR1_DRAM0_PEND | R/W1S | 0h | Interrupt Pending Status for pr1_dram0_pend |
4.14.3.10 ICSSG_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = X]
ICSSG_DED_ENABLE_SET_REG0 is shown in Figure 6-289 and described in Table 6-550.
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Interrupt Enable Set Register 0
Table 6-549 ICSSG_DED_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A180h |
PRU_ICSSG1_ECC_AGGR | 3F00 B180h |
Figure 6-289 ICSSG_DED_ENABLE_SET_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-550 ICSSG_DED_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_dram1_pend |
0 | PR1_DRAM0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for pr1_dram0_pend |
4.14.3.11 ICSSG_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = X]
ICSSG_DED_ENABLE_CLR_REG0 is shown in Figure 6-290 and described in Table 6-552.
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Interrupt Enable Clear Register 0
Table 6-551 ICSSG_DED_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A1C0h |
PRU_ICSSG1_ECC_AGGR | 3F00 B1C0h |
Figure 6-290 ICSSG_DED_ENABLE_CLR_REG0 Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 6-552 ICSSG_DED_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-9 | RESERVED | R/W | X | |
8 | PR1_PDSP_TX1_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp_tx1_iram_pend |
7 | PR1_PDSP_TX0_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp_tx0_iram_pend |
6 | PR1_RTU1_IRAM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_rtu1_iram_ecc_pend |
5 | PR1_RTU0_IRAM_ECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_rtu0_iram_ecc_pend |
4 | PR1_RAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_ram_pend |
3 | PR1_PDSP1_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp1_iram_pend |
2 | PR1_PDSP0_IRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_pdsp0_iram_pend |
1 | PR1_DRAM1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_dram1_pend |
0 | PR1_DRAM0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for pr1_dram0_pend |
4.14.3.12 ICSSG_AGGR_ENABLE_SET Register (Offset = 200h) [reset = X]
ICSSG_AGGR_ENABLE_SET is shown in Figure 6-291 and described in Table 6-554.
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AGGR interrupt enable set Register
Table 6-553 ICSSG_AGGR_ENABLE_SET InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A200h |
PRU_ICSSG1_ECC_AGGR | 3F00 B200h |
Figure 6-291 ICSSG_AGGR_ENABLE_SET Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 6-554 ICSSG_AGGR_ENABLE_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for SVBUS timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
4.14.3.13 ICSSG_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = X]
ICSSG_AGGR_ENABLE_CLR is shown in Figure 6-292 and described in Table 6-556.
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AGGR interrupt enable clear Register
Table 6-555 ICSSG_AGGR_ENABLE_CLR InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A204h |
PRU_ICSSG1_ECC_AGGR | 3F00 B204h |
Figure 6-292 ICSSG_AGGR_ENABLE_CLR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 6-556 ICSSG_AGGR_ENABLE_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for SVBUS timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
4.14.3.14 ICSSG_AGGR_STATUS_SET Register (Offset = 208h) [reset = X]
ICSSG_AGGR_STATUS_SET is shown in Figure 6-293 and described in Table 6-558.
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AGGR interrupt status set Register
Table 6-557 ICSSG_AGGR_STATUS_SET InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A208h |
PRU_ICSSG1_ECC_AGGR | 3F00 B208h |
Figure 6-293 ICSSG_AGGR_STATUS_SET Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-558 ICSSG_AGGR_STATUS_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/W | 0h | interrupt status set for SVBUS timeout errors |
1-0 | PARITY | R/W | 0h | interrupt status set for parity errors |
4.14.3.15 ICSSG_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = X]
ICSSG_AGGR_STATUS_CLR is shown in Figure 6-294 and described in Table 6-560.
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AGGR interrupt status clear Register
Table 6-559 ICSSG_AGGR_STATUS_CLR InstancesInstance | Physical Address |
---|
PRU_ICSSG0_ECC_AGGR | 3F00 A20Ch |
PRU_ICSSG1_ECC_AGGR | 3F00 B20Ch |
Figure 6-294 ICSSG_AGGR_STATUS_CLR Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 6-560 ICSSG_AGGR_STATUS_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/W | 0h | interrupt status clear for SVBUS timeout errors |
1-0 | PARITY | R/W | 0h | interrupt status clear for parity errors |