DDRSS0 does not support the following:
- DDR3 SDRAMs
- DDR3L SDRAMs
- DDR3U SDRAMs
- DIMM
- 1/2 width (8-bit) mode via software
configuration
- Data bus obfuscation or any other kind
of encryption
- Fail-safe reset I/O to maintain reset
state during SoC power OFF
- Independent operation of dual 16-bit
channels for LPDDR4
- The ECC engine of the DDR
controller
- LPDDR4x SDRAMs
- Automatic periodic scrubbing of SDRAM
for ECC
- Maximum of 17 row bits are supported
for LPDDR4. LPDDR4 with 18 row bits are not supported
- Only 1 rank designs are supported
- Only address range of up to 2GBytes is
supported
- LPDDR4 devices with byte mode die configurations