SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
RTU_PRU core can write and read data packets to and from port queues, located in the MSMC SRAM into PRU/RTU_PRU core registers via XFR2VBUS hardware accelerator. Each of the PRU_ICSSG Slices has implemented two sets of TX/RX XFR2VBUS hardware accelerators.
Supported features:
XFR2VBUS RX buffer features:
XFR2VBUS TX buffer features:
The ownership of commands and data is flexible. The XFR2VBUS accelerator is shared between RTU_PRU and PRU cores. Either RTU_PRU or PRU cores can own command or data. Status is available to both cores.
Note: The ownership should be preplanned and static per use model.
The XFR2VBUS is a simple hardware accelerator wich is used to get the lowest read round trip latency from MSMC and to decouple the latency seen by the PRU. Each XFR2VBUS instance is connected to the CBASS0.
The PRU_ICSSG system has a total of 4 XFR2VBUS TX/RX hardware accelerators and 2 extra XFR2VBUS RX only, attached to each of the TX_PRU cores.
The hardware has no protect nor arbitration between the 2 controllers, so it is the firmware responsibility to insure there is only one owner/access to a common address.