SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There are two MMCSD modules integrated in the device MAIN domain - MMCSD0 and MMCSD1. Figure 12-1742 shows the integration of MMCSD0 and MMCSD1.
Table 12-3427 through Table 12-3430 summarize the integration of MMCSD0 and MMCSD1 in the device MAIN domain.
Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
---|---|---|---|---|
MMCSD0 | PSC0 | PD0 | LPSC5 | CBASS0 |
MMCSD1 | PSC0 | PD0 | LPSC4 | CBASS0 |
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
---|---|---|---|---|
MMCSD0 | MMCSD0_ICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | MMCSD0 Interface Clock |
MMCSD0_FCLK | MAIN_PLL0_HSDIV5_CLKOUT (MMCSD0 default selection) |
PLL0_HSDIV5 | MMCSD0
Functional Clock (for more information about clock multiplexing, see CTRLMMR_EMMC0_CLKSEL[1-0] CLK_SEL bit field in Control Module (CTRL_MMR). Default: CTRLMMR_EMMC0_CLKSEL[1-0] CLK_SEL = 0, MAIN_PLL0_HSDIV5_CLKOUT is selected) |
|
MAIN_PLL2_HSDIV2_CLKOUT (MMCSD1 default selection) |
PLL2_HSDIV2 | |||
MMCSD1 | MMCSD1_ICLK | MAIN_SYSCLK0/2 | PLLCTRL0 | MMCSD1 Interface Clock |
MMCSD1_FCLK | MAIN_PLL0_HSDIV5_CLKOUT (MMCSD0 default selection) |
PLL0_HSDIV5 | MMCSD1
Functional Clock (for more information about clock multiplexing, see CTRLMMR_EMMC1_CLKSEL[1-0] CLK_SEL bit field in Control Module (CTRL_MMR). Default: CTRLMMR_EMMC1_CLKSEL[1-0] CLK_SEL = 0, MAIN_PLL0_HSDIV5_CLKOUT is selected) |
|
MAIN_PLL2_HSDIV2_CLKOUT (MMCSD1 default selection) |
PLL2_HSDIV2 |
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
---|---|---|---|---|
MMCSD0 | MMCSD0_RST | MOD_G_RST | LPSC5 | MMCSD0 Asynchronous Reset |
MMCSD1 | MMCSD1_RST | MOD_G_RST | LPSC4 | MMCSD1 Asynchronous Reset |
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
---|---|---|---|---|---|
MMCSD0 | MMCSD0_EMMCSS_INTR_0 | GICSS0_SPI_IN_165 | GICSS0 | MMCSD0 Interrupt Request | Level |
R5FSS0_CORE0_INTR_IN_165 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_165 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_165 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_165 | R5FSS1_CORE1 | ||||
MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0 | ESM0_LVL_IN_54 | ESM0 | MMCSD0 Receive ECC Correctable Error Interrupt Request | Level | |
MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_55 | ESM0 | MMCSD0 Receive ECC Uncorrectable Error Interrupt Request | Level | |
MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0 | ESM0_LVL_IN_56 | ESM0 | MMCSD0 Transmit ECC Correctable Error Interrupt Request | Level | |
MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_57 | ESM0 | MMCSD0 Transmit ECC Uncorrectable Error Interrupt Request | Level | |
MMCSD1 | MMCSD1_EMMCSDSS_INTR_0 | GICSS0_SPI_IN_166 | GICSS0 | MMCSD1 Interrupt Request | Level |
R5FSS0_CORE0_INTR_IN_166 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_166 | R5FSS0_CORE1 | ||||
R5FSS1_CORE0_INTR_IN_166 | R5FSS1_CORE0 | ||||
R5FSS1_CORE1_INTR_IN_166 | R5FSS1_CORE1 | ||||
MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0 | ESM0_LVL_IN_58 | ESM0 | MMCSD1 Receive ECC Correctable Error Interrupt Request | Level | |
MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_59 | ESM0 | MMCSD1 Receive ECC Uncorrectable Error Interrupt Request | Level | |
MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0 | ESM0_LVL_IN_60 | ESM0 | MMCSD1 Transmit ECC Correctable Error Interrupt Request | Level | |
MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0 | ESM0_LVL_IN_61 | ESM0 | MMCSD1 Transmit ECC Uncorrectable Error Interrupt Request | Level |