SPRUIM2H User guide | 德州仪器 TI.com.cn

Table 5-48 lists the memory-mapped registers for the CTRL_MMR0. All register offset addresses not listed in Table 5-48 should be considered as reserved locations and the register contents should not be modified.

Table 5-47 CTRL_MMR0 Instances

Instance	Base Address
CTRL_MMR0	4300 0000h

Table 5-48 CTRL_MMR0 Registers

Proxy0 Offset	Proxy1 Offset	Acronym	Register Name	CTRL_MMR0 Proxy0 Physical Address	CTRL_MMR0 Proxy1 Physical Address
0h	2000h	CTRLMMR_PID	Peripheral Identification Register	4300 0000h	4300 2000h
8h	2008h	CTRLMMR_MMR_CFG1	Configuration register 1	4300 0008h	4300 2008h
14h	2014h	CTRLMMR_JTAGID	JTAG / DEVICE ID Register	4300 0014h	4300 2014h
18h	2018h	CTRLMMR_JTAG_USER_ID	JTAG User Code ID Register	4300 0018h	4300 2018h
30h	2030h	CTRLMMR_MAIN_DEVSTAT	MAIN domain Device Status Register	4300 0030h	4300 2030h
34h	2034h	CTRLMMR_MAIN_BOOTCFG	MAIN domain Boot Configuration Register	4300 0034h	4300 2034h
60h	2060h	CTRLMMR_DEVICE_FEATURE0	Device Feature Register 0	4300 0060h	4300 2060h
68h	2068h	CTRLMMR_DEVICE_FEATURE2	Device Feature Register 2	4300 0068h	4300 2068h
78h	2078h	CTRLMMR_DEVICE_FEATURE6	Device Feature Register 6	4300 0078h	4300 2078h
200h	2200h	CTRLMMR_MAC_ID0	MAC Address Lo register	4300 0200h	4300 2200h
204h	2204h	CTRLMMR_MAC_ID1	MAC Address Hi Register	4300 0204h	4300 2204h
210h	2210h	CTRLMMR_PCI_DEVICE_ID0	PCI Device ID Register0	4300 0210h	4300 2210h
214h	2214h	CTRLMMR_PCI_DEVICE_ID1	PCI Device ID Register1	4300 0214h	4300 2214h
220h	2220h	CTRLMMR_USB_DEVICE_ID0	USB Device ID Register0	4300 0220h	4300 2220h
224h	2224h	CTRLMMR_USB_DEVICE_ID1	USB Device ID Register1	4300 0224h	4300 2224h
230h	2230h	CTRLMMR_GP_SW0	General Purpose Software Fuse Value 0	4300 0230h	4300 2230h
234h	2234h	CTRLMMR_GP_SW1	General Purpose Software Fuse Value 1	4300 0234h	4300 2234h
238h	2238h	CTRLMMR_GP_SW2	General Purpose Software Fuse Value 2	4300 0238h	4300 2238h
23Ch	223Ch	CTRLMMR_GP_SW3	General Purpose Software Fuse Value 3	4300 023Ch	4300 223Ch
270h	2270h	CTRLMMR_CBA_ERR_STAT	Bus Error Status	4300 0270h	4300 2270h
1008h	3008h	CTRLMMR_LOCK0_KICK0	Partition 0 Lock Key 0 Register	4300 1008h	4300 3008h
100Ch	300Ch	CTRLMMR_LOCK0_KICK1	Partition 0 Lock Key 1 Register	4300 100Ch	4300 300Ch
1010h	3010h	CTRLMMR_INTR_RAW_STAT	Interrupt Raw Status Register	4300 1010h	4300 3010h
1014h	3014h	CTRLMMR_INTR_STAT_CLR	Interrupt Status and Clear Register	4300 1014h	4300 3014h
1018h	3018h	CTRLMMR_INTR_EN_SET	Interrupt Enable Set Register	4300 1018h	4300 3018h
101Ch	301Ch	CTRLMMR_INTR_EN_CLR	Interrupt Enable Clear Register	4300 101Ch	4300 301Ch
1020h	3020h	CTRLMMR_EOI	End of Interrupt Register	4300 1020h	4300 3020h
1024h	3024h	CTRLMMR_FAULT_ADDR	Fault Address Register	4300 1024h	4300 3024h
1028h	3028h	CTRLMMR_FAULT_TYPE	Fault Type Register	4300 1028h	4300 3028h
102Ch	302Ch	CTRLMMR_FAULT_ATTR	Fault Attribute Register	4300 102Ch	4300 302Ch
1030h	3030h	CTRLMMR_FAULT_CLR	Fault Clear Register	4300 1030h	4300 3030h
1100h	3100h	CTRLMMR_P0_CLAIM0	Partition 0 Claim Register 0	4300 1100h	4300 3100h
1110h	3110h	CTRLMMR_P0_CLAIM4	Partition 0 Claim Register 4	4300 1110h	4300 3110h
4008h	6008h	CTRLMMR_USB0_PHY_CTRL	USB0 Phy Control Register	4300 4008h	4300 6008h
4044h	6044h	CTRLMMR_ENET1_CTRL	Ethernet1 Control Register	4300 4044h	4300 6044h
4048h	6048h	CTRLMMR_ENET2_CTRL	Ethernet2 Control Register	4300 4048h	4300 6048h
4070h	6070h	CTRLMMR_PCIE0_CTRL	PCEI0 Control Register	4300 4070h	4300 6070h
4080h	6080h	CTRLMMR_SERDES0_LN0_CTRL	SERDES0 Lane0 Control Register	4300 4080h	4300 6080h
40C0h	60C0h	CTRLMMR_ADC0_TRIM	ADC0 Trim Register	4300 40C0h	4300 60C0h
40E0h	60E0h	CTRLMMR_SERDES0_CTRL	SERDES0 Control Register	4300 40E0h	4300 60E0h
4100h	6100h	CTRLMMR_ICSSG0_CTRL0	ICSS_G0 Control Register 0	4300 4100h	4300 6100h
4104h	6104h	CTRLMMR_ICSSG0_CTRL1	ICSS_G0 Control Register 1	4300 4104h	4300 6104h
4110h	6110h	CTRLMMR_ICSSG1_CTRL0	ICSS_G1 Control Register 0	4300 4110h	4300 6110h
4114h	6114h	CTRLMMR_ICSSG1_CTRL1	ICSS_G1 Control Register 1	4300 4114h	4300 6114h
4130h	6130h	CTRLMMR_EPWM_TB_CLKEN	EPWM Time Base Clock Enable Register	4300 4130h	4300 6130h
4134h	6134h	CTRLMMR_EPWM_TB_CLKEN_SET	EPWM Time Base Clock Enable Set Register	4300 4134h	4300 6134h
4138h	6138h	CTRLMMR_EPWM_TB_CLKEN_CLR	EPWM Time Base Clock Enable Clear Register	4300 4138h	4300 6138h
4140h	6140h	CTRLMMR_EPWM0_CTRL	PWM0 Control Register	4300 4140h	4300 6140h
4144h	6144h	CTRLMMR_EPWM1_CTRL	PWM1 Control Register	4300 4144h	4300 6144h
4148h	6148h	CTRLMMR_EPWM2_CTRL	PWM2 Control Register	4300 4148h	4300 6148h
414Ch	614Ch	CTRLMMR_EPWM3_CTRL	PWM3 Control Register	4300 414Ch	4300 614Ch
4150h	6150h	CTRLMMR_EPWM4_CTRL	PWM4 Control Register	4300 4150h	4300 6150h
4154h	6154h	CTRLMMR_EPWM5_CTRL	PWM5 Control Register	4300 4154h	4300 6154h
4158h	6158h	CTRLMMR_EPWM6_CTRL	PWM6 Control Register	4300 4158h	4300 6158h
415Ch	615Ch	CTRLMMR_EPWM7_CTRL	PWM7 Control Register	4300 415Ch	4300 615Ch
4160h	6160h	CTRLMMR_EPWM8_CTRL	PWM8 Control Register	4300 4160h	4300 6160h
4170h	6170h	CTRLMMR_SOCA_SEL	PWM SOCA Select Register	4300 4170h	4300 6170h
4174h	6174h	CTRLMMR_SOCB_SEL	PWM SOCB Select Register	4300 4174h	4300 6174h
4180h	6180h	CTRLMMR_EQEP0_CTRL	EQEP SOCA Select Register	4300 4180h	4300 6180h
4184h	6184h	CTRLMMR_EQEP1_CTRL	EQEP SOCA Select Register	4300 4184h	4300 6184h
4188h	6188h	CTRLMMR_EQEP2_CTRL	EQEP SOCA Select Register	4300 4188h	4300 6188h
41A0h	61A0h	CTRLMMR_EQEP_STAT	EQEP Status Register	4300 41A0h	4300 61A0h
41B4h	61B4h	CTRLMMR_SDIO1_CTRL	SDIO1 Control Register	4300 41B4h	4300 61B4h
4204h	6204h	CTRLMMR_TIMER1_CTRL	TIMER1 Control Register	4300 4204h	4300 6204h
420Ch	620Ch	CTRLMMR_TIMER3_CTRL	TIMER3 Control Register	4300 420Ch	4300 620Ch
4214h	6214h	CTRLMMR_TIMER5_CTRL	TIMER5 Control Register	4300 4214h	4300 6214h
421Ch	621Ch	CTRLMMR_TIMER7_CTRL	TIMER7 Control Register	4300 421Ch	4300 621Ch
4224h	6224h	CTRLMMR_TIMER9_CTRL	TIMER9 Control Register	4300 4224h	4300 6224h
422Ch	622Ch	CTRLMMR_TIMER11_CTRL	TIMER11 Control Register	4300 422Ch	4300 622Ch
42E0h	62E0h	CTRLMMR_I2C0_CTRL	I2C0 Control Register	4300 42E0h	4300 62E0h
4700h	6700h	CTRLMMR_FSS_CTRL	Flash Subsystem Control Register	4300 4700h	4300 6700h
4710h	6710h	CTRLMMR_ADC0_CTRL	ADC0 Control Register	4300 4710h	4300 6710h
4750h	6750h	CTRLMMR_DCC_STAT	DCC Status Register	4300 4750h	4300 6750h
5008h	7008h	CTRLMMR_LOCK1_KICK0	Partition 1 Lock Key 0 Register	4300 5008h	4300 7008h
500Ch	700Ch	CTRLMMR_LOCK1_KICK1	Partition 1 Lock Key 1 Register	4300 500Ch	4300 700Ch
5100h	7100h	CTRLMMR_P1_CLAIM0	Partition 1 Claim Register 0	4300 5100h	4300 7100h
5104h	7104h	CTRLMMR_P1_CLAIM1	Partition 1 Claim Register 1	4300 5104h	4300 7104h
5108h	7108h	CTRLMMR_P1_CLAIM2	Partition 1 Claim Register 2	4300 5108h	4300 7108h
510Ch	710Ch	CTRLMMR_P1_CLAIM3	Partition 1 Claim Register 3	4300 510Ch	4300 710Ch
5110h	7110h	CTRLMMR_P1_CLAIM4	Partition 1 Claim Register 4	4300 5110h	4300 7110h
5114h	7114h	CTRLMMR_P1_CLAIM5	Partition 1 Claim Register 5	4300 5114h	4300 7114h
5130h	7130h	CTRLMMR_P1_CLAIM12	Partition 1 Claim Register 12	4300 5130h	4300 7130h
5134h	7134h	CTRLMMR_P1_CLAIM13	Partition 1 Claim Register 13	4300 5134h	4300 7134h
5138h	7138h	CTRLMMR_P1_CLAIM14	Partition 1 Claim Register 14	4300 5138h	4300 7138h
8000h	A000h	CTRLMMR_OBSCLK0_CTRL	Observe Clock 0 Output Control Register	4300 8000h	4300 A000h
8010h	A010h	CTRLMMR_CLKOUT_CTRL	CLKOUT Control Register	4300 8010h	4300 A010h
8030h	A030h	CTRLMMR_GTC_CLKSEL	GTC Clock Select Register	4300 8030h	4300 A030h
803Ch	A03Ch	CTRLMMR_EFUSE_CLKSEL	Main eFuse Controller Clock Select Register	4300 803Ch	4300 A03Ch
8040h	A040h	CTRLMMR_ICSSG0_CLKSEL	ICSS_G0 Clock Select Register	4300 8040h	4300 A040h
8044h	A044h	CTRLMMR_ICSSG1_CLKSEL	ICSS_G1 Clock Select Register	4300 8044h	4300 A044h
8060h	A060h	CTRLMMR_MAIN_PLL0_CLKSEL	MAIN PLL0 Source Clock Select Register	4300 8060h	4300 A060h
8064h	A064h	CTRLMMR_MAIN_PLL1_CLKSEL	MAIN PLL1 Source Clock Select Register	4300 8064h	4300 A064h
8068h	A068h	CTRLMMR_MAIN_PLL2_CLKSEL	MAIN PLL2 Source Clock Select Register	4300 8068h	4300 A068h
8080h	A080h	CTRLMMR_MAIN_PLL8_CLKSEL	MAIN PLL8 Source Clock Select Register	4300 8080h	4300 A080h
8090h	A090h	CTRLMMR_MAIN_PLL12_CLKSEL	MAIN PLL12 Source Clock Select Register	4300 8090h	4300 A090h
8098h	A098h	CTRLMMR_MAIN_PLL14_CLKSEL	MAIN PLL14 Source Clock Select Register	4300 8098h	4300 A098h
8120h	A120h	CTRLMMR_PCIE0_CLKSEL	PCIE0 Clock Select Register	4300 8120h	4300 A120h
8140h	A140h	CTRLMMR_CPSW_CLKSEL	CPSW Clock Select Register	4300 8140h	4300 A140h
8150h	A150h	CTRLMMR_CPTS_CLKSEL	CPTS Clock Select Register	4300 8150h	4300 A150h
8160h	A160h	CTRLMMR_EMMC0_CLKSEL	eMMC0 Clock Select Register	4300 8160h	4300 A160h
8168h	A168h	CTRLMMR_EMMC1_CLKSEL	eMMC1 Clock Select Register	4300 8168h	4300 A168h
8180h	A180h	CTRLMMR_GPMC_CLKSEL	GPMC Clock Select Register	4300 8180h	4300 A180h
8190h	A190h	CTRLMMR_USB0_CLKSEL	USB0 Clock Select Register	4300 8190h	4300 A190h
81B0h	A1B0h	CTRLMMR_TIMER0_CLKSEL	Timer0 Clock Select Register	4300 81B0h	4300 A1B0h
81B4h	A1B4h	CTRLMMR_TIMER1_CLKSEL	Timer1 Clock Select Register	4300 81B4h	4300 A1B4h
81B8h	A1B8h	CTRLMMR_TIMER2_CLKSEL	Timer2 Clock Select Register	4300 81B8h	4300 A1B8h
81BCh	A1BCh	CTRLMMR_TIMER3_CLKSEL	Timer3 Clock Select Register	4300 81BCh	4300 A1BCh
81C0h	A1C0h	CTRLMMR_TIMER4_CLKSEL	Timer4 Clock Select Register	4300 81C0h	4300 A1C0h
81C4h	A1C4h	CTRLMMR_TIMER5_CLKSEL	Timer5 Clock Select Register	4300 81C4h	4300 A1C4h
81C8h	A1C8h	CTRLMMR_TIMER6_CLKSEL	Timer6 Clock Select Register	4300 81C8h	4300 A1C8h
81CCh	A1CCh	CTRLMMR_TIMER7_CLKSEL	Timer7 Clock Select Register	4300 81CCh	4300 A1CCh
81D0h	A1D0h	CTRLMMR_TIMER8_CLKSEL	Timer8 Clock Select Register	4300 81D0h	4300 A1D0h
81D4h	A1D4h	CTRLMMR_TIMER9_CLKSEL	Timer9 Clock Select Register	4300 81D4h	4300 A1D4h
81D8h	A1D8h	CTRLMMR_TIMER10_CLKSEL	Timer10 Clock Select Register	4300 81D8h	4300 A1D8h
81DCh	A1DCh	CTRLMMR_TIMER11_CLKSEL	Timer11 Clock Select Register	4300 81DCh	4300 A1DCh
8200h	A200h	CTRLMMR_SPI0_CLKSEL	SPI0 Clock Select Register	4300 8200h	4300 A200h
8204h	A204h	CTRLMMR_SPI1_CLKSEL	SPI1 Clock Select Register	4300 8204h	4300 A204h
8208h	A208h	CTRLMMR_SPI2_CLKSEL	SPI2 Clock Select Register	4300 8208h	4300 A208h
820Ch	A20Ch	CTRLMMR_SPI3_CLKSEL	SPI3 Clock Select Register	4300 820Ch	4300 A20Ch
8210h	A210h	CTRLMMR_SPI4_CLKSEL	SPI4 Clock Select Register	4300 8210h	4300 A210h
8240h	A240h	CTRLMMR_USART0_CLK_CTRL	USART0 Functional Clock Control	4300 8240h	4300 A240h
8244h	A244h	CTRLMMR_USART1_CLK_CTRL	USART1 Functional Clock Control	4300 8244h	4300 A244h
8248h	A248h	CTRLMMR_USART2_CLK_CTRL	USART2 Functional Clock Control	4300 8248h	4300 A248h
824Ch	A24Ch	CTRLMMR_USART3_CLK_CTRL	USART3 Functional Clock Control	4300 824Ch	4300 A24Ch
8250h	A250h	CTRLMMR_USART4_CLK_CTRL	USART4 Functional Clock Control	4300 8250h	4300 A250h
8254h	A254h	CTRLMMR_USART5_CLK_CTRL	USART5 Functional Clock Control	4300 8254h	4300 A254h
8258h	A258h	CTRLMMR_USART6_CLK_CTRL	USART6 Functional Clock Control	4300 8258h	4300 A258h
8280h	A280h	CTRLMMR_USART0_CLKSEL	USART0 Functional Clock Control	4300 8280h	4300 A280h
8284h	A284h	CTRLMMR_USART1_CLKSEL	USART1 Functional Clock Control	4300 8284h	4300 A284h
8288h	A288h	CTRLMMR_USART2_CLKSEL	USART2 Functional Clock Control	4300 8288h	4300 A288h
828Ch	A28Ch	CTRLMMR_USART3_CLKSEL	USART3 Functional Clock Control	4300 828Ch	4300 A28Ch
8290h	A290h	CTRLMMR_USART4_CLKSEL	USART4 Functional Clock Control	4300 8290h	4300 A290h
8294h	A294h	CTRLMMR_USART5_CLKSEL	USART5 Functional Clock Control	4300 8294h	4300 A294h
8298h	A298h	CTRLMMR_USART6_CLKSEL	USART6 Functional Clock Control	4300 8298h	4300 A298h
8380h	A380h	CTRLMMR_WWD0_CLKSEL	WWD0 Clock Select Register	4300 8380h	4300 A380h
8384h	A384h	CTRLMMR_WWD1_CLKSEL	WWD1 Clock Select Register	4300 8384h	4300 A384h
83A0h	A3A0h	CTRLMMR_WWD8_CLKSEL	WWD8 Clock Select Register	4300 83A0h	4300 A3A0h
83A4h	A3A4h	CTRLMMR_WWD9_CLKSEL	WWD9 Clock Select Register	4300 83A4h	4300 A3A4h
83A8h	A3A8h	CTRLMMR_WWD10_CLKSEL	WWD10 Clock Select Register	4300 83A8h	4300 A3A8h
83ACh	A3ACh	CTRLMMR_WWD11_CLKSEL	WWD11 Clock Select Register	4300 83ACh	4300 A3ACh
8400h	A400h	CTRLMMR_SERDES0_CLKSEL	SERDES 0 Clock Select Register	4300 8400h	4300 A400h
8480h	A480h	CTRLMMR_MCAN0_CLKSEL	MCAN0 Clock Select Register	4300 8480h	4300 A480h
8484h	A484h	CTRLMMR_MCAN1_CLKSEL	MCAN1 Clock Select Register	4300 8484h	4300 A484h
8500h	A500h	CTRLMMR_OSPI0_CLKSEL	OSPI Clock Select Register	4300 8500h	4300 A500h
8510h	A510h	CTRLMMR_ADC0_CLKSEL	ADC0 Clock Select Register	4300 8510h	4300 A510h
9008h	B008h	CTRLMMR_LOCK2_KICK0	Partition 2 Lock Key 0 Register	4300 9008h	4300 B008h
900Ch	B00Ch	CTRLMMR_LOCK2_KICK1	Partition 2 Lock Key 1 Register	4300 900Ch	4300 B00Ch
9100h	B100h	CTRLMMR_P2_CLAIM0	Partition 2 Claim Register 0	4300 9100h	4300 B100h
9104h	B104h	CTRLMMR_P2_CLAIM1	Partition 2 Claim Register 1	4300 9104h	4300 B104h
9108h	B108h	CTRLMMR_P2_CLAIM2	Partition 2 Claim Register 2	4300 9108h	4300 B108h
910Ch	B10Ch	CTRLMMR_P2_CLAIM3	Partition 2 Claim Register 3	4300 910Ch	4300 B10Ch
9110h	B110h	CTRLMMR_P2_CLAIM4	Partition 2 Claim Register 4	4300 9110h	4300 B110h
9114h	B114h	CTRLMMR_P2_CLAIM5	Partition 2 Claim Register 5	4300 9114h	4300 B114h
9118h	B118h	CTRLMMR_P2_CLAIM6	Partition 2 Claim Register 6	4300 9118h	4300 B118h
911Ch	B11Ch	CTRLMMR_P2_CLAIM7	Partition 2 Claim Register 7	4300 911Ch	4300 B11Ch
9120h	B120h	CTRLMMR_P2_CLAIM8	Partition 2 Claim Register 8	4300 9120h	4300 B120h
9124h	B124h	CTRLMMR_P2_CLAIM9	Partition 2 Claim Register 9	4300 9124h	4300 B124h
9128h	B128h	CTRLMMR_P2_CLAIM10	Partition 2 Claim Register 10	4300 9128h	4300 B128h
C320h	E320h	CTRLMMR_FUSE_CRC_STAT	MAIN eFUse CRC Status Register	4300 C320h	4300 E320h
C400h	E400h	CTRLMMR_PBIST_EN	PBIST Enable Register	4300 C400h	4300 E400h
D008h	F008h	CTRLMMR_LOCK3_KICK0	Partition 3 Lock Key 0 Register	4300 D008h	4300 F008h
D00Ch	F00Ch	CTRLMMR_LOCK3_KICK1	Partition 3 Lock Key 1 Register	4300 D00Ch	4300 F00Ch
D118h	F118h	CTRLMMR_P3_CLAIM6	Partition 3 Claim Register 6	4300 D118h	4300 F118h
14000h	16000h	CTRLMMR_CHNG_DDR4_FSP_REQ	Change LPDDR4 FSP Request Register	4301 4000h	4301 6000h
14004h	16004h	CTRLMMR_CHNG_DDR4_FSP_ACK	Change LPDDR4 FSP Acknowledge Register	4301 4004h	4301 6004h
14080h	16080h	CTRLMMR_DDR4_FSP_CLKCHNG_REQ	LPDDR4 FSP Clock Change Request Register	4301 4080h	4301 6080h
140C0h	160C0h	CTRLMMR_DDR4_FSP_CLKCHNG_ACK	LPDDR4 FSP Clock Change Acknowledge Register	4301 40C0h	4301 60C0h
15008h	17008h	CTRLMMR_LOCK5_KICK0	Partition 5 Lock Key 0 Register	4301 5008h	4301 7008h
1500Ch	1700Ch	CTRLMMR_LOCK5_KICK1	Partition 5 Lock Key 1 Register	4301 500Ch	4301 700Ch
15100h	17100h	CTRLMMR_P5_CLAIM0	Partition 5 Claim Register 0	4301 5100h	4301 7100h
15104h	17104h	CTRLMMR_P5_CLAIM1	Partition 5 Claim Register 1	4301 5104h	4301 7104h
18170h	1A170h	CTRLMMR_RST_CTRL	Reset Control Register	4301 8170h	4301 A170h
18174h	1A174h	CTRLMMR_RST_STAT	Reset Status Register	4301 8174h	4301 A174h
18178h	1A178h	CTRLMMR_RST_SRC	Reset Source Register	4301 8178h	4301 A178h
1817Ch	1A17Ch	CTRLMMR_RST_MAGIC_WORD	Magic Word	4301 817Ch	4301 A17Ch
19008h	1B008h	CTRLMMR_LOCK6_KICK0	Partition 6 Lock Key 0 Register	4301 9008h	4301 B008h
1900Ch	1B00Ch	CTRLMMR_LOCK6_KICK1	Partition 6 Lock Key 1 Register	4301 900Ch	4301 B00Ch
19108h	1B108h	CTRLMMR_P6_CLAIM2	Partition 6 Claim Register 2	4301 9108h	4301 B108h

1.1.5.1 CTRLMMR_PID Register (Proxy0 Offset = 0h; Proxy1 Offset = 2000h) [reset = 61800000h]

CTRLMMR_PID is shown in Figure 5-17 and described in Table 5-50.

Return to Summary Table.

Peripheral release details.

Table 5-49 CTRLMMR_PID Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0000h	4300 2000h

Figure 5-17 CTRLMMR_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-180h

23	22	21	20	19	18	17	16
FUNC
R-180h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-50 CTRLMMR_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	CTRLMMR_PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	180h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number
10-8	X_MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	Custom revision number
5-0	Y_MINOR	R	0h	Minor revision number

1.1.5.2 CTRLMMR_MMR_CFG1 Register (Proxy0 Offset = 8h; Proxy1 Offset = 2008h) [reset = 800000BFh]

CTRLMMR_MMR_CFG1 is shown in Figure 5-18 and described in Table 5-52.

Return to Summary Table.

Indicates the MMR configuration.

Table 5-51 CTRLMMR_MMR_CFG1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0008h	4300 2008h

Figure 5-18 CTRLMMR_MMR_CFG1 Register

31	30	29	28	27	26	25	24
PROXY_EN	RESERVED
R-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
PARTITIONS
R-BFh

LEGEND: R = Read Only; -n = value after reset

Table 5-52 CTRLMMR_MMR_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PROXY_EN	R	1h	Proxy addressing enabled
30-8	RESERVED	R	0h	Reserved
7-0	PARTITIONS	R	BFh	Indicates present partitions

1.1.5.3 CTRLMMR_JTAGID Register (Proxy0 Offset = 14h; Proxy1 Offset = 2014h) [reset = BB3802Fh]

CTRLMMR_JTAGID is shown in Figure 5-19 and described in Table 5-54.

Return to Summary Table.

The CTRLMMR_JTAGID register must be readable by the configuration bus so that this can be accessed via the JTAG and CPU. In Boundary Scan mode, this ID should also be readable with only TCLK present. This means without a valid CPU clock running and also implies that Fusefarm scan is not necessary. The partno and variant field inputs should be set in the top metal mask so that this may be changed if a future PG is necessary. All other fields may be hard coded.

Table 5-53 CTRLMMR_JTAGID Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0014h	4300 2014h

Figure 5-19 CTRLMMR_JTAGID Register

31	30	29	28	27	26	25	24
VARIANT				PARTNO
R-0h				R-BB38h

23	22	21	20	19	18	17	16
PARTNO
R-BB38h

15	14	13	12	11	10	9	8
PARTNO				MFG
R-BB38h				R-17h

7	6	5	4	3	2	1	0
MFG							LSB
R-17h							R-1h

LEGEND: R = Read Only; -n = value after reset

Table 5-54 CTRLMMR_JTAGID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	VARIANT	R	0h	Used to indicate new PGs
27-12	PARTNO	R	BB38h	Part number for boundary scan
11-1	MFG	R	17h	Indicates manufacturer
0	LSB	R	1h	Always 1

1.1.5.4 CTRLMMR_JTAG_USER_ID Register (Proxy0 Offset = 18h; Proxy1 Offset = 2018h) [reset = BB3802Fh]

CTRLMMR_JTAG_USER_ID is shown in Figure 5-20 and described in Table 5-56.

Return to Summary Table.

Table 5-55 CTRLMMR_JTAG_USER_ID Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0018h	4300 2018h

Figure 5-20 CTRLMMR_JTAG_USER_ID Register

31	30	29	28	27	26	25	24
DEVICE_ID
R

23	22	21	20	19	18	17	16
DEVICE_ID
R

15	14	13	12	11	10	9	8
DEVICE_ID			SECURITY	SAFETY	SPEED
R			R	R	R

7	6	5	4	3	2	1	0
SPEED		TEMP			PKG
R		R			R

LEGEND: R = Read Only; -n = value after reset

Table 5-56 CTRLMMR_JTAG_USER_ID Register Field Descriptions

Bit	Field	Type	Description
31-13	DEVICE_ID	R	Base Part Number See device comparison table in device specific datasheet for details.
12	SECURITY	R	0h = Non-Secure 1h = Secure
11	SAFETY	R	0h = Non-Functional Safety 1h = Functional Safety
10-6	SPEED	R	Device Speed Grade 1 (1h) = A Speed Designator 2 (2h) = B Speed Designator ... 25 (19h) = Y Speed Designator 26 (1Ah) = Z Speed Designator
5-3	TEMP	R	Temperature Grade 3h = 0°C to 90°C 4h = -40°C to 105°C 5h = -40°C to 125°C Others = Reserved
2-0	PKG	R	Device Package Type 4h = ALV 5h = ALX

1.1.5.5 CTRLMMR_MAIN_DEVSTAT Register (Proxy0 Offset = 30h; Proxy1 Offset = 2030h) [reset = X]

CTRLMMR_MAIN_DEVSTAT is shown in Figure 5-21 and described in Table 5-58.

Return to Summary Table.

Indicates SoC bootstrap selection. The default value of this register is determined by the SoC bootstrap pins.

Table 5-57 CTRLMMR_MAIN_DEVSTAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0030h	4300 2030h

Figure 5-21 CTRLMMR_MAIN_DEVSTAT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																BOOTMODE
R-0h																R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-58 CTRLMMR_MAIN_DEVSTAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	BOOTMODE	R/W	X	Specifies the device Primary and Backup boot media.

1.1.5.6 CTRLMMR_MAIN_BOOTCFG Register (Proxy0 Offset = 34h; Proxy1 Offset = 2034h) [reset = X]

CTRLMMR_MAIN_BOOTCFG is shown in Figure 5-22 and described in Table 5-60.

Return to Summary Table.

Indicates SoC bootstrap selection latched at power-on reset. The default value of this register is determined by the SoC bootstrap pins.

Table 5-59 CTRLMMR_MAIN_BOOTCFG Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0034h	4300 2034h

Figure 5-22 CTRLMMR_MAIN_BOOTCFG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																BOOTMODE
R-0h																R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-60 CTRLMMR_MAIN_BOOTCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	BOOTMODE	R	X	Specifies the device Primary and Backup boot media as latched at PORz

1.1.5.7 CTRLMMR_DEVICE_FEATURE0 Register (Proxy0 Offset = 60h; Proxy1 Offset = 2060h) [reset = X]

CTRLMMR_DEVICE_FEATURE0 is shown in Figure 5-23 and described in Table 5-62.

Return to Summary Table.

Indicates enabled MAIN domain processing elements on the device.

Table 5-61 CTRLMMR_DEVICE_FEATURE0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0060h	4300 2060h

Figure 5-23 CTRLMMR_DEVICE_FEATURE0 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED				R5FSS1_CORE1	R5FSS1_CORE0	R5FSS0_CORE1	R5FSS0_CORE0
R-0h				R-X	R-X	R-X	R-X

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						MPU_CLUSTER0_CORE1	MPU_CLUSTER0_CORE0
R-0h						R-X	R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-62 CTRLMMR_DEVICE_FEATURE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	0h	Reserved
19	R5FSS1_CORE1	R	X	Dual/Single CPU Support R5FSS1 1 = Both Dual and Single CPU operation is supported 0 = Only Single CPU operation is supported
18	R5FSS1_CORE0	R	X	unused
17	R5FSS0_CORE1	R	X	Dual/Single CPU Support R5FSS0 1 = Both Dual and Single CPU operation is supported 0 = Only Single CPU operation is supported
16	R5FSS0_CORE0	R	X	unused
15-2	RESERVED	R	0h	Reserved
1	MPU_CLUSTER0_CORE1	R	X	MPU Cluster0 Core 1 is enabled when set
0	MPU_CLUSTER0_CORE0	R	X	MPU Cluster0 Core 0 is enabled when set

1.1.5.8 CTRLMMR_DEVICE_FEATURE2 Register (Proxy0 Offset = 68h; Proxy1 Offset = 2068h) [reset = X]

CTRLMMR_DEVICE_FEATURE2 is shown in Figure 5-24 and described in Table 5-64.

Return to Summary Table.

Indicates enabled MCU domain interface elements on the device.

Table 5-63 CTRLMMR_DEVICE_FEATURE2 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0068h	4300 2068h

Figure 5-24 CTRLMMR_DEVICE_FEATURE2 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED					CRYPTO_PKA_EN	CRYPTO_ENCR_EN	CRYPTO_SHA_EN
R-0h					R-X	R-X	R-X

7	6	5	4	3	2	1	0
AES_AUTH_EN	RESERVED						MCAN_FD_MODE
R-X	R-0h						R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-64 CTRLMMR_DEVICE_FEATURE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10	CRYPTO_PKA_EN	R	X	SA2_UL Crypto Module PKA enabled
9	CRYPTO_ENCR_EN	R	X	SA2_UL Crypto Module AES/3DES/DBRG enabled
8	CRYPTO_SHA_EN	R	X	SA2_UL Crypto Module SHA/MD5 enabled
7	AES_AUTH_EN	R	X	AES authentication is enabled in FlashSS and DMSC when set
6-1	RESERVED	R	0h	Reserved
0	MCAN_FD_MODE	R	X	FD mode is supported on MCAN[1:0] when set

1.1.5.9 CTRLMMR_DEVICE_FEATURE6 Register (Proxy0 Offset = 78h; Proxy1 Offset = 2078h) [reset = X]

CTRLMMR_DEVICE_FEATURE6 is shown in Figure 5-25 and described in Table 5-66.

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Indicates enabled MAIN domain interface elements on the device.

Table 5-65 CTRLMMR_DEVICE_FEATURE6 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0078h	4300 2078h

Figure 5-25 CTRLMMR_DEVICE_FEATURE6 Register

31	30	29	28	27	26	25	24
RESERVED					MAIN_RESERVED_2	MAIN_RESERVED_1	MAIN_RESERVED_0
R-0h					R-X	R-X	R-X

23	22	21	20	19	18	17	16
RESERVED						SPARE1	SPARE0
R-0h						R-X	R-X

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		SA2_UL	RESERVED
R-0h		R-X	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-66 CTRLMMR_DEVICE_FEATURE6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26	MAIN_RESERVED_2	R	X	MAIN domain Reserved 2 LPSC is enabled when set
25	MAIN_RESERVED_1	R	X	MAIN domain Reserved 1 LPSC is enabled when set
24	MAIN_RESERVED_0	R	X	MAIN domain Reserved 0 LPSC is enabled when set
23-18	RESERVED	R	0h	Reserved
17	SPARE1	R	X	Spare1 LPSC is enabled when set
16	SPARE0	R	X	Spare0 LPSC is enabled when set
15-6	RESERVED	R	0h	Reserved
5	SA2_UL	R	X	MAIN domain security accelerator is enabled when set
4-0	RESERVED	R	0h	Reserved

1.1.5.10 CTRLMMR_MAC_ID0 Register (Proxy0 Offset = 200h; Proxy1 Offset = 2200h) [reset = X]

CTRLMMR_MAC_ID0 is shown in Figure 5-26 and described in Table 5-68.

Return to Summary Table.

Ethernet MAC address lower 32-bits.

Table 5-67 CTRLMMR_MAC_ID0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0200h	4300 2200h

Figure 5-26 CTRLMMR_MAC_ID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MACID_LO
R/W-X

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-68 CTRLMMR_MAC_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MACID_LO	R/W	X	32 lsbs of MAC address

1.1.5.11 CTRLMMR_MAC_ID1 Register (Proxy0 Offset = 204h; Proxy1 Offset = 2204h) [reset = X]

CTRLMMR_MAC_ID1 is shown in Figure 5-27 and described in Table 5-70.

Return to Summary Table.

Ethernet MAC address upper 16-bits.

Table 5-69 CTRLMMR_MAC_ID1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0204h	4300 2204h

Figure 5-27 CTRLMMR_MAC_ID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																MACID_HI
R-0h																R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-70 CTRLMMR_MAC_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	MACID_HI	R/W	X	16 msbs of MAC address

1.1.5.12 CTRLMMR_PCI_DEVICE_ID0 Register (Proxy0 Offset = 210h; Proxy1 Offset = 2210h) [reset = B010104Ch]

CTRLMMR_PCI_DEVICE_ID0 is shown in Figure 5-28 and described in Table 5-72.

Return to Summary Table.

PCIe device ID and vendor ID register 0.

Table 5-71 CTRLMMR_PCI_DEVICE_ID0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0210h	4300 2210h

Figure 5-28 CTRLMMR_PCI_DEVICE_ID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID0
R/W-B010104Ch

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-72 CTRLMMR_PCI_DEVICE_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID0	R/W	B010104Ch	ROM can optionally update this register with a 32 bit value from Customer OTP

1.1.5.13 CTRLMMR_PCI_DEVICE_ID1 Register (Proxy0 Offset = 214h; Proxy1 Offset = 2214h) [reset = B010104Ch]

CTRLMMR_PCI_DEVICE_ID1 is shown in Figure 5-29 and described in Table 5-74.

Return to Summary Table.

PCIe device ID and vendor ID register 1.

Table 5-73 CTRLMMR_PCI_DEVICE_ID1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0214h	4300 2214h

Figure 5-29 CTRLMMR_PCI_DEVICE_ID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID1
R/W-B010104Ch

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-74 CTRLMMR_PCI_DEVICE_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID1	R/W	B010104Ch	ROM can optionally update this register with a 32 bit value from Customer OTP

1.1.5.14 CTRLMMR_USB_DEVICE_ID0 Register (Proxy0 Offset = 220h; Proxy1 Offset = 2220h) [reset = 61650451h]

CTRLMMR_USB_DEVICE_ID0 is shown in Figure 5-30 and described in Table 5-76.

Return to Summary Table.

USB device and vendor ID register 0.

Table 5-75 CTRLMMR_USB_DEVICE_ID0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0220h	4300 2220h

Figure 5-30 CTRLMMR_USB_DEVICE_ID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID0
R/W-61650451h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-76 CTRLMMR_USB_DEVICE_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID0	R/W	61650451h	ROM can optionally update this register with a 32 bit value from Customer OTP

1.1.5.15 CTRLMMR_USB_DEVICE_ID1 Register (Proxy0 Offset = 224h; Proxy1 Offset = 2224h) [reset = 61650451h]

CTRLMMR_USB_DEVICE_ID1 is shown in Figure 5-31 and described in Table 5-78.

Return to Summary Table.

USB device and vendor ID register 1.

Table 5-77 CTRLMMR_USB_DEVICE_ID1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0224h	4300 2224h

Figure 5-31 CTRLMMR_USB_DEVICE_ID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID1
R/W-61650451h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-78 CTRLMMR_USB_DEVICE_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID1	R/W	61650451h	ROM can optionally update this register with a 32 bit value from Customer OTP

1.1.5.16 CTRLMMR_GP_SW0 Register (Proxy0 Offset = 230h; Proxy1 Offset = 2230h) [reset = X]

CTRLMMR_GP_SW0 is shown in Figure 5-32 and described in Table 5-80.

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Allocated for customer use - Ex. Storage of CTRLMMR_PID/VID, Model #, Etc.

Table 5-79 CTRLMMR_GP_SW0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0230h	4300 2230h

Figure 5-32 CTRLMMR_GP_SW0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-80 CTRLMMR_GP_SW0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	X	general purpose value

1.1.5.17 CTRLMMR_GP_SW1 Register (Proxy0 Offset = 234h; Proxy1 Offset = 2234h) [reset = X]

CTRLMMR_GP_SW1 is shown in Figure 5-33 and described in Table 5-82.

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Allocated for customer use - Ex. Storage of CTRLMMR_PID/VID, Model #, Etc.

Table 5-81 CTRLMMR_GP_SW1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0234h	4300 2234h

Figure 5-33 CTRLMMR_GP_SW1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-82 CTRLMMR_GP_SW1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	X	general purpose value

1.1.5.18 CTRLMMR_GP_SW2 Register (Proxy0 Offset = 238h; Proxy1 Offset = 2238h) [reset = X]

CTRLMMR_GP_SW2 is shown in Figure 5-34 and described in Table 5-84.

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Allocated for customer use - Ex. Storage of CTRLMMR_PID/VID, Model #, Etc.

Table 5-83 CTRLMMR_GP_SW2 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0238h	4300 2238h

Figure 5-34 CTRLMMR_GP_SW2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-84 CTRLMMR_GP_SW2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	VAL	R	X	general purpose value

1.1.5.19 CTRLMMR_GP_SW3 Register (Proxy0 Offset = 23Ch; Proxy1 Offset = 223Ch) [reset = X]

CTRLMMR_GP_SW3 is shown in Figure 5-35 and described in Table 5-86.

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Allocated for customer use - Ex. Storage of CTRLMMR_PID/VID, Model #, Etc.

Table 5-85 CTRLMMR_GP_SW3 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 023Ch	4300 223Ch

Figure 5-35 CTRLMMR_GP_SW3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												VAL
R-0h																												R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-86 CTRLMMR_GP_SW3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3-0	VAL	R	X	general purpose value

1.1.5.20 CTRLMMR_CBA_ERR_STAT Register (Proxy0 Offset = 270h; Proxy1 Offset = 2270h) [reset = X]

CTRLMMR_CBA_ERR_STAT is shown in Figure 5-36 and described in Table 5-88.

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Indicates addressing errors on the bus segments.

Table 5-87 CTRLMMR_CBA_ERR_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 0270h	4300 2270h

Figure 5-36 CTRLMMR_CBA_ERR_STAT Register

31	30	29	28	27	26	25	24
DBG_CBA_ERR	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED							MCU_CBA_ERR
R-0h							R-X

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						MAIN_INFRA_CBA_ERR	MAIN_CBA_ERR
R-0h						R-X	R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-88 CTRLMMR_CBA_ERR_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DBG_CBA_ERR	R	X
30-17	RESERVED	R	0h	Reserved
16	MCU_CBA_ERR	R	X
15-2	RESERVED	R	0h	Reserved
1	MAIN_INFRA_CBA_ERR	R	X
0	MAIN_CBA_ERR	R	X

1.1.5.21 CTRLMMR_LOCK0_KICK0 Register (Proxy0 Offset = 1008h; Proxy1 Offset = 3008h) [reset = 0h]

CTRLMMR_LOCK0_KICK0 is shown in Figure 5-37 and described in Table 5-90.

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Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written.

Table 5-89 CTRLMMR_LOCK0_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1008h	4300 3008h

Figure 5-37 CTRLMMR_LOCK0_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-90 CTRLMMR_LOCK0_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.22 CTRLMMR_LOCK0_KICK1 Register (Proxy0 Offset = 100Ch; Proxy1 Offset = 300Ch) [reset = 0h]

CTRLMMR_LOCK0_KICK1 is shown in Figure 5-38 and described in Table 5-92.

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Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written.

Table 5-91 CTRLMMR_LOCK0_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 100Ch	4300 300Ch

Figure 5-38 CTRLMMR_LOCK0_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-92 CTRLMMR_LOCK0_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

1.1.5.23 CTRLMMR_INTR_RAW_STAT Register (Proxy0 Offset = 1010h; Proxy1 Offset = 3010h) [reset = 0h]

CTRLMMR_INTR_RAW_STAT is shown in Figure 5-39 and described in Table 5-94.

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Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test).

Table 5-93 CTRLMMR_INTR_RAW_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1010h	4300 3010h

Figure 5-39 CTRLMMR_INTR_RAW_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				PROXY_ERR	LOCK_ERR	ADDR_ERR	PROT_ERR
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-94 CTRLMMR_INTR_RAW_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	PROXY_ERR	W1TS	0h	Proxy violation occurred (attempt to write a Proxy1 claimed register through its Proxy0 address) Write 1 to set the status bit (for test) Writing 0 has no effect.
2	LOCK_ERR	W1TS	0h	Lock violation occurred (attempt to write a write-locked register with partition locked) Write 1 to set the status bit (for test) Writing 0 has no effect.
1	ADDR_ERR	W1TS	0h	Address violation occurred (attempt to read or write an invalid register address) Write 1 to set the status bit (for test) Writing 0 has no effect.
0	PROT_ERR	W1TS	0h	Reserved (Protection) Error Condition. Not applicable or checked on this device, but still can be stimulated by a software write to this bit. Write 1 to set the status bit (for test) Writing 0 has no effect.

1.1.5.24 CTRLMMR_INTR_STAT_CLR Register (Proxy0 Offset = 1014h; Proxy1 Offset = 3014h) [reset = 0h]

CTRLMMR_INTR_STAT_CLR is shown in Figure 5-40 and described in Table 5-96.

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Shows the enabled interrupt status and allows the interrupt to be cleared.

Table 5-95 CTRLMMR_INTR_STAT_CLR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1014h	4300 3014h

Figure 5-40 CTRLMMR_INTR_STAT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				EN_PROXY_ERR	EN_LOCK_ERR	EN_ADDR_ERR	EN_PROT_ERR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-96 CTRLMMR_INTR_STAT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	EN_PROXY_ERR	W1TC	0h	Enabled proxy interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
2	EN_LOCK_ERR	W1TC	0h	Enabled lock interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
1	EN_ADDR_ERR	W1TC	0h	Enabled address interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
0	EN_PROT_ERR	W1TC	0h	Enabled Reserved (protection) interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.

1.1.5.25 CTRLMMR_INTR_EN_SET Register (Proxy0 Offset = 1018h; Proxy1 Offset = 3018h) [reset = 0h]

CTRLMMR_INTR_EN_SET is shown in Figure 5-41 and described in Table 5-98.

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Allows interrupt enables to be set.

Table 5-97 CTRLMMR_INTR_EN_SET Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1018h	4300 3018h

Figure 5-41 CTRLMMR_INTR_EN_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				PROXY_ERR_EN_SET	LOCK_ERR_EN_SET	ADDR_ERR_EN_SET	PROT_ERR_EN_SET
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-98 CTRLMMR_INTR_EN_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	PROXY_ERR_EN_SET	W1TS	0h	Proxy interrupt enable Write 1 to enable proxy interrupt events Writing 0 has no effect.
2	LOCK_ERR_EN_SET	W1TS	0h	Lock interrupt enable Write 1 to enable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_SET	W1TS	0h	Address interrupt enable Write 1 to enable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_SET	W1TS	0h	Reserved (Protection) interrupt enable Write 1 to enable protection interrupt events Writing 0 has no effect.

1.1.5.26 CTRLMMR_INTR_EN_CLR Register (Proxy0 Offset = 101Ch; Proxy1 Offset = 301Ch) [reset = 0h]

CTRLMMR_INTR_EN_CLR is shown in Figure 5-42 and described in Table 5-100.

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Allows interrupt enables to be cleared.

Table 5-99 CTRLMMR_INTR_EN_CLR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 101Ch	4300 301Ch

Figure 5-42 CTRLMMR_INTR_EN_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				PROXY_ERR_EN_CLR	LOCK_ERR_EN_CLR	ADDR_ERR_EN_CLR	PROT_ERR_EN_CLR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-100 CTRLMMR_INTR_EN_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	PROXY_ERR_EN_CLR	W1TC	0h	Proxy interrupt disable Write 1 to disable proxy interrupt events Writing 0 has no effect.
2	LOCK_ERR_EN_CLR	W1TC	0h	Lock interrupt disable Write 1 to disable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_CLR	W1TC	0h	Address interrupt disable Write 1 to disable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_CLR	W1TC	0h	Reserved (Protection) interrupt disable Write 1 to disable protection interrupt events Writing 0 has no effect.

1.1.5.27 CTRLMMR_EOI Register (Proxy0 Offset = 1020h; Proxy1 Offset = 3020h) [reset = 0h]

CTRLMMR_EOI is shown in Figure 5-43 and described in Table 5-102.

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CTRLMMR_EOI Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt.

Table 5-101 CTRLMMR_EOI Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1020h	4300 3020h

Figure 5-43 CTRLMMR_EOI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								VECTOR
R-0h																								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-102 CTRLMMR_EOI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	VECTOR	R/W	0h	CTRLMMR_EOI vector value

1.1.5.28 CTRLMMR_FAULT_ADDR Register (Proxy0 Offset = 1024h; Proxy1 Offset = 3024h) [reset = 0h]

CTRLMMR_FAULT_ADDR is shown in Figure 5-44 and described in Table 5-104.

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Indicates the address of the first transfer that caused a fault to occur.

Table 5-103 CTRLMMR_FAULT_ADDR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1024h	4300 3024h

Figure 5-44 CTRLMMR_FAULT_ADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-104 CTRLMMR_FAULT_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDRESS	R	0h	Address of the faulted access

1.1.5.29 CTRLMMR_FAULT_TYPE Register (Proxy0 Offset = 1028h; Proxy1 Offset = 3028h) [reset = 0h]

CTRLMMR_FAULT_TYPE is shown in Figure 5-45 and described in Table 5-106.

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Indicates the access type of the first transfer that caused a fault to occur.

Table 5-105 CTRLMMR_FAULT_TYPE Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1028h	4300 3028h

Figure 5-45 CTRLMMR_FAULT_TYPE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										TYPE
R-0h																										R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-106 CTRLMMR_FAULT_TYPE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-6

RESERVED

R

0h

Reserved

5-0

TYPE

R

0h

Type of access which faulted

0h - No fault

1h - User execute access

2h - User write access

4h - User read access

8h - Supervisor execute access

10h - Supervisor write access

20h - Supervisor read access

1.1.5.30 CTRLMMR_FAULT_ATTR Register (Proxy0 Offset = 102Ch; Proxy1 Offset = 302Ch) [reset = 0h]

CTRLMMR_FAULT_ATTR is shown in Figure 5-46 and described in Table 5-108.

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Indicates the attributes of the first transfer that caused a fault to occur.

Table 5-107 CTRLMMR_FAULT_ATTR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 102Ch	4300 302Ch

Figure 5-46 CTRLMMR_FAULT_ATTR Register

31	30	29	28	27	26	25	24
XID
R-0h

23	22	21	20	19	18	17	16
XID				ROUTEID
R-0h				R-0h

15	14	13	12	11	10	9	8
ROUTEID
R-0h

7	6	5	4	3	2	1	0
PRIVID
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-108 CTRLMMR_FAULT_ATTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	XID	R	0h	Transaction ID
19-8	ROUTEID	R	0h	Route ID
7-0	PRIVID	R	0h	Privilege ID

1.1.5.31 CTRLMMR_FAULT_CLR Register (Proxy0 Offset = 1030h; Proxy1 Offset = 3030h) [reset = 0h]

CTRLMMR_FAULT_CLR is shown in Figure 5-47 and described in Table 5-110.

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Allows software to clear the current fault Clearing the current fault allows the CTRLMMR_FAULT_ADDR, CTRLMMR_FAULT_TYPE, and CTRLMMR_FAULT_ATTR registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits.

Table 5-109 CTRLMMR_FAULT_CLR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1030h	4300 3030h

Figure 5-47 CTRLMMR_FAULT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLEAR
R-0h							W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-110 CTRLMMR_FAULT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLEAR	W1TC	0h	Fault clear Write 1 to clear the current fault Writing 0 has no effect

1.1.5.32 CTRLMMR_P0_CLAIM0 Register (Proxy0 Offset = 1100h; Proxy1 Offset = 3100h) [reset = 0h]

CTRLMMR_P0_CLAIM0 is shown in Figure 5-48 and described in Table 5-112.

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Claim bits for Partition 0 Registers.

Table 5-111 CTRLMMR_P0_CLAIM0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1100h	4300 3100h

Figure 5-48 CTRLMMR_P0_CLAIM0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-112 CTRLMMR_P0_CLAIM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x0 + (0 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x2000 + (0 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.33 CTRLMMR_P0_CLAIM4 Register (Proxy0 Offset = 1110h; Proxy1 Offset = 3110h) [reset = 0h]

CTRLMMR_P0_CLAIM4 is shown in Figure 5-49 and described in Table 5-114.

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Claim bits for Partition 0 Registers.

Table 5-113 CTRLMMR_P0_CLAIM4 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 1110h	4300 3110h

Figure 5-49 CTRLMMR_P0_CLAIM4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-114 CTRLMMR_P0_CLAIM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x0 + (4 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x2000 + (4 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.34 CTRLMMR_USB0_PHY_CTRL Register (Proxy0 Offset = 4008h; Proxy1 Offset = 6008h) [reset = 80000004h]

CTRLMMR_USB0_PHY_CTRL is shown in Figure 5-50 and described in Table 5-116.

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Configures the USB0 Phy operation.

Table 5-115 CTRLMMR_USB0_PHY_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4008h	4300 6008h

Figure 5-50 CTRLMMR_USB0_PHY_CTRL Register

31	30	29	28	27	26	25	24
RESERVED	RESERVED
R-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED						LOOPBACK_MODE
R-0h						R/W-0h

15	14	13	12	11	10	9	8
PLL_STANDALONE	RESERVED			PLL_CLKOUT_ON	RESERVED	PLL_CLKOUT_SEL
R/W-0h	R-0h			R/W-0h	R-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED				PLL_REF_SEL
R-0h				R/W-4h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-116 CTRLMMR_USB0_PHY_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17-16	LOOPBACK_MODE	R/W	0h	Enables USB0 PHY loopback operation 0h - Loopback is off 1h - LS loopback mode 2h - FS loopback mode 3h - HS loopback mode
15	PLL_STANDALONE	R/W	0h	Enables USB0 PHY as a standalone PLL 0h - PHY PLL not used as standalone 1h - UTMI interface is in suspend mode and PLL clock is output
14-12	RESERVED	R	0h	Reserved
11	PLL_CLKOUT_ON	R/W	0h	Controls USB0 PLL clock output 0h - Output clock is disabled 1h - Output clock in enabled
10	RESERVED	R	0h	Reserved
9-8	PLL_CLKOUT_SEL	R/W	0h	Selects the frequency of the USB0 PLL output clock 0h - 480 MHz 1h - 240 MHz 2h - 120 MHz 3h - 60 MHz
7-4	RESERVED	R	0h	Reserved
3-0	PLL_REF_SEL	R/W	4h	Indicates the frequency of the REF_CLOCK input used by the USB PLL. This value should match the frequency value of the HFOSC0 or oscillator as selected by the CTRLMMR_USB0_CLKSEL register 0h - 9.6 MHz 1h - 10 MHz 2h - 12 MHz 3h - 18.2 MHZ 4h - 20 MHz 5h - 24 MHz 6h - 25 MHz 7h - 26 MHz 8h - 38.4 MHz 9h - 40 MHz Ah - 48 MHz Bh - 50 MHz Ch - 52 MHz

1.1.5.35 CTRLMMR_ENET1_CTRL Register (Proxy0 Offset = 4044h; Proxy1 Offset = 6044h) [reset = 2h]

CTRLMMR_ENET1_CTRL is shown in Figure 5-51 and described in Table 5-118.

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Controls Ethernet Port1 operation.

Table 5-117 CTRLMMR_ENET1_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4044h	4300 6044h

Figure 5-51 CTRLMMR_ENET1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	RESERVED	PORT_MODE_SEL
R-0h			R/W-0h	R-0h	R/W-2h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-118 CTRLMMR_ENET1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	PORT_MODE_SEL	R/W	2h	Selects Ethernet switch Port1 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII (not supported) 4h - QSGMII (not supported) 5h - XFI (not supported) 6h - QSGMII_SUB (not supported) 7h - Reserved

1.1.5.36 CTRLMMR_ENET2_CTRL Register (Proxy0 Offset = 4048h; Proxy1 Offset = 6048h) [reset = 2h]

CTRLMMR_ENET2_CTRL is shown in Figure 5-52 and described in Table 5-120.

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Controls Ethernet Port2 operation.

Table 5-119 CTRLMMR_ENET2_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4048h	4300 6048h

Figure 5-52 CTRLMMR_ENET2_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED	RESERVED	PORT_MODE_SEL
R-0h			R/W-0h	R-0h	R/W-2h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-120 CTRLMMR_ENET2_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	PORT_MODE_SEL	R/W	2h	Selects Ethernet switch Port2 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII (not supported) 4h - QSGMII (not supported) 5h - XFI (not supported) 6h - QSGMII_SUB (not supported) 7h - Reserved

1.1.5.37 CTRLMMR_PCIE0_CTRL Register (Proxy0 Offset = 4070h; Proxy1 Offset = 6070h) [reset = 1h]

CTRLMMR_PCIE0_CTRL is shown in Figure 5-53 and described in Table 5-122.

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Controls PCIe0 operation.

Table 5-121 CTRLMMR_PCIE0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4070h	4300 6070h

Figure 5-53 CTRLMMR_PCIE0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
MODE_SEL	RESERVED					GENERATION_SEL
R/W-0h	R-0h					R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-122 CTRLMMR_PCIE0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	MODE_SEL	R/W	0h	Selects the operating mode 0h - Endpoint 1h - Root Complex
6-2	RESERVED	R	0h	Reserved
1-0	GENERATION_SEL	R/W	1h	Configures the PCIe generation support in the PCIe capabilities linked-list 1h - Gen2 - Controller advertises Gen1 & Gen2 capability and link operates at either speed 2h - Reserved 3h - Reserved

1.1.5.38 CTRLMMR_SERDES0_LN0_CTRL Register (Proxy0 Offset = 4080h; Proxy1 Offset = 6080h) [reset = 0h]

CTRLMMR_SERDES0_LN0_CTRL is shown in Figure 5-54 and described in Table 5-124.

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Controls 10G SERDES0 lane0 selection.

Table 5-123 CTRLMMR_SERDES0_LN0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4080h	4300 6080h

Figure 5-54 CTRLMMR_SERDES0_LN0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						LANE_FUNC_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-124 CTRLMMR_SERDES0_LN0_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

LANE_FUNC_SEL

R/W

0h

Selects the SERDES0 lane0 function

0h - IP2 - PCIe0 Lane0

1h - IP2 - USBSS0

1.1.5.39 CTRLMMR_ADC0_TRIM Register (Proxy0 Offset = 40C0h; Proxy1 Offset = 60C0h) [reset = X]

CTRLMMR_ADC0_TRIM is shown in Figure 5-55 and described in Table 5-126.

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Trim for Non-Linearities.

Table 5-125 CTRLMMR_ADC0_TRIM Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 40C0h	4300 60C0h

Figure 5-55 CTRLMMR_ADC0_TRIM Register

31	30	29	28	27	26	25	24
RESERVED					TRIM5
R-0h					R/W-X

23	22	21	20	19	18	17	16
TRIM4			TRIM3			TRIM2
R/W-X			R/W-X			R/W-X

15	14	13	12	11	10	9	8
TRIM2		TRIM1				ENABLE_CALB
R/W-X		R/W-X				R/W-X

7	6	5	4	3	2	1	0
ENABLE_CALB			ENABLE_CAL
R/W-X			R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-126 CTRLMMR_ADC0_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	TRIM5	R/W	X	Trims Nonlinearities from ADC
23-21	TRIM4	R/W	X	Trims Nonlinearities from ADC
20-18	TRIM3	R/W	X	Trims Nonlinearities from ADC
17-14	TRIM2	R/W	X	Trims Nonlinearities from ADC
13-10	TRIM1	R/W	X	Trims Nonlinearities from ADC
9-5	ENABLE_CALB	R/W	X	Trims Nonlinearities from ADC
4-0	ENABLE_CAL	R/W	X	Trims Nonlinearities from ADC

1.1.5.40 CTRLMMR_SERDES0_CTRL Register (Proxy0 Offset = 40E0h; Proxy1 Offset = 60E0h) [reset = 0h]

CTRLMMR_SERDES0_CTRL is shown in Figure 5-56 and described in Table 5-128.

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Controls SERDES0 operation.

Table 5-127 CTRLMMR_SERDES0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 40E0h	4300 60E0h

Figure 5-56 CTRLMMR_SERDES0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED			REF_SEL	RESERVED			RET_EN
R-0h			R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-128 CTRLMMR_SERDES0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	0h	Reserved
12	REF_SEL	R/W	0h	REFCLK output select
11-9	RESERVED	R	0h	Reserved
8	RET_EN	R/W	0h	Retention enable
7-0	RESERVED	R	0h	Reserved

1.1.5.41 CTRLMMR_ICSSG0_CTRL0 Register (Proxy0 Offset = 4100h; Proxy1 Offset = 6100h) [reset = 0h]

CTRLMMR_ICSSG0_CTRL0 is shown in Figure 5-57 and described in Table 5-130.

Return to Summary Table.

Controls ICSS_G0 operation.

Table 5-129 CTRLMMR_ICSSG0_CTRL0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4100h	4300 6100h

Figure 5-57 CTRLMMR_ICSSG0_CTRL0 Register

31	30	29	28	27	26	25	24
RESERVED							RGMII0_ID_MODE
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				GPM_BIDI
R-0h				R/W-0h

15	14	13	12	11	10	9	8
GPM_BIDI
R/W-0h

7	6	5	4	3	2	1	0
GPM_BIDI
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-130 CTRLMMR_ICSSG0_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RGMII0_ID_MODE	R/W	0h	Controls the ICSS_G0 RGMII0 port internal transmit delay 0h - Internal transmit delay is enabled 1h - Internal transmit delay is not enabled. TX clock rising edge is aligned with TX data
23-20	RESERVED	R	0h	Reserved
19-0	GPM_BIDI	R/W	0h	Controls operation of the ICSS_G0 PRU0_GPO pins. Each bit n controls the corresponding PRG0_PRU0GPOn I/O 0h - In GPO mode, pin n functions as GPM output only 1h - In GPO mode, pin n functions as GPM output or GPN input. Direction is controlled by the ICSS-G0 _pr1_edio0_data_out_en[n] output.

1.1.5.42 CTRLMMR_ICSSG0_CTRL1 Register (Proxy0 Offset = 4104h; Proxy1 Offset = 6104h) [reset = 0h]

CTRLMMR_ICSSG0_CTRL1 is shown in Figure 5-58 and described in Table 5-132.

Return to Summary Table.

Controls ICSS_G0 operation.

Table 5-131 CTRLMMR_ICSSG0_CTRL1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4104h	4300 6104h

Figure 5-58 CTRLMMR_ICSSG0_CTRL1 Register

31	30	29	28	27	26	25	24
RESERVED							RGMII1_ID_MODE
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				GPM_BIDI
R-0h				R/W-0h

15	14	13	12	11	10	9	8
GPM_BIDI
R/W-0h

7	6	5	4	3	2	1	0
GPM_BIDI
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-132 CTRLMMR_ICSSG0_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RGMII1_ID_MODE	R/W	0h	Controls the ICSS_G0 RGMII1 port internal transmit delay 0h - Internal transmit delay is enabled 1h - Internal transmit delay is not enabled. TX clock rising edge is aligned with TX data
23-20	RESERVED	R	0h	Reserved
19-0	GPM_BIDI	R/W	0h	Controls operation of the ICSS_G0 PRU1_GPO pins. Each bit n controls the corresponding PRG0_PRU1GPOn I/O 0h - In GPO mode, pin n functions as GPM output only 1h - In GPO mode, pin n functions as GPM output or GPN input. Direction is controlled by the ICSS-G0 _pr1_edio1_data_out_en[n] output.

1.1.5.43 CTRLMMR_ICSSG1_CTRL0 Register (Proxy0 Offset = 4110h; Proxy1 Offset = 6110h) [reset = 0h]

CTRLMMR_ICSSG1_CTRL0 is shown in Figure 5-59 and described in Table 5-134.

Return to Summary Table.

Controls ICSS_G1 operation.

Table 5-133 CTRLMMR_ICSSG1_CTRL0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4110h	4300 6110h

Figure 5-59 CTRLMMR_ICSSG1_CTRL0 Register

31	30	29	28	27	26	25	24
RESERVED							RGMII0_ID_MODE
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				GPM_BIDI
R-0h				R/W-0h

15	14	13	12	11	10	9	8
GPM_BIDI
R/W-0h

7	6	5	4	3	2	1	0
GPM_BIDI
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-134 CTRLMMR_ICSSG1_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RGMII0_ID_MODE	R/W	0h	Controls the ICSS_G1 RGMII0 port internal transmit delay 0h - Internal transmit delay is enabled 1h - Internal transmit delay is not enabled. TX clock rising edge is aligned with TX data
23-20	RESERVED	R	0h	Reserved
19-0	GPM_BIDI	R/W	0h	Controls operation of the ICSS_G1 PRU0_GPO pins. Each bit n controls the corresponding PRG1_PRU0GPOn I/O 0h - In GPO mode, pin n functions as GPM output only 1h - In GPO mode, pin n functions as GPM output or GPN input. Direction is controlled by the ICSS-G1 _pr1_edio0_data_out_en[n] output.

1.1.5.44 CTRLMMR_ICSSG1_CTRL1 Register (Proxy0 Offset = 4114h; Proxy1 Offset = 6114h) [reset = 0h]

CTRLMMR_ICSSG1_CTRL1 is shown in Figure 5-60 and described in Table 5-136.

Return to Summary Table.

Controls ICSS_G1 operation.

Table 5-135 CTRLMMR_ICSSG1_CTRL1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4114h	4300 6114h

Figure 5-60 CTRLMMR_ICSSG1_CTRL1 Register

31	30	29	28	27	26	25	24
RESERVED							RGMII1_ID_MODE
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				GPM_BIDI
R-0h				R/W-0h

15	14	13	12	11	10	9	8
GPM_BIDI
R/W-0h

7	6	5	4	3	2	1	0
GPM_BIDI
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-136 CTRLMMR_ICSSG1_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RGMII1_ID_MODE	R/W	0h	Controls the ICSS_G1 RGMII1 port internal transmit delay 0h - Internal transmit delay is enabled 1h - Internal transmit delay is not enabled. TX clock rising edge is aligned with TX data
23-20	RESERVED	R	0h	Reserved
19-0	GPM_BIDI	R/W	0h	Controls operation of the ICSS_G1 PRU1_GPO pins. Each bit n controls the corresponding PRG1_PRU1GPOn I/O 0h - In GPO mode, pin n functions as GPM output only 1h - In GPO mode, pin n functions as GPM output or GPN input. Direction is controlled by the ICSS-G1 _pr1_edio1_data_out_en[n] output.

1.1.5.45 CTRLMMR_EPWM_TB_CLKEN Register (Proxy0 Offset = 4130h; Proxy1 Offset = 6130h) [reset = 0h]

CTRLMMR_EPWM_TB_CLKEN is shown in Figure 5-61 and described in Table 5-138.

Return to Summary Table.

Controls Timebase Counter of EPWM Modules.

Table 5-137 CTRLMMR_EPWM_TB_CLKEN Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4130h	4300 6130h

Figure 5-61 CTRLMMR_EPWM_TB_CLKEN Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							EPWM8_TB_CLKEN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
EPWM7_TB_CLKEN	EPWM6_TB_CLKEN	EPWM5_TB_CLKEN	EPWM4_TB_CLKEN	EPWM3_TB_CLKEN	EPWM2_TB_CLKEN	EPWM1_TB_CLKEN	EPWM0_TB_CLKEN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-138 CTRLMMR_EPWM_TB_CLKEN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	EPWM8_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM8 When Set
7	EPWM7_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM7 When Set
6	EPWM6_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM6 When Set
5	EPWM5_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM5 When Set
4	EPWM4_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM4 When Set
3	EPWM3_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM3 When Set
2	EPWM2_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM2 When Set
1	EPWM1_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM1 When Set
0	EPWM0_TB_CLKEN	R/W	0h	Enables Timebase Clock of EPWM0 When Set

1.1.5.46 CTRLMMR_EPWM_TB_CLKEN_SET Register (Proxy0 Offset = 4134h; Proxy1 Offset = 6134h) [reset = 0h]

CTRLMMR_EPWM_TB_CLKEN_SET is shown in Figure 5-62 and described in Table 5-140.

Return to Summary Table.

Controls Timebase Counter of EPWM Modules.

Table 5-139 CTRLMMR_EPWM_TB_CLKEN_SET Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4134h	4300 6134h

Figure 5-62 CTRLMMR_EPWM_TB_CLKEN_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							EPWM8_TB_CLKEN
R-0h							W1TS-0h

7	6	5	4	3	2	1	0
EPWM7_TB_CLKEN	EPWM6_TB_CLKEN	EPWM5_TB_CLKEN	EPWM4_TB_CLKEN	EPWM3_TB_CLKEN	EPWM2_TB_CLKEN	EPWM1_TB_CLKEN	EPWM0_TB_CLKEN
W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-140 CTRLMMR_EPWM_TB_CLKEN_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	EPWM8_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM8
7	EPWM7_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM7
6	EPWM6_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM6
5	EPWM5_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM5
4	EPWM4_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM4
3	EPWM3_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM3
2	EPWM2_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM2
1	EPWM1_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM1
0	EPWM0_TB_CLKEN	W1TS	0h	Writing One Enables Timebase Clock of EPWM0

1.1.5.47 CTRLMMR_EPWM_TB_CLKEN_CLR Register (Proxy0 Offset = 4138h; Proxy1 Offset = 6138h) [reset = 0h]

CTRLMMR_EPWM_TB_CLKEN_CLR is shown in Figure 5-63 and described in Table 5-142.

Return to Summary Table.

Controls Timebase Counter of EPWM Modules.

Table 5-141 CTRLMMR_EPWM_TB_CLKEN_CLR Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4138h	4300 6138h

Figure 5-63 CTRLMMR_EPWM_TB_CLKEN_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							EPWM8_TB_CLKEN
R-0h							W1TC-0h

7	6	5	4	3	2	1	0
EPWM7_TB_CLKEN	EPWM6_TB_CLKEN	EPWM5_TB_CLKEN	EPWM4_TB_CLKEN	EPWM3_TB_CLKEN	EPWM2_TB_CLKEN	EPWM1_TB_CLKEN	EPWM0_TB_CLKEN
W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-142 CTRLMMR_EPWM_TB_CLKEN_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	EPWM8_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM8
7	EPWM7_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM7
6	EPWM6_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM6
5	EPWM5_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM5
4	EPWM4_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM4
3	EPWM3_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM3
2	EPWM2_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM2
1	EPWM1_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM1
0	EPWM0_TB_CLKEN	W1TC	0h	Writing One Disables Timebase Clock of EPWM0

1.1.5.48 CTRLMMR_EPWM0_CTRL Register (Proxy0 Offset = 4140h; Proxy1 Offset = 6140h) [reset = 0h]

CTRLMMR_EPWM0_CTRL is shown in Figure 5-64 and described in Table 5-144.

Return to Summary Table.

Controls EPWM0 Operation.

Table 5-143 CTRLMMR_EPWM0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4140h	4300 6140h

Figure 5-64 CTRLMMR_EPWM0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED					SYNCIN_SEL
R-0h					R/W-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-144 CTRLMMR_EPWM0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	SYNCIN_SEL	R/W	0h	Selects the source of the EPWM0 synchronization input 0h - EPWM0_SYNCIN Pin 1h - None 2h - Time Sync Router 38 3h - Compare Event Router 40 4h - ICSSG0 Host Interrupt 6 5h - ICSSG1 Host Interrupt 6 6h - None 7h - None
7-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.49 CTRLMMR_EPWM1_CTRL Register (Proxy0 Offset = 4144h; Proxy1 Offset = 6144h) [reset = 0h]

CTRLMMR_EPWM1_CTRL is shown in Figure 5-65 and described in Table 5-146.

Return to Summary Table.

Controls EPWM1 Operation.

Table 5-145 CTRLMMR_EPWM1_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4144h	4300 6144h

Figure 5-65 CTRLMMR_EPWM1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-146 CTRLMMR_EPWM1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.50 CTRLMMR_EPWM2_CTRL Register (Proxy0 Offset = 4148h; Proxy1 Offset = 6148h) [reset = 0h]

CTRLMMR_EPWM2_CTRL is shown in Figure 5-66 and described in Table 5-148.

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Controls EPWM2 Operation.

Table 5-147 CTRLMMR_EPWM2_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4148h	4300 6148h

Figure 5-66 CTRLMMR_EPWM2_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-148 CTRLMMR_EPWM2_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.51 CTRLMMR_EPWM3_CTRL Register (Proxy0 Offset = 414Ch; Proxy1 Offset = 614Ch) [reset = 0h]

CTRLMMR_EPWM3_CTRL is shown in Figure 5-67 and described in Table 5-150.

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Controls EPWM3 Operation.

Table 5-149 CTRLMMR_EPWM3_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 414Ch	4300 614Ch

Figure 5-67 CTRLMMR_EPWM3_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED					SYNCIN_SEL
R-0h					R/W-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-150 CTRLMMR_EPWM3_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	SYNCIN_SEL	R/W	0h	Selects the source of the EPWM3 synchronization input 0h - EPWM3_SYNCIN Pin 1h - EPWM2 syncout signal, daisy chained 2h - Time Sync Router 39 3h - Compare Event Router 41 4h - ICSSG0 Host Interrupt 7 5h - ICSSG1 Host Interrupt 7 6h - None 7h - None
7-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.52 CTRLMMR_EPWM4_CTRL Register (Proxy0 Offset = 4150h; Proxy1 Offset = 6150h) [reset = 0h]

CTRLMMR_EPWM4_CTRL is shown in Figure 5-68 and described in Table 5-152.

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Controls EPWM4 Operation.

Table 5-151 CTRLMMR_EPWM4_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4150h	4300 6150h

Figure 5-68 CTRLMMR_EPWM4_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-152 CTRLMMR_EPWM4_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.53 CTRLMMR_EPWM5_CTRL Register (Proxy0 Offset = 4154h; Proxy1 Offset = 6154h) [reset = 0h]

CTRLMMR_EPWM5_CTRL is shown in Figure 5-69 and described in Table 5-154.

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Controls EPWM5 Operation.

Table 5-153 CTRLMMR_EPWM5_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4154h	4300 6154h

Figure 5-69 CTRLMMR_EPWM5_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-154 CTRLMMR_EPWM5_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.54 CTRLMMR_EPWM6_CTRL Register (Proxy0 Offset = 4158h; Proxy1 Offset = 6158h) [reset = 0h]

CTRLMMR_EPWM6_CTRL is shown in Figure 5-70 and described in Table 5-156.

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Controls EPWM6 Operation.

Table 5-155 CTRLMMR_EPWM6_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4158h	4300 6158h

Figure 5-70 CTRLMMR_EPWM6_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED					SYNCIN_SEL
R-0h					R/W-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-156 CTRLMMR_EPWM6_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R	0h	Reserved
10-8	SYNCIN_SEL	R/W	0h	Selects the source of the EPWM6 synchronization input 0h - EPWM6_SYNCIN Pin 1h - EPWM5 syncout signal, daisy chained 2h - Time Sync Router 40 3h - Compare Event Router 42 4h - ICSSG0 Host Interrupt 7 5h - ICSSG1 Host Interrupt 7 6h - None 7h - None
7-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.55 CTRLMMR_EPWM7_CTRL Register (Proxy0 Offset = 415Ch; Proxy1 Offset = 615Ch) [reset = 0h]

CTRLMMR_EPWM7_CTRL is shown in Figure 5-71 and described in Table 5-158.

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Controls EPWM7 Operation.

Table 5-157 CTRLMMR_EPWM7_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 415Ch	4300 615Ch

Figure 5-71 CTRLMMR_EPWM7_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-158 CTRLMMR_EPWM7_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.56 CTRLMMR_EPWM8_CTRL Register (Proxy0 Offset = 4160h; Proxy1 Offset = 6160h) [reset = 0h]

CTRLMMR_EPWM8_CTRL is shown in Figure 5-72 and described in Table 5-160.

Return to Summary Table.

Controls EPWM8 Operation.

Table 5-159 CTRLMMR_EPWM8_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4160h	4300 6160h

Figure 5-72 CTRLMMR_EPWM8_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			EALLOW	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-160 CTRLMMR_EPWM8_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	EALLOW	R/W	0h	Enable write access to EPWM tripzone registers 0h - Disabled 1h - Enabled
3-0	RESERVED	R	0h	Reserved

1.1.5.57 CTRLMMR_SOCA_SEL Register (Proxy0 Offset = 4170h; Proxy1 Offset = 6170h) [reset = 0h]

CTRLMMR_SOCA_SEL is shown in Figure 5-73 and described in Table 5-162.

Return to Summary Table.

Selects Start of Conversion A output signal source.. Each EPWM provides a SOCA event that can be used to trigger ADCs (External or Internal). All EPWM SOCA events are ORed together allowing any of the EPWM modules to generate the event (if enabled within the EPWM). This event is then muxed with an ICSSx host interrupt allowing either an ICSSx or EPWM to source the SOCA event pin.

Table 5-161 CTRLMMR_SOCA_SEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4170h	4300 6170h

Figure 5-73 CTRLMMR_SOCA_SEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						SOCA_SEL_SOCA_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-162 CTRLMMR_SOCA_SEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

SOCA_SEL_SOCA_SEL

R/W

0h

Selects the SOC A output source

0h - OR of all EPWM SOCA outputs

1h - ICSSG0 Host Interrupt 1

2h - ICSSG1 Host Interrupt 1

3h - None

1.1.5.58 CTRLMMR_SOCB_SEL Register (Proxy0 Offset = 4174h; Proxy1 Offset = 6174h) [reset = 0h]

CTRLMMR_SOCB_SEL is shown in Figure 5-74 and described in Table 5-164.

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Selects Start of Conversion B output signal source.. Each EPWM provides a SOCB event that can be used to trigger ADCs (External or Internal). All EPWM SOCb events are ORed together allowing any of the EPWM modules to generate the event (if enabled within the EPWM). This event is then muxed with an ICSSx host interrupt allowing either an ICSSx or EPWM to source the SOCB event pin.

Table 5-163 CTRLMMR_SOCB_SEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4174h	4300 6174h

Figure 5-74 CTRLMMR_SOCB_SEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						SOCB_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-164 CTRLMMR_SOCB_SEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

SOCB_SEL

R/W

0h

Selects the SOC B output source

0h - OR of all EPWM SOCB ouputs

1h - ICSSG0 Host Interrupt 2

2h - ICSSG1 Host Interrupt 2

3h - None

1.1.5.59 CTRLMMR_EQEP0_CTRL Register (Proxy0 Offset = 4180h; Proxy1 Offset = 6180h) [reset = 0h]

CTRLMMR_EQEP0_CTRL is shown in Figure 5-75 and described in Table 5-166.

Return to Summary Table.

Selects Start of Conversion A input signal for EQEP0. This can be used to create a strobe (EQEP0_S) from one of the on chip sources selected by the EQEP0 SOCA mux.

Table 5-165 CTRLMMR_EQEP0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4180h	4300 6180h

Figure 5-75 CTRLMMR_EQEP0_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																											SOCA_SEL
R-0h																											R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-166 CTRLMMR_EQEP0_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-5

RESERVED

R

0h

Reserved

4-0

SOCA_SEL

R/W

0h

Selects the source of SOCA input for EQEP0

0h - ADC_EXT_TRIGGER0 Pin

1h - ADC_EXT_TRIGGER1 Pin

2h - EPWM SOCA_OUT

3h - EPWM SOCB_OUT

4h - MCU_TIMER0 PWM

5h - MCU_TIMER1 PWM

6h - MCU_TIMER2 PWM

7h - MCU_TIMER3 PWM

8h - TIMER0 PWM

9h - TIMER1 PWM

Ah - TIMER2 PWM

Bh - TIMER3 PWM

Ch - TIMER4 PWM

Dh - TIMER5 PWM

Eh - TIMER6 PWM

Fh - TIMER7 PWM

10h - TIMER8 PWM

11h - TIMER9 PWM

12h - TIMER10 PWM

13h - TIMER11 PWM

14h - ICSSG0 PR1 IEP0

15h - ICSSG0 PR1 IEP1

16h - ICSSG1 PR1 IEP0

17h - ICSSG1 PR1 IEP1

18h - ICSSG0 PR1 HOST INTR PEND4

19h - ICSSG0 PR1 HOST INTR PEND5

1Ah - ICSSG1 PR1 HOST INTR PEND4

1Bh - ICSSG1 PR1 HOST INTR PEND5

1.1.5.60 CTRLMMR_EQEP1_CTRL Register (Proxy0 Offset = 4184h; Proxy1 Offset = 6184h) [reset = 0h]

CTRLMMR_EQEP1_CTRL is shown in Figure 5-76 and described in Table 5-168.

Return to Summary Table.

Selects Start of Conversion A input signal for EQEP1. This can be used to create a strobe (EQEP1_S) from one of the on chip sources selected by the EQEP1 SOCA mux.

Table 5-167 CTRLMMR_EQEP1_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4184h	4300 6184h

Figure 5-76 CTRLMMR_EQEP1_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																											SOCA_SEL
R-0h																											R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-168 CTRLMMR_EQEP1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-5

RESERVED

R

0h

Reserved

4-0

SOCA_SEL

R/W

0h

Selects the source of SOCA input for EQEP1

0h - ADC_EXT_TRIGGER0 Pin

1h - ADC_EXT_TRIGGER1 Pin

2h - EPWM SOCA_OUT

3h - EPWM SOCB_OUT

4h - MCU_TIMER0 PWM

5h - MCU_TIMER1 PWM

6h - MCU_TIMER2 PWM

7h - MCU_TIMER3 PWM

8h - TIMER0 PWM

9h - TIMER1 PWM

Ah - TIMER2 PWM

Bh - TIMER3 PWM

Ch - TIMER4 PWM

Dh - TIMER5 PWM

Eh - TIMER6 PWM

Fh - TIMER7 PWM

10h - TIMER8 PWM

11h - TIMER9 PWM

12h - TIMER10 PWM

13h - TIMER11 PWM

14h - ICSSG0 PR1 IEP0

15h - ICSSG0 PR1 IEP1

16h - ICSSG1 PR1 IEP0

17h - ICSSG1 PR1 IEP1

18h - ICSSG0 PR1 HOST INTR PEND4

19h - ICSSG0 PR1 HOST INTR PEND5

1Ah - ICSSG1 PR1 HOST INTR PEND4

1Bh - ICSSG1 PR1 HOST INTR PEND5

1.1.5.61 CTRLMMR_EQEP2_CTRL Register (Proxy0 Offset = 4188h; Proxy1 Offset = 6188h) [reset = 0h]

CTRLMMR_EQEP2_CTRL is shown in Figure 5-77 and described in Table 5-170.

Return to Summary Table.

Selects Start of Conversion A input signal for EQEP2. This can be used to create a strobe (EQEP2_S) from one of the on chip sources selected by the EQEP2 SOCA mux.

Table 5-169 CTRLMMR_EQEP2_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4188h	4300 6188h

Figure 5-77 CTRLMMR_EQEP2_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																											SOCA_SEL
R-0h																											R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-170 CTRLMMR_EQEP2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-5

RESERVED

R

0h

Reserved

4-0

SOCA_SEL

R/W

0h

Selects the source of SOCA input for EQEP2

0h - ADC_EXT_TRIGGER0 Pin

1h - ADC_EXT_TRIGGER1 Pin

2h - EPWM SOCA_OUT

3h - EPWM SOCB_OUT

4h - MCU_TIMER0 PWM

5h - MCU_TIMER1 PWM

6h - MCU_TIMER2 PWM

7h - MCU_TIMER3 PWM

8h - TIMER0 PWM

9h - TIMER1 PWM

Ah - TIMER2 PWM

Bh - TIMER3 PWM

Ch - TIMER4 PWM

Dh - TIMER5 PWM

Eh - TIMER6 PWM

Fh - TIMER7 PWM

10h - TIMER8 PWM

11h - TIMER9 PWM

12h - TIMER10 PWM

13h - TIMER11 PWM

14h - ICSSG0 PR1 IEP0

15h - ICSSG0 PR1 IEP1

16h - ICSSG1 PR1 IEP0

17h - ICSSG1 PR1 IEP1

18h - ICSSG0 PR1 HOST INTR PEND4

19h - ICSSG0 PR1 HOST INTR PEND5

1Ah - ICSSG1 PR1 HOST INTR PEND4

1Bh - ICSSG1 PR1 HOST INTR PEND5

1.1.5.62 CTRLMMR_EQEP_STAT Register (Proxy0 Offset = 41A0h; Proxy1 Offset = 61A0h) [reset = X]

CTRLMMR_EQEP_STAT is shown in Figure 5-78 and described in Table 5-172.

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Displays status of EQEP modules.

Table 5-171 CTRLMMR_EQEP_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 41A0h	4300 61A0h

Figure 5-78 CTRLMMR_EQEP_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					PHASE_ERR2	PHASE_ERR1	PHASE_ERR0
R-0h					R-X	R-X	R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-172 CTRLMMR_EQEP_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	0h	Reserved
2	PHASE_ERR2	R	X	EQEP2 Phase error status 0h - No error 1h - Phase error occurred
1	PHASE_ERR1	R	X	EQEP1 Phase error status 0h - No error 1h - Phase error occurred
0	PHASE_ERR0	R	X	EQEP0 Phase error status 0h - No error 1h - Phase error occurred

1.1.5.63 CTRLMMR_SDIO1_CTRL Register (Proxy0 Offset = 41B4h; Proxy1 Offset = 61B4h) [reset = X]

CTRLMMR_SDIO1_CTRL is shown in Figure 5-79 and described in Table 5-174.

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Controls drive strength of MMC1 SDIO mode pins.

Table 5-173 CTRLMMR_SDIO1_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 41B4h	4300 61B4h

Figure 5-79 CTRLMMR_SDIO1_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																											DRV_STR
R-0h																											R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-174 CTRLMMR_SDIO1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4-0	DRV_STR	R/W	X	Selects the SDIO drive strength

1.1.5.64 CTRLMMR_TIMER1_CTRL Register (Proxy0 Offset = 4204h; Proxy1 Offset = 6204h) [reset = 0h]

CTRLMMR_TIMER1_CTRL is shown in Figure 5-80 and described in Table 5-176.

Return to Summary Table.

Controls TIMER1 operation.

Table 5-175 CTRLMMR_TIMER1_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4204h	4300 6204h

Figure 5-80 CTRLMMR_TIMER1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-176 CTRLMMR_TIMER1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER1 to TIMER0
7-0	RESERVED	R	0h	Reserved

1.1.5.65 CTRLMMR_TIMER3_CTRL Register (Proxy0 Offset = 420Ch; Proxy1 Offset = 620Ch) [reset = 0h]

CTRLMMR_TIMER3_CTRL is shown in Figure 5-81 and described in Table 5-178.

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Controls TIMER3 operation.

Table 5-177 CTRLMMR_TIMER3_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 420Ch	4300 620Ch

Figure 5-81 CTRLMMR_TIMER3_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-178 CTRLMMR_TIMER3_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER3 to TIMER2
7-0	RESERVED	R	0h	Reserved

1.1.5.66 CTRLMMR_TIMER5_CTRL Register (Proxy0 Offset = 4214h; Proxy1 Offset = 6214h) [reset = 0h]

CTRLMMR_TIMER5_CTRL is shown in Figure 5-82 and described in Table 5-180.

Return to Summary Table.

Controls TIMER5 operation.

Table 5-179 CTRLMMR_TIMER5_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4214h	4300 6214h

Figure 5-82 CTRLMMR_TIMER5_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-180 CTRLMMR_TIMER5_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER5 to TIMER4
7-0	RESERVED	R	0h	Reserved

1.1.5.67 CTRLMMR_TIMER7_CTRL Register (Proxy0 Offset = 421Ch; Proxy1 Offset = 621Ch) [reset = 0h]

CTRLMMR_TIMER7_CTRL is shown in Figure 5-83 and described in Table 5-182.

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Controls TIMER7 operation.

Table 5-181 CTRLMMR_TIMER7_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 421Ch	4300 621Ch

Figure 5-83 CTRLMMR_TIMER7_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-182 CTRLMMR_TIMER7_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER7 to TIMER6
7-0	RESERVED	R	0h	Reserved

1.1.5.68 CTRLMMR_TIMER9_CTRL Register (Proxy0 Offset = 4224h; Proxy1 Offset = 6224h) [reset = 0h]

CTRLMMR_TIMER9_CTRL is shown in Figure 5-84 and described in Table 5-184.

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Controls TIMER9 operation.

Table 5-183 CTRLMMR_TIMER9_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4224h	4300 6224h

Figure 5-84 CTRLMMR_TIMER9_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-184 CTRLMMR_TIMER9_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER9 to TIMER8
7-0	RESERVED	R	0h	Reserved

1.1.5.69 CTRLMMR_TIMER11_CTRL Register (Proxy0 Offset = 422Ch; Proxy1 Offset = 622Ch) [reset = 0h]

CTRLMMR_TIMER11_CTRL is shown in Figure 5-85 and described in Table 5-186.

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Controls TIMER11 operation.

Table 5-185 CTRLMMR_TIMER11_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 422Ch	4300 622Ch

Figure 5-85 CTRLMMR_TIMER11_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-186 CTRLMMR_TIMER11_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	Enables cascading of TIMER11 to TIMER10
7-0	RESERVED	R	0h	Reserved

1.1.5.70 CTRLMMR_I2C0_CTRL Register (Proxy0 Offset = 42E0h; Proxy1 Offset = 62E0h) [reset = 0h]

CTRLMMR_I2C0_CTRL is shown in Figure 5-86 and described in Table 5-188.

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Controls I2C0 operation for open drain I/Os.

Table 5-187 CTRLMMR_I2C0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 42E0h	4300 62E0h

Figure 5-86 CTRLMMR_I2C0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							HS_MCS_EN
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-188 CTRLMMR_I2C0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	HS_MCS_EN	R/W	0h	HS Mode master current source enable. When set, enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing.

1.1.5.71 CTRLMMR_FSS_CTRL Register (Proxy0 Offset = 4700h; Proxy1 Offset = 6700h) [reset = 0h]

CTRLMMR_FSS_CTRL is shown in Figure 5-87 and described in Table 5-190.

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Controls Flash boot region size and placement.

Table 5-189 CTRLMMR_FSS_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4700h	4300 6700h

Figure 5-87 CTRLMMR_FSS_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							S0_BOOT_SIZE
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED		S0_BOOT_SEG
R-0h		R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-190 CTRLMMR_FSS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	S0_BOOT_SIZE	R/W	0h	Selects the size of the boot block to be used for the S0 (OSPI0) flash interface 0h - S0 boot size is 64 MB 1h - S0 boot size is 128 MB
7-6	RESERVED	R	0h	Reserved
5-0	S0_BOOT_SEG	R/W	0h	Selects the boot block to be used for the S0 (OSPI0) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap the address of the flash. (e.g. if both ECC and authentication are enabled for 64 MB boot, the highest valid block number is is 49, as sector 50 is only .2M Bytes in size.) 6'h00 - Use block 0 6'h01 - Use block 1 : 6'h3F - Use block 63

1.1.5.72 CTRLMMR_ADC0_CTRL Register (Proxy0 Offset = 4710h; Proxy1 Offset = 6710h) [reset = 0h]

CTRLMMR_ADC0_CTRL is shown in Figure 5-88 and described in Table 5-192.

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Controls operation of ADC0.

Table 5-191 CTRLMMR_ADC0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4710h	4300 6710h

Figure 5-88 CTRLMMR_ADC0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							GPI_MODE_EN
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			TRIG_SEL
R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-192 CTRLMMR_ADC0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	GPI_MODE_EN	R/W	0h	Enables ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0
15-5	RESERVED	R	0h	Reserved
4-0	TRIG_SEL	R/W	0h	Selects the source of the ADC hardware event trigger 0h - ADC_EXT_TRIGGER0 Pin 1h - ADC_EXT_TRIGGER1 Pin 2h - EPWM SOCA_OUT 3h - EPWM SOCB_OUT 4h - MCU_TIMER0 PWM 5h - MCU_TIMER1 PWM 6h - MCU_TIMER2 PWM 7h - MCU_TIMER3 PWM 8h - TIMER0 PWM 9h - TIMER1 PWM Ah - TIMER2 PWM Bh - TIMER3 PWM Ch - TIMER4 PWM Dh - TIMER5 PWM Eh - TIMER6 PWM Fh - TIMER7 PWM 10h - TIMER8 PWM 11h - TIMER9 PWM 12h - TIMER10 PWM 13h - TIMER11 PWM 14h - ICSSG0 PR1 IEP0 15h - ICSSG0 PR1 IEP1 16h - ICSSG1 PR1 IEP0 17h - ICSSG1 PR1 IEP1 18h - ICSSG0 PR1 HOST INTR PEND4 19h - ICSSG0 PR1 HOST INTR PEND5 1Ah - ICSSG1 PR1 HOST INTR PEND4 1Bh - ICSSG1 PR1 HOST INTR PEND5

1.1.5.73 CTRLMMR_DCC_STAT Register (Proxy0 Offset = 4750h; Proxy1 Offset = 6750h) [reset = X]

CTRLMMR_DCC_STAT is shown in Figure 5-89 and described in Table 5-194.

Return to Summary Table.

Interrupt Status of Individual DCC Ips.

Table 5-193 CTRLMMR_DCC_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 4750h	4300 6750h

Figure 5-89 CTRLMMR_DCC_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MCU_DCC0_INTR_DONE
R-0h							R-X

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		DCC5_INTR_DONE	DCC4_INTR_DONE	DCC3_INTR_DONE	DCC2_INTR_DONE	DCC1_INTR_DONE	DCC0_INTR_DONE
R-0h		R-X	R-X	R-X	R-X	R-X	R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-194 CTRLMMR_DCC_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MCU_DCC0_INTR_DONE	R	X	MCU_DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
15-6	RESERVED	R	0h	Reserved
5	DCC5_INTR_DONE	R	X	DCC5 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
4	DCC4_INTR_DONE	R	X	DCC4 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
3	DCC3_INTR_DONE	R	X	DCC3 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
2	DCC2_INTR_DONE	R	X	DCC2 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
1	DCC1_INTR_DONE	R	X	DCC1 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending
0	DCC0_INTR_DONE	R	X	DCC0 Done Interrupt Status 0 = No Interrupt Pending 1 = Interrupt Pending

1.1.5.74 CTRLMMR_LOCK1_KICK0 Register (Proxy0 Offset = 5008h; Proxy1 Offset = 7008h) [reset = 0h]

CTRLMMR_LOCK1_KICK0 is shown in Figure 5-90 and described in Table 5-196.

Return to Summary Table.

Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written.

Table 5-195 CTRLMMR_LOCK1_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5008h	4300 7008h

Figure 5-90 CTRLMMR_LOCK1_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-196 CTRLMMR_LOCK1_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.75 CTRLMMR_LOCK1_KICK1 Register (Proxy0 Offset = 500Ch; Proxy1 Offset = 700Ch) [reset = 0h]

CTRLMMR_LOCK1_KICK1 is shown in Figure 5-91 and described in Table 5-198.

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Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written.

Table 5-197 CTRLMMR_LOCK1_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 500Ch	4300 700Ch

Figure 5-91 CTRLMMR_LOCK1_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-198 CTRLMMR_LOCK1_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

1.1.5.76 CTRLMMR_P1_CLAIM0 Register (Proxy0 Offset = 5100h; Proxy1 Offset = 7100h) [reset = 0h]

CTRLMMR_P1_CLAIM0 is shown in Figure 5-92 and described in Table 5-200.

Return to Summary Table.

Claim bits for Partition1 Registers.

Table 5-199 CTRLMMR_P1_CLAIM0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5100h	4300 7100h

Figure 5-92 CTRLMMR_P1_CLAIM0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-200 CTRLMMR_P1_CLAIM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (0 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (0 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.77 CTRLMMR_P1_CLAIM1 Register (Proxy0 Offset = 5104h; Proxy1 Offset = 7104h) [reset = 0h]

CTRLMMR_P1_CLAIM1 is shown in Figure 5-93 and described in Table 5-202.

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Claim bits for Partition1 Registers.

Table 5-201 CTRLMMR_P1_CLAIM1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5104h	4300 7104h

Figure 5-93 CTRLMMR_P1_CLAIM1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-202 CTRLMMR_P1_CLAIM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (1 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (1 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.78 CTRLMMR_P1_CLAIM2 Register (Proxy0 Offset = 5108h; Proxy1 Offset = 7108h) [reset = 0h]

CTRLMMR_P1_CLAIM2 is shown in Figure 5-94 and described in Table 5-204.

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Claim bits for Partition1 Registers.

Table 5-203 CTRLMMR_P1_CLAIM2 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5108h	4300 7108h

Figure 5-94 CTRLMMR_P1_CLAIM2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-204 CTRLMMR_P1_CLAIM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (2 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (2 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.79 CTRLMMR_P1_CLAIM3 Register (Proxy0 Offset = 510Ch; Proxy1 Offset = 710Ch) [reset = 0h]

CTRLMMR_P1_CLAIM3 is shown in Figure 5-95 and described in Table 5-206.

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Claim bits for Partition1 Registers.

Table 5-205 CTRLMMR_P1_CLAIM3 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 510Ch	4300 710Ch

Figure 5-95 CTRLMMR_P1_CLAIM3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-206 CTRLMMR_P1_CLAIM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (3 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (3 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.80 CTRLMMR_P1_CLAIM4 Register (Proxy0 Offset = 5110h; Proxy1 Offset = 7110h) [reset = 0h]

CTRLMMR_P1_CLAIM4 is shown in Figure 5-96 and described in Table 5-208.

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Claim bits for Partition1 Registers.

Table 5-207 CTRLMMR_P1_CLAIM4 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5110h	4300 7110h

Figure 5-96 CTRLMMR_P1_CLAIM4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-208 CTRLMMR_P1_CLAIM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (4 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (4 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.81 CTRLMMR_P1_CLAIM5 Register (Proxy0 Offset = 5114h; Proxy1 Offset = 7114h) [reset = 0h]

CTRLMMR_P1_CLAIM5 is shown in Figure 5-97 and described in Table 5-210.

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Claim bits for Partition1 Registers.

Table 5-209 CTRLMMR_P1_CLAIM5 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5114h	4300 7114h

Figure 5-97 CTRLMMR_P1_CLAIM5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-210 CTRLMMR_P1_CLAIM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (5 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (5 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.82 CTRLMMR_P1_CLAIM12 Register (Proxy0 Offset = 5130h; Proxy1 Offset = 7130h) [reset = 0h]

CTRLMMR_P1_CLAIM12 is shown in Figure 5-98 and described in Table 5-212.

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Claim bits for Partition1 Registers.

Table 5-211 CTRLMMR_P1_CLAIM12 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5130h	4300 7130h

Figure 5-98 CTRLMMR_P1_CLAIM12 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-212 CTRLMMR_P1_CLAIM12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (12 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (12 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.83 CTRLMMR_P1_CLAIM13 Register (Proxy0 Offset = 5134h; Proxy1 Offset = 7134h) [reset = 0h]

CTRLMMR_P1_CLAIM13 is shown in Figure 5-99 and described in Table 5-214.

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Claim bits for Partition1 Registers.

Table 5-213 CTRLMMR_P1_CLAIM13 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5134h	4300 7134h

Figure 5-99 CTRLMMR_P1_CLAIM13 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-214 CTRLMMR_P1_CLAIM13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (13 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (13 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.84 CTRLMMR_P1_CLAIM14 Register (Proxy0 Offset = 5138h; Proxy1 Offset = 7138h) [reset = 0h]

CTRLMMR_P1_CLAIM14 is shown in Figure 5-100 and described in Table 5-216.

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Claim bits for Partition1 Registers.

Table 5-215 CTRLMMR_P1_CLAIM14 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 5138h	4300 7138h

Figure 5-100 CTRLMMR_P1_CLAIM14 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-216 CTRLMMR_P1_CLAIM14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x4000 + (14 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x6000 + (14 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.85 CTRLMMR_OBSCLK0_CTRL Register (Proxy0 Offset = 8000h; Proxy1 Offset = A000h) [reset = Dh]

CTRLMMR_OBSCLK0_CTRL is shown in Figure 5-101 and described in Table 5-218.

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This register controls which internal clock is made observable on the OBSCLK[2:0] output pins.

Table 5-217 CTRLMMR_OBSCLK0_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8000h	4300 A000h

Figure 5-101 CTRLMMR_OBSCLK0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
CLK_DIV
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CLK_SEL
R-0h				R/W-Dh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-218 CTRLMMR_OBSCLK0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-8	CLK_DIV	R/W	0h	OBSCLK0 output divider Divides the selected clock by clkdiv+1 for output to the OBSCLK[2:0] pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1.
7-4	RESERVED	R	0h	Reserved
3-0	CLK_SEL	R/W	Dh	OBSCLK0 clock source selection. Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK0 pin. 0h - MAIN_PLL0_HSDIV0_CLKOUT 1h - MAIN_PLL1_HSDIV0_CLKOUT 2h - MAIN_PLL2_HSDIV0_CLKOUT 3h - MAIN_PLL8_HSDIV0_CLKOUT 4h - MAIN_PLL12_HSDIV0_CLKOUT 5h - CLK_12M_RC 6h - HFOSC0_CLKOUT_32K 7h - PLLCTRL_OBSCLK 8h - HFOSC0_CLKOUT 9h - CLK_32K Ah - cpsw3g_cpts_genf0 Bh - cpsw3g_cpts_genf1 Ch - cpts_genf1 Dh - cpts_genf2 Eh - cpts_genf3 Fh - MAIN_PLL14_HSDIV0_CLKOUT

1.1.5.86 CTRLMMR_CLKOUT_CTRL Register (Proxy0 Offset = 8010h; Proxy1 Offset = A010h) [reset = 0h]

CTRLMMR_CLKOUT_CTRL is shown in Figure 5-102 and described in Table 5-220.

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Enables and selects clock source of CPSW CLKOUT pin.

Table 5-219 CTRLMMR_CLKOUT_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8010h	4300 A010h

Figure 5-102 CTRLMMR_CLKOUT_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			CLK_EN	RESERVED			CLK_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-220 CTRLMMR_CLKOUT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	CLK_EN	R/W	0h	When set, enables CLKOUT output
3-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects CLKOUT clock source 0h - RGMII_MHZ_50_CLK (50 MHz) 1h -RGMII_MHZ_50_CLK_DIV2 (25 MHz)

1.1.5.87 CTRLMMR_GTC_CLKSEL Register (Proxy0 Offset = 8030h; Proxy1 Offset = A030h) [reset = 0h]

CTRLMMR_GTC_CLKSEL is shown in Figure 5-103 and described in Table 5-222.

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Selects the timebase clock source for the Global Timebase Counter.

Table 5-221 CTRLMMR_GTC_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8030h	4300 A030h

Figure 5-103 CTRLMMR_GTC_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-222 CTRLMMR_GTC_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Selects the GTC timebase clock source

0h - MAIN_PLL2_HSDIV5_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - CPSW3G_CPTS_RFT_CLK (Pin)

3h - CPTS_RFT_CLK (Pin)

4h - MCU_EXT_REFCLK0 (Pin)

5h - EXT_REFCLK1 (Pin)

6h - SERDES0_IP1_LN0_TXMCLK

7h - MAIN_SYSCLK0

1.1.5.88 CTRLMMR_EFUSE_CLKSEL Register (Proxy0 Offset = 803Ch; Proxy1 Offset = A03Ch) [reset = 0h]

CTRLMMR_EFUSE_CLKSEL is shown in Figure 5-104 and described in Table 5-224.

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Selects the functional clock source for the MAIN domain eFuse Controller.

Table 5-223 CTRLMMR_EFUSE_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 803Ch	4300 A03Ch

Figure 5-104 CTRLMMR_EFUSE_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-224 CTRLMMR_EFUSE_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-1

RESERVED

R

0h

Reserved

0

CLK_SEL

R/W

0h

Selects the clock source

0h - HFOSC0_CLKOUT

1h - MAIN_SYSCLK0/4

1.1.5.89 CTRLMMR_ICSSG0_CLKSEL Register (Proxy0 Offset = 8040h; Proxy1 Offset = A040h) [reset = 0h]

CTRLMMR_ICSSG0_CLKSEL is shown in Figure 5-105 and described in Table 5-226.

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Selects the functional clock source for ICSS_G0.

Table 5-225 CTRLMMR_ICSSG0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8040h	4300 A040h

Figure 5-105 CTRLMMR_ICSSG0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED					IEP_CLKSEL
R-0h					R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CORE_CLKSEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-226 CTRLMMR_ICSSG0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	0h	Reserved
18-16	IEP_CLKSEL	R/W	0h	Selects the ICSSG0 IEP clock source 0h - MAIN_PLL2_HSDIV5_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - CPSW3G_CPTS_RFT_CLK 3h - CPTS_RFT_CLK 4h - MCU_EXT_REFCLK0 5h - EXT_REFCLK1 6h - SERDES0_IP1_LN0_TXMCLK 7h - MAIN_SYSCLK0
15-1	RESERVED	R	0h	Reserved
0	CORE_CLKSEL	R/W	0h	Selects the ICSSG0 functional clock source 0h - MAIN_PLL2_HSDIV0_CLKOUT 1h - MAIN_PLL0_HSDIV9_CLKOUT

1.1.5.90 CTRLMMR_ICSSG1_CLKSEL Register (Proxy0 Offset = 8044h; Proxy1 Offset = A044h) [reset = 0h]

CTRLMMR_ICSSG1_CLKSEL is shown in Figure 5-106 and described in Table 5-228.

Return to Summary Table.

Selects the functional clock source for ICSS_G1.

Table 5-227 CTRLMMR_ICSSG1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8044h	4300 A044h

Figure 5-106 CTRLMMR_ICSSG1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED					IEP_CLKSEL
R-0h					R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CORE_CLKSEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-228 CTRLMMR_ICSSG1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	0h	Reserved
18-16	IEP_CLKSEL	R/W	0h	Selects the ICSSG1 IEP clock source 0h - MAIN_PLL2_HSDIV5_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - CPSW3G_CPTS_RFT_CLK 3h - CPTS_RFT_CLK 4h - MCU_EXT_REFCLK0 5h - EXT_REFCLK1 6h - SERDES0_IP1_LN0_TXMCLK 7h - MAIN_SYSCLK0
15-1	RESERVED	R	0h	Reserved
0	CORE_CLKSEL	R/W	0h	Selects the ICSSG1 functional clock source 0h - MAIN_PLL2_HSDIV0_CLKOUT 1h - MAIN_PLL0_HSDIV9_CLKOUT

1.1.5.91 CTRLMMR_MAIN_PLL0_CLKSEL Register (Proxy0 Offset = 8060h; Proxy1 Offset = A060h) [reset = 0h]

CTRLMMR_MAIN_PLL0_CLKSEL is shown in Figure 5-107 and described in Table 5-230.

Return to Summary Table.

Controls the clock source for MAIN voltage domain PLL0.

Table 5-229 CTRLMMR_MAIN_PLL0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8060h	4300 A060h

Figure 5-107 CTRLMMR_MAIN_PLL0_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-230 CTRLMMR_MAIN_PLL0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL0. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	0h	PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b0) when a MAIN warm reset occurs to keep MAIN PLL0 from being bypassed, supporting reset isolation of the CPSW. 1'b0 = Exit bypass mode (based on MAIN PLL0_CTRL_bypass_en bit value) 1'b1 = Maintain bypass mode.
22-0	RESERVED	R	0h	Reserved

1.1.5.92 CTRLMMR_MAIN_PLL1_CLKSEL Register (Proxy0 Offset = 8064h; Proxy1 Offset = A064h) [reset = 0h]

CTRLMMR_MAIN_PLL1_CLKSEL is shown in Figure 5-108 and described in Table 5-232.

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Controls the clock source for MAIN voltage domain PLL1.

Table 5-231 CTRLMMR_MAIN_PLL1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8064h	4300 A064h

Figure 5-108 CTRLMMR_MAIN_PLL1_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-232 CTRLMMR_MAIN_PLL1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL1 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	0h	PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL1 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because MAIN PLL1 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event.
22-0	RESERVED	R	0h	Reserved

1.1.5.93 CTRLMMR_MAIN_PLL2_CLKSEL Register (Proxy0 Offset = 8068h; Proxy1 Offset = A068h) [reset = 0h]

CTRLMMR_MAIN_PLL2_CLKSEL is shown in Figure 5-109 and described in Table 5-234.

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Controls the clock source for MAIN voltage domain PLL2.

Table 5-233 CTRLMMR_MAIN_PLL2_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8068h	4300 A068h

Figure 5-109 CTRLMMR_MAIN_PLL2_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-0h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-234 CTRLMMR_MAIN_PLL2_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override This bit has no effect on PLL operation as MAIN PLL2 is reset isolated and exit from bypass mode (in the case of a Thermal reset) is always hardware controlled.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	0h	PLL bypass mode after warm reset. This bit is cleared to 1'b0 when a MAIN warm reset occurs which will cause MAIN PLL2 to exit bypass mode after reset exit. Setting this bit will have no effect on PLL behaviot. Because MAIN PLL2 is warm reset insensitive, bypass mode will only be entered (and exited) in the case of a Thermal reset event.
22-0	RESERVED	R	0h	Reserved

1.1.5.94 CTRLMMR_MAIN_PLL8_CLKSEL Register (Proxy0 Offset = 8080h; Proxy1 Offset = A080h) [reset = 800000h]

CTRLMMR_MAIN_PLL8_CLKSEL is shown in Figure 5-110 and described in Table 5-236.

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Controls the clock source for MAIN voltage domain PLL8.

Table 5-235 CTRLMMR_MAIN_PLL8_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8080h	4300 A080h

Figure 5-110 CTRLMMR_MAIN_PLL8_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-1h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-236 CTRLMMR_MAIN_PLL8_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL8. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	1h	PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL8 in bypass mode after reset exit until cleared by software. 1'b0 = Exit bypass mode (based on MAIN PLL8_CTRL_bypass_en bit value) 1'b1 = Maintain bypass mode.
22-0	RESERVED	R	0h	Reserved

1.1.5.95 CTRLMMR_MAIN_PLL12_CLKSEL Register (Proxy0 Offset = 8090h; Proxy1 Offset = A090h) [reset = 800000h]

CTRLMMR_MAIN_PLL12_CLKSEL is shown in Figure 5-111 and described in Table 5-238.

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Controls the clock source for MAIN voltage domain PLL12.

Table 5-237 CTRLMMR_MAIN_PLL12_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8090h	4300 A090h

Figure 5-111 CTRLMMR_MAIN_PLL12_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-1h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-238 CTRLMMR_MAIN_PLL12_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL12. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	1h	PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL12 in bypass mode after reset exit until cleared by software. 1'b0 = Exit bypass mode (based on MAIN PLL12_CTRL_bypass_en bit value) 1'b1 = Maintain bypass mode.
22-0	RESERVED	R	0h	Reserved

1.1.5.96 CTRLMMR_MAIN_PLL14_CLKSEL Register (Proxy0 Offset = 8098h; Proxy1 Offset = A098h) [reset = 800000h]

CTRLMMR_MAIN_PLL14_CLKSEL is shown in Figure 5-112 and described in Table 5-240.

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Controls the clock source for MAIN voltage domain PLL14.

Table 5-239 CTRLMMR_MAIN_PLL14_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8098h	4300 A098h

Figure 5-112 CTRLMMR_MAIN_PLL14_CLKSEL Register

31	30	29	28	27	26	25	24
BYPASS_SW_OVRD	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
BYP_WARM_RST	RESERVED
R/W-1h	R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-240 CTRLMMR_MAIN_PLL14_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BYPASS_SW_OVRD	R/W	0h	PLL Bypass warm reset software override When set, enables software control of exit from bypass mode on a main_reset_z for MAIN PLL14. This bit must not be set until after the corresponding byp_warm_rst bit has been cleared or the PLL will immediately enter bypass mode.
30-24	RESERVED	R	0h	Reserved
23	BYP_WARM_RST	R/W	1h	PLL bypass mode after warm reset. This bit is only valid when bypass_sw_ovrd is set to 1'b1 to enable bypass software override. This bit is set (1'b1) when a MAIN warm reset occurs and will keep MAIN PLL14 in bypass mode after reset exit until cleared by software. 1'b0 = Exit bypass mode (based on MAIN PLL14_CTRL_bypass_en bit value) 1'b1 = Maintain bypass mode.
22-0	RESERVED	R	0h	Reserved

1.1.5.97 CTRLMMR_PCIE0_CLKSEL Register (Proxy0 Offset = 8120h; Proxy1 Offset = A120h) [reset = 0h]

CTRLMMR_PCIE0_CLKSEL is shown in Figure 5-113 and described in Table 5-242.

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Selects PCIe0 functional clock sources.

Table 5-241 CTRLMMR_PCIE0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8120h	4300 A120h

Figure 5-113 CTRLMMR_PCIE0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CPTS_CLKSEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-242 CTRLMMR_PCIE0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CPTS_CLKSEL

R/W

0h

Selects the clock source for the PCIE0 Common Platform Time Stamp module

0h - MAIN_PLL2_HSDIV5_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - CPSW3G_CPTS_RFT_CLK (Pin)

3h - CPTS_RFT_CLK (Pin)

4h - MCU_EXT_REFCLK0 (Pin)

5h - EXT_REFCLK1 (Pin)

6h - SERDES0_IP1_LN0_TXMCLK

7h - MAIN_SYSCLK0

1.1.5.98 CTRLMMR_CPSW_CLKSEL Register (Proxy0 Offset = 8140h; Proxy1 Offset = A140h) [reset = 0h]

CTRLMMR_CPSW_CLKSEL is shown in Figure 5-114 and described in Table 5-244.

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Selects the CP Switch clock sources.

Table 5-243 CTRLMMR_CPSW_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8140h	4300 A140h

Figure 5-114 CTRLMMR_CPSW_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				CPTS_CLKSEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-244 CTRLMMR_CPSW_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CPTS_CLKSEL

R/W

0h

Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module

0h - MAIN_PLL2_HSDIV5_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - CPSW3G_CPTS_RFT_CLK (Pin)

3h - CPTS_RFT_CLK (Pin)

4h - MCU_EXT_REFCLK0 (Pin)

5h - EXT_REFCLK1 (Pin)

6h - SERDES0_IP1_LN0_TXMCLK

7h - MAIN_SYSCLK0

1.1.5.99 CTRLMMR_CPTS_CLKSEL Register (Proxy0 Offset = 8150h; Proxy1 Offset = A150h) [reset = 0h]

CTRLMMR_CPTS_CLKSEL is shown in Figure 5-115 and described in Table 5-246.

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Selects the clock source for the Common Platform Time Sync Module.

Table 5-245 CTRLMMR_CPTS_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8150h	4300 A150h

Figure 5-115 CTRLMMR_CPTS_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CPTS_CLKSEL_CPTS_CLKSEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-246 CTRLMMR_CPTS_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CPTS_CLKSEL_CPTS_CLKSEL

R/W

0h

Selects the clock source for the SoC Common Platform Time Stamp module

0h - MAIN_PLL2_HSDIV5_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - CPSW3G_CPTS_RFT_CLK (Pin)

3h - CPTS_RFT_CLK (Pin)

4h - MCU_EXT_REFCLK0 (Pin)

5h - EXT_REFCLK1 (Pin)

6h - SERDES0_IP1_LN0_TXMCLK

7h - MAIN_SYSCLK0

1.1.5.100 CTRLMMR_EMMC0_CLKSEL Register (Proxy0 Offset = 8160h; Proxy1 Offset = A160h) [reset = 0h]

CTRLMMR_EMMC0_CLKSEL is shown in Figure 5-116 and described in Table 5-248.

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Selects the functional clock source for 8-bit eMMC0.

Table 5-247 CTRLMMR_EMMC0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8160h	4300 A160h

Figure 5-116 CTRLMMR_EMMC0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EMMCSD0_REFCLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-248 CTRLMMR_EMMC0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	EMMCSD0_REFCLK_SEL	R/W	0h	eMMC XIN_CLK selection 0h - MAIN_PLL0_HSDIV5_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT

1.1.5.101 CTRLMMR_EMMC1_CLKSEL Register (Proxy0 Offset = 8168h; Proxy1 Offset = A168h) [reset = 1h]

CTRLMMR_EMMC1_CLKSEL is shown in Figure 5-117 and described in Table 5-250.

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Selects the functional clock source for 4-bit eMMC1.

Table 5-249 CTRLMMR_EMMC1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8168h	4300 A168h

Figure 5-117 CTRLMMR_EMMC1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							EMMCSD1_IO_CLKLB_SEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							EMMCSD1_REFCLK_SEL
R-0h							R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-250 CTRLMMR_EMMC1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	EMMCSD1_IO_CLKLB_SEL	R/W	0h	eMMC IO Clock Selection: 0h - Loopback from Unbonded Pad MMCSD1_CLKLB 1h - Loopback from IO Pin MMCSD1_CLK
15-1	RESERVED	R	0h	Reserved
0	EMMCSD1_REFCLK_SEL	R/W	1h	eMMC XIN_CLK selection 0h - MAIN_PLL0_HSDIV5_CLKOUT 1h - MAIN_PLL2_HSDIV2_CLKOUT

1.1.5.102 CTRLMMR_GPMC_CLKSEL Register (Proxy0 Offset = 8180h; Proxy1 Offset = A180h) [reset = 0h]

CTRLMMR_GPMC_CLKSEL is shown in Figure 5-118 and described in Table 5-252.

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Selects the bus and functional clock source for the GPMC module. This allows the GPMC to run asynchronously to the bus fabric in order to optimize parallel port performance.

Table 5-251 CTRLMMR_GPMC_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8180h	4300 A180h

Figure 5-118 CTRLMMR_GPMC_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-252 CTRLMMR_GPMC_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the GPMC clock source 0h - MAIN_PLL0_HSDIV3_CLKOUT 1h - MAIN_PLL2_HSDIV3_CLKOUT

1.1.5.103 CTRLMMR_USB0_CLKSEL Register (Proxy0 Offset = 8190h; Proxy1 Offset = A190h) [reset = 0h]

CTRLMMR_USB0_CLKSEL is shown in Figure 5-119 and described in Table 5-254.

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Selects the functional clock sources for USB0.

Table 5-253 CTRLMMR_USB0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8190h	4300 A190h

Figure 5-119 CTRLMMR_USB0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							REFCLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-254 CTRLMMR_USB0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	REFCLK_SEL	R/W	0h	Selects the clock source for the USB0 ref_clk. 0h - Use HFOSC0_CLKOUT 1h - Use MAIN_PLL2_HSDIV4_CLKOUT

1.1.5.104 CTRLMMR_TIMER0_CLKSEL Register (Proxy0 Offset = 81B0h; Proxy1 Offset = A1B0h) [reset = 0h]

CTRLMMR_TIMER0_CLKSEL is shown in Figure 5-120 and described in Table 5-256.

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Timer0 functional clock selection control.

Table 5-255 CTRLMMR_TIMER0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81B0h	4300 A1B0h

Figure 5-120 CTRLMMR_TIMER0_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-256 CTRLMMR_TIMER0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.105 CTRLMMR_TIMER1_CLKSEL Register (Proxy0 Offset = 81B4h; Proxy1 Offset = A1B4h) [reset = 0h]

CTRLMMR_TIMER1_CLKSEL is shown in Figure 5-121 and described in Table 5-258.

Return to Summary Table.

Timer1 functional clock selection control.

Table 5-257 CTRLMMR_TIMER1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81B4h	4300 A1B4h

Figure 5-121 CTRLMMR_TIMER1_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-258 CTRLMMR_TIMER1_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.106 CTRLMMR_TIMER2_CLKSEL Register (Proxy0 Offset = 81B8h; Proxy1 Offset = A1B8h) [reset = 0h]

CTRLMMR_TIMER2_CLKSEL is shown in Figure 5-122 and described in Table 5-260.

Return to Summary Table.

Timer2 functional clock selection control.

Table 5-259 CTRLMMR_TIMER2_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81B8h	4300 A1B8h

Figure 5-122 CTRLMMR_TIMER2_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-260 CTRLMMR_TIMER2_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.107 CTRLMMR_TIMER3_CLKSEL Register (Proxy0 Offset = 81BCh; Proxy1 Offset = A1BCh) [reset = 0h]

CTRLMMR_TIMER3_CLKSEL is shown in Figure 5-123 and described in Table 5-262.

Return to Summary Table.

Timer3 functional clock selection control.

Table 5-261 CTRLMMR_TIMER3_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81BCh	4300 A1BCh

Figure 5-123 CTRLMMR_TIMER3_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-262 CTRLMMR_TIMER3_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.108 CTRLMMR_TIMER4_CLKSEL Register (Proxy0 Offset = 81C0h; Proxy1 Offset = A1C0h) [reset = 0h]

CTRLMMR_TIMER4_CLKSEL is shown in Figure 5-124 and described in Table 5-264.

Return to Summary Table.

Timer4 functional clock selection control.

Table 5-263 CTRLMMR_TIMER4_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81C0h	4300 A1C0h

Figure 5-124 CTRLMMR_TIMER4_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-264 CTRLMMR_TIMER4_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.109 CTRLMMR_TIMER5_CLKSEL Register (Proxy0 Offset = 81C4h; Proxy1 Offset = A1C4h) [reset = 0h]

CTRLMMR_TIMER5_CLKSEL is shown in Figure 5-125 and described in Table 5-266.

Return to Summary Table.

Timer5 functional clock selection control.

Table 5-265 CTRLMMR_TIMER5_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81C4h	4300 A1C4h

Figure 5-125 CTRLMMR_TIMER5_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-266 CTRLMMR_TIMER5_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.110 CTRLMMR_TIMER6_CLKSEL Register (Proxy0 Offset = 81C8h; Proxy1 Offset = A1C8h) [reset = 0h]

CTRLMMR_TIMER6_CLKSEL is shown in Figure 5-126 and described in Table 5-268.

Return to Summary Table.

Timer6 functional clock selection control.

Table 5-267 CTRLMMR_TIMER6_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81C8h	4300 A1C8h

Figure 5-126 CTRLMMR_TIMER6_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-268 CTRLMMR_TIMER6_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.111 CTRLMMR_TIMER7_CLKSEL Register (Proxy0 Offset = 81CCh; Proxy1 Offset = A1CCh) [reset = 0h]

CTRLMMR_TIMER7_CLKSEL is shown in Figure 5-127 and described in Table 5-270.

Return to Summary Table.

Timer7 functional clock selection control.

Table 5-269 CTRLMMR_TIMER7_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81CCh	4300 A1CCh

Figure 5-127 CTRLMMR_TIMER7_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-270 CTRLMMR_TIMER7_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.112 CTRLMMR_TIMER8_CLKSEL Register (Proxy0 Offset = 81D0h; Proxy1 Offset = A1D0h) [reset = 0h]

CTRLMMR_TIMER8_CLKSEL is shown in Figure 5-128 and described in Table 5-272.

Return to Summary Table.

Timer8 functional clock selection control.

Table 5-271 CTRLMMR_TIMER8_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81D0h	4300 A1D0h

Figure 5-128 CTRLMMR_TIMER8_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-272 CTRLMMR_TIMER8_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.113 CTRLMMR_TIMER9_CLKSEL Register (Proxy0 Offset = 81D4h; Proxy1 Offset = A1D4h) [reset = 0h]

CTRLMMR_TIMER9_CLKSEL is shown in Figure 5-129 and described in Table 5-274.

Return to Summary Table.

Timer9 functional clock selection control.

Table 5-273 CTRLMMR_TIMER9_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81D4h	4300 A1D4h

Figure 5-129 CTRLMMR_TIMER9_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-274 CTRLMMR_TIMER9_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.114 CTRLMMR_TIMER10_CLKSEL Register (Proxy0 Offset = 81D8h; Proxy1 Offset = A1D8h) [reset = 0h]

CTRLMMR_TIMER10_CLKSEL is shown in Figure 5-130 and described in Table 5-276.

Return to Summary Table.

Timer10 functional clock selection control.

Table 5-275 CTRLMMR_TIMER10_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81D8h	4300 A1D8h

Figure 5-130 CTRLMMR_TIMER10_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-276 CTRLMMR_TIMER10_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.115 CTRLMMR_TIMER11_CLKSEL Register (Proxy0 Offset = 81DCh; Proxy1 Offset = A1DCh) [reset = 0h]

CTRLMMR_TIMER11_CLKSEL is shown in Figure 5-131 and described in Table 5-278.

Return to Summary Table.

Timer11 functional clock selection control.

Table 5-277 CTRLMMR_TIMER11_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 81DCh	4300 A1DCh

Figure 5-131 CTRLMMR_TIMER11_CLKSEL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CLK_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-278 CTRLMMR_TIMER11_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control (Reserved values default to HFOSC0_CLK)

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - MAIN_PLL0_HSDIV7_CLKOUT

3h - CLK_12M_RC

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - CPTS_RFT_CLK (pin)

7h - CPSW3G_CPTS_RFT_CLK

8h - MAIN_PLL1_HSDIV3_CLKOUT

9h - MAIN_PLL2_HSDIV6_CLKOUT

Ah - CPSW3G_CPTS_GENF0

Bh - CPSW3G_CPTS_GENF1

Ch - CPTS_GENF1

Dh - CPTS_GENF2

Eh - CPTS_GENF3

Fh - CPTS_GENF4

1.1.5.116 CTRLMMR_SPI0_CLKSEL Register (Proxy0 Offset = 8200h; Proxy1 Offset = A200h) [reset = 0h]

CTRLMMR_SPI0_CLKSEL is shown in Figure 5-132 and described in Table 5-280.

Return to Summary Table.

SPI0 clock control.

Table 5-279 CTRLMMR_SPI0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8200h	4300 A200h

Figure 5-132 CTRLMMR_SPI0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MSTR_LB_CLKSEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-280 CTRLMMR_SPI0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MSTR_LB_CLKSEL	R/W	0h	Master mode receive capture clock loopback selection 0h - Internal clock loopback 1h - Loopback from pad
15-0	RESERVED	R	0h	Reserved

1.1.5.117 CTRLMMR_SPI1_CLKSEL Register (Proxy0 Offset = 8204h; Proxy1 Offset = A204h) [reset = 0h]

CTRLMMR_SPI1_CLKSEL is shown in Figure 5-133 and described in Table 5-282.

Return to Summary Table.

SPI1 clock control.

Table 5-281 CTRLMMR_SPI1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8204h	4300 A204h

Figure 5-133 CTRLMMR_SPI1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MSTR_LB_CLKSEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-282 CTRLMMR_SPI1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MSTR_LB_CLKSEL	R/W	0h	Master mode receive capture clock loopback selection 0h - Internal clock loopback 1h - Loopback from pad
15-0	RESERVED	R	0h	Reserved

1.1.5.118 CTRLMMR_SPI2_CLKSEL Register (Proxy0 Offset = 8208h; Proxy1 Offset = A208h) [reset = 0h]

CTRLMMR_SPI2_CLKSEL is shown in Figure 5-134 and described in Table 5-284.

Return to Summary Table.

SPI2 clock control.

Table 5-283 CTRLMMR_SPI2_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8208h	4300 A208h

Figure 5-134 CTRLMMR_SPI2_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MSTR_LB_CLKSEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-284 CTRLMMR_SPI2_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MSTR_LB_CLKSEL	R/W	0h	Master mode receive capture clock loopback selection 0h - Internal clock loopback 1h - Loopback from pad
15-0	RESERVED	R	0h	Reserved

1.1.5.119 CTRLMMR_SPI3_CLKSEL Register (Proxy0 Offset = 820Ch; Proxy1 Offset = A20Ch) [reset = 0h]

CTRLMMR_SPI3_CLKSEL is shown in Figure 5-135 and described in Table 5-286.

Return to Summary Table.

SPI3 clock control.

Table 5-285 CTRLMMR_SPI3_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 820Ch	4300 A20Ch

Figure 5-135 CTRLMMR_SPI3_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MSTR_LB_CLKSEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-286 CTRLMMR_SPI3_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MSTR_LB_CLKSEL	R/W	0h	Master mode receive capture clock loopback selection 0h - Internal clock loopback 1h - Loopback from pad
15-0	RESERVED	R	0h	Reserved

1.1.5.120 CTRLMMR_SPI4_CLKSEL Register (Proxy0 Offset = 8210h; Proxy1 Offset = A210h) [reset = 0h]

CTRLMMR_SPI4_CLKSEL is shown in Figure 5-136 and described in Table 5-288.

Return to Summary Table.

SPI4 clock control.

Table 5-287 CTRLMMR_SPI4_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8210h	4300 A210h

Figure 5-136 CTRLMMR_SPI4_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							MSTR_LB_CLKSEL
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-288 CTRLMMR_SPI4_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	MSTR_LB_CLKSEL	R/W	0h	Master mode receive capture clock loopback selection 0h - Internal clock loopback 1h - Loopback from pad
15-0	RESERVED	R	0h	Reserved

1.1.5.121 CTRLMMR_USART0_CLK_CTRL Register (Proxy0 Offset = 8240h; Proxy1 Offset = A240h) [reset = 3h]

CTRLMMR_USART0_CLK_CTRL is shown in Figure 5-137 and described in Table 5-290.

Return to Summary Table.

Selects the clock divider of the USART0 functional clock.

Table 5-289 CTRLMMR_USART0_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8240h	4300 A240h

Figure 5-137 CTRLMMR_USART0_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-290 CTRLMMR_USART0_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.122 CTRLMMR_USART1_CLK_CTRL Register (Proxy0 Offset = 8244h; Proxy1 Offset = A244h) [reset = 3h]

CTRLMMR_USART1_CLK_CTRL is shown in Figure 5-138 and described in Table 5-292.

Return to Summary Table.

Selects the clock divider of the USART1 functional clock.

Table 5-291 CTRLMMR_USART1_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8244h	4300 A244h

Figure 5-138 CTRLMMR_USART1_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-292 CTRLMMR_USART1_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.123 CTRLMMR_USART2_CLK_CTRL Register (Proxy0 Offset = 8248h; Proxy1 Offset = A248h) [reset = 3h]

CTRLMMR_USART2_CLK_CTRL is shown in Figure 5-139 and described in Table 5-294.

Return to Summary Table.

Selects the clock divider of the USART2 functional clock.

Table 5-293 CTRLMMR_USART2_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8248h	4300 A248h

Figure 5-139 CTRLMMR_USART2_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-294 CTRLMMR_USART2_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.124 CTRLMMR_USART3_CLK_CTRL Register (Proxy0 Offset = 824Ch; Proxy1 Offset = A24Ch) [reset = 3h]

CTRLMMR_USART3_CLK_CTRL is shown in Figure 5-140 and described in Table 5-296.

Return to Summary Table.

Selects the clock divider of the USART3 functional clock.

Table 5-295 CTRLMMR_USART3_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 824Ch	4300 A24Ch

Figure 5-140 CTRLMMR_USART3_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-296 CTRLMMR_USART3_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.125 CTRLMMR_USART4_CLK_CTRL Register (Proxy0 Offset = 8250h; Proxy1 Offset = A250h) [reset = 3h]

CTRLMMR_USART4_CLK_CTRL is shown in Figure 5-141 and described in Table 5-298.

Return to Summary Table.

Selects the clock divider of the USART4 functional clock.

Table 5-297 CTRLMMR_USART4_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8250h	4300 A250h

Figure 5-141 CTRLMMR_USART4_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-298 CTRLMMR_USART4_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.126 CTRLMMR_USART5_CLK_CTRL Register (Proxy0 Offset = 8254h; Proxy1 Offset = A254h) [reset = 3h]

CTRLMMR_USART5_CLK_CTRL is shown in Figure 5-142 and described in Table 5-300.

Return to Summary Table.

Selects the clock divider of the USART5 functional clock.

Table 5-299 CTRLMMR_USART5_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8254h	4300 A254h

Figure 5-142 CTRLMMR_USART5_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-300 CTRLMMR_USART5_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.127 CTRLMMR_USART6_CLK_CTRL Register (Proxy0 Offset = 8258h; Proxy1 Offset = A258h) [reset = 3h]

CTRLMMR_USART6_CLK_CTRL is shown in Figure 5-143 and described in Table 5-302.

Return to Summary Table.

Selects the clock divider of the USART6 functional clock.

Table 5-301 CTRLMMR_USART6_CLK_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8258h	4300 A258h

Figure 5-143 CTRLMMR_USART6_CLK_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							CLK_DIV_LD
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_DIV
R-0h						R/W-3h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-302 CTRLMMR_USART6_CLK_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	CLK_DIV_LD	R/W	0h	Load the output divider value Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.
15-2	RESERVED	R	0h	Reserved
1-0	CLK_DIV	R/W	3h	Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1. 0h - Divide by 1 1h - Divide by 2 2h - Divide by 3 3h - Divide by 4

1.1.5.128 CTRLMMR_USART0_CLKSEL Register (Proxy0 Offset = 8280h; Proxy1 Offset = A280h) [reset = 0h]

CTRLMMR_USART0_CLKSEL is shown in Figure 5-144 and described in Table 5-304.

Return to Summary Table.

Selects the clock source for USART0 functional clock.

Table 5-303 CTRLMMR_USART0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8280h	4300 A280h

Figure 5-144 CTRLMMR_USART0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-304 CTRLMMR_USART0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART0: 0 = Clock Divider Controlled by CTRLMMR_USART0_CLK_CTRL is the clock source for USART0 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART0

1.1.5.129 CTRLMMR_USART1_CLKSEL Register (Proxy0 Offset = 8284h; Proxy1 Offset = A284h) [reset = 0h]

CTRLMMR_USART1_CLKSEL is shown in Figure 5-145 and described in Table 5-306.

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Selects the clock source for USART1 functional clock.

Table 5-305 CTRLMMR_USART1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8284h	4300 A284h

Figure 5-145 CTRLMMR_USART1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-306 CTRLMMR_USART1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART1: 0 = Clock Divider Controlled by CTRLMMR_USART1_CLK_CTRL is the clock source for USART1 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART1

1.1.5.130 CTRLMMR_USART2_CLKSEL Register (Proxy0 Offset = 8288h; Proxy1 Offset = A288h) [reset = 0h]

CTRLMMR_USART2_CLKSEL is shown in Figure 5-146 and described in Table 5-308.

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Selects the clock source for USART2 functional clock.

Table 5-307 CTRLMMR_USART2_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8288h	4300 A288h

Figure 5-146 CTRLMMR_USART2_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-308 CTRLMMR_USART2_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART2: 0 = Clock Divider Controlled by CTRLMMR_USART2_CLK_CTRL is the clock source for USART2 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART2

1.1.5.131 CTRLMMR_USART3_CLKSEL Register (Proxy0 Offset = 828Ch; Proxy1 Offset = A28Ch) [reset = 0h]

CTRLMMR_USART3_CLKSEL is shown in Figure 5-147 and described in Table 5-310.

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Selects the clock source for USART3 functional clock.

Table 5-309 CTRLMMR_USART3_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 828Ch	4300 A28Ch

Figure 5-147 CTRLMMR_USART3_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-310 CTRLMMR_USART3_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART3: 0 = Clock Divider Controlled by CTRLMMR_USART3_CLK_CTRL is the clock source for USART3 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART3

1.1.5.132 CTRLMMR_USART4_CLKSEL Register (Proxy0 Offset = 8290h; Proxy1 Offset = A290h) [reset = 0h]

CTRLMMR_USART4_CLKSEL is shown in Figure 5-148 and described in Table 5-312.

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Selects the clock source for USART4 functional clock.

Table 5-311 CTRLMMR_USART4_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8290h	4300 A290h

Figure 5-148 CTRLMMR_USART4_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-312 CTRLMMR_USART4_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART4: 0 = Clock Divider Controlled by CTRLMMR_USART4_CLK_CTRL is the clock source for USART4 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART4

1.1.5.133 CTRLMMR_USART5_CLKSEL Register (Proxy0 Offset = 8294h; Proxy1 Offset = A294h) [reset = 0h]

CTRLMMR_USART5_CLKSEL is shown in Figure 5-149 and described in Table 5-314.

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Selects the clock source for USART5 functional clock.

Table 5-313 CTRLMMR_USART5_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8294h	4300 A294h

Figure 5-149 CTRLMMR_USART5_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-314 CTRLMMR_USART5_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART5: 0 = Clock Divider Controlled by CTRLMMR_USART5_CLK_CTRL is the clock source for USART5 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART5

1.1.5.134 CTRLMMR_USART6_CLKSEL Register (Proxy0 Offset = 8298h; Proxy1 Offset = A298h) [reset = 0h]

CTRLMMR_USART6_CLKSEL is shown in Figure 5-150 and described in Table 5-316.

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Selects the clock source for USART6 functional clock.

Table 5-315 CTRLMMR_USART6_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8298h	4300 A298h

Figure 5-150 CTRLMMR_USART6_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-316 CTRLMMR_USART6_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the clock source for UART6: 0 = Clock Divider Controlled by CTRLMMR_USART6_CLK_CTRL is the clock source for USART6 1 = MAIN_PLL1_HSDIV1_CLKOUT is the clock source for USART6

1.1.5.135 CTRLMMR_WWD0_CLKSEL Register (Proxy0 Offset = 8380h; Proxy1 Offset = A380h) [reset = 0h]

CTRLMMR_WWD0_CLKSEL is shown in Figure 5-151 and described in Table 5-318.

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ARM MPU Core 0 Windowed watchdog timer functional clock selection control.

Table 5-317 CTRLMMR_WWD0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8380h	4300 A380h

Figure 5-151 CTRLMMR_WWD0_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-318 CTRLMMR_WWD0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD0_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.136 CTRLMMR_WWD1_CLKSEL Register (Proxy0 Offset = 8384h; Proxy1 Offset = A384h) [reset = 0h]

CTRLMMR_WWD1_CLKSEL is shown in Figure 5-152 and described in Table 5-320.

Return to Summary Table.

ARM MPU Core 1 Windowed watchdog timer functional clock selection control.

Table 5-319 CTRLMMR_WWD1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8384h	4300 A384h

Figure 5-152 CTRLMMR_WWD1_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-320 CTRLMMR_WWD1_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD1_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.137 CTRLMMR_WWD8_CLKSEL Register (Proxy0 Offset = 83A0h; Proxy1 Offset = A3A0h) [reset = 0h]

CTRLMMR_WWD8_CLKSEL is shown in Figure 5-153 and described in Table 5-322.

Return to Summary Table.

Main R5 Core 0 Windowed watchdog timer functional clock selection control.

Table 5-321 CTRLMMR_WWD8_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 83A0h	4300 A3A0h

Figure 5-153 CTRLMMR_WWD8_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-322 CTRLMMR_WWD8_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD8_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.138 CTRLMMR_WWD9_CLKSEL Register (Proxy0 Offset = 83A4h; Proxy1 Offset = A3A4h) [reset = 0h]

CTRLMMR_WWD9_CLKSEL is shown in Figure 5-154 and described in Table 5-324.

Return to Summary Table.

Main R5 Core 1 Windowed watchdog timer functional clock selection control.

Table 5-323 CTRLMMR_WWD9_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 83A4h	4300 A3A4h

Figure 5-154 CTRLMMR_WWD9_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-324 CTRLMMR_WWD9_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD9_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.139 CTRLMMR_WWD10_CLKSEL Register (Proxy0 Offset = 83A8h; Proxy1 Offset = A3A8h) [reset = 0h]

CTRLMMR_WWD10_CLKSEL is shown in Figure 5-155 and described in Table 5-326.

Return to Summary Table.

Main R5 Core 2 Windowed watchdog timer functional clock selection control.

Table 5-325 CTRLMMR_WWD10_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 83A8h	4300 A3A8h

Figure 5-155 CTRLMMR_WWD10_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-326 CTRLMMR_WWD10_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD10_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.140 CTRLMMR_WWD11_CLKSEL Register (Proxy0 Offset = 83ACh; Proxy1 Offset = A3ACh) [reset = 0h]

CTRLMMR_WWD11_CLKSEL is shown in Figure 5-156 and described in Table 5-328.

Return to Summary Table.

Main R5 Core 3 Windowed watchdog timer functional clock selection control.

Table 5-327 CTRLMMR_WWD11_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 83ACh	4300 A3ACh

Figure 5-156 CTRLMMR_WWD11_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-328 CTRLMMR_WWD11_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks CTRLMMR_WWD11_CLKSEL from further writes until the next module reset.

30-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC0_CLKOUT_32K

2h - CLK_12M_RC

3h - CLK_32K

1.1.5.141 CTRLMMR_SERDES0_CLKSEL Register (Proxy0 Offset = 8400h; Proxy1 Offset = A400h) [reset = 0h]

CTRLMMR_SERDES0_CLKSEL is shown in Figure 5-157 and described in Table 5-330.

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Selects the clock source for Serdes0.

Table 5-329 CTRLMMR_SERDES0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8400h	4300 A400h

Figure 5-157 CTRLMMR_SERDES0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CORE_REFCLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-330 CTRLMMR_SERDES0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

CORE_REFCLK_SEL

R/W

0h

Selects the source for the core_refclk input

0h - HFOSC0_CLKOUT_SERDES

1h - EXT_REFCLK1

2h - MAIN_PLL0_HSDIV8_CLKOUT

3h - MAIN_PLL2_HSDIV4_CLKOUT

1.1.5.142 CTRLMMR_MCAN0_CLKSEL Register (Proxy0 Offset = 8480h; Proxy1 Offset = A480h) [reset = 0h]

CTRLMMR_MCAN0_CLKSEL is shown in Figure 5-158 and described in Table 5-332.

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Controls the functional clock source MCAN0.

Table 5-331 CTRLMMR_MCAN0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8480h	4300 A480h

Figure 5-158 CTRLMMR_MCAN0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-332 CTRLMMR_MCAN0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CLK_SEL	R/W	0h	MAIN MCAN_CLK selection 0h - MAIN_PLL0_HSDIV2_CLKOUT 1h - MCU_EXT_REFCLK0 (pin) 2h - EXT_REFCLK0 (pin) 3h - HFOSC0_CLKOUT

1.1.5.143 CTRLMMR_MCAN1_CLKSEL Register (Proxy0 Offset = 8484h; Proxy1 Offset = A484h) [reset = 0h]

CTRLMMR_MCAN1_CLKSEL is shown in Figure 5-159 and described in Table 5-334.

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Controls the functional clock source MCAN1.

Table 5-333 CTRLMMR_MCAN1_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8484h	4300 A484h

Figure 5-159 CTRLMMR_MCAN1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-334 CTRLMMR_MCAN1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CLK_SEL	R/W	0h	MAIN MCAN_CLK selection 0h - MAIN_PLL0_HSDIV2_CLKOUT 1h - MCU_EXT_REFCLK0 (pin) 2h - EXT_REFCLK0 (pin) 3h - HFOSC0_CLKOUT

1.1.5.144 CTRLMMR_OSPI0_CLKSEL Register (Proxy0 Offset = 8500h; Proxy1 Offset = A500h) [reset = 0h]

CTRLMMR_OSPI0_CLKSEL is shown in Figure 5-160 and described in Table 5-336.

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Controls the OSPI loopback clock source.

Table 5-335 CTRLMMR_OSPI0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8500h	4300 A500h

Figure 5-160 CTRLMMR_OSPI0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			LOOPCLK_SEL	RESERVED			CLK_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-336 CTRLMMR_OSPI0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	LOOPCLK_SEL	R/W	0h	OBSPI0 Loopback clock source 0h - OSPI_DQS (Pin) 1h - OSPI_LBCLKO (Pin)
3-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	OSPI0 reference clock selection 0h - MAIN_PLL0_HSDIV1_CLKOUT 1h - MAIN_PLL1_HSDIV5_CLKOUT

1.1.5.145 CTRLMMR_ADC0_CLKSEL Register (Proxy0 Offset = 8510h; Proxy1 Offset = A510h) [reset = 0h]

CTRLMMR_ADC0_CLKSEL is shown in Figure 5-161 and described in Table 5-338.

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Controls the functional clock source for the ADC0.

Table 5-337 CTRLMMR_ADC0_CLKSEL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 8510h	4300 A510h

Figure 5-161 CTRLMMR_ADC0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-338 CTRLMMR_ADC0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Selects the sampling clock source for ADC0

0h - HFOSC0_CLKOUT

1h - MAIN_PLL1_HSDIV6_CLKOUT

2h - MAIN_PLL2_HSDIV8

3h - EXT_REFCLK1

1.1.5.146 CTRLMMR_LOCK2_KICK0 Register (Proxy0 Offset = 9008h; Proxy1 Offset = B008h) [reset = 0h]

CTRLMMR_LOCK2_KICK0 is shown in Figure 5-162 and described in Table 5-340.

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Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written.

Table 5-339 CTRLMMR_LOCK2_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9008h	4300 B008h

Figure 5-162 CTRLMMR_LOCK2_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-340 CTRLMMR_LOCK2_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.147 CTRLMMR_LOCK2_KICK1 Register (Proxy0 Offset = 900Ch; Proxy1 Offset = B00Ch) [reset = 0h]

CTRLMMR_LOCK2_KICK1 is shown in Figure 5-163 and described in Table 5-342.

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Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written.

Table 5-341 CTRLMMR_LOCK2_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 900Ch	4300 B00Ch

Figure 5-163 CTRLMMR_LOCK2_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-342 CTRLMMR_LOCK2_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

1.1.5.148 CTRLMMR_P2_CLAIM0 Register (Proxy0 Offset = 9100h; Proxy1 Offset = B100h) [reset = 0h]

CTRLMMR_P2_CLAIM0 is shown in Figure 5-164 and described in Table 5-344.

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Claim bits for Partition2 Registers.

Table 5-343 CTRLMMR_P2_CLAIM0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9100h	4300 B100h

Figure 5-164 CTRLMMR_P2_CLAIM0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-344 CTRLMMR_P2_CLAIM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (0 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (0 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.149 CTRLMMR_P2_CLAIM1 Register (Proxy0 Offset = 9104h; Proxy1 Offset = B104h) [reset = 0h]

CTRLMMR_P2_CLAIM1 is shown in Figure 5-165 and described in Table 5-346.

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Claim bits for Partition2 Registers.

Table 5-345 CTRLMMR_P2_CLAIM1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9104h	4300 B104h

Figure 5-165 CTRLMMR_P2_CLAIM1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-346 CTRLMMR_P2_CLAIM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (1 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (1 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.150 CTRLMMR_P2_CLAIM2 Register (Proxy0 Offset = 9108h; Proxy1 Offset = B108h) [reset = 0h]

CTRLMMR_P2_CLAIM2 is shown in Figure 5-166 and described in Table 5-348.

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Claim bits for Partition2 Registers.

Table 5-347 CTRLMMR_P2_CLAIM2 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9108h	4300 B108h

Figure 5-166 CTRLMMR_P2_CLAIM2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-348 CTRLMMR_P2_CLAIM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (2 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (2 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.151 CTRLMMR_P2_CLAIM3 Register (Proxy0 Offset = 910Ch; Proxy1 Offset = B10Ch) [reset = 0h]

CTRLMMR_P2_CLAIM3 is shown in Figure 5-167 and described in Table 5-350.

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Claim bits for Partition2 Registers.

Table 5-349 CTRLMMR_P2_CLAIM3 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 910Ch	4300 B10Ch

Figure 5-167 CTRLMMR_P2_CLAIM3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-350 CTRLMMR_P2_CLAIM3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (3 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (3 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.152 CTRLMMR_P2_CLAIM4 Register (Proxy0 Offset = 9110h; Proxy1 Offset = B110h) [reset = 0h]

CTRLMMR_P2_CLAIM4 is shown in Figure 5-168 and described in Table 5-352.

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Claim bits for Partition2 Registers.

Table 5-351 CTRLMMR_P2_CLAIM4 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9110h	4300 B110h

Figure 5-168 CTRLMMR_P2_CLAIM4 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-352 CTRLMMR_P2_CLAIM4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (4 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (4 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.153 CTRLMMR_P2_CLAIM5 Register (Proxy0 Offset = 9114h; Proxy1 Offset = B114h) [reset = 0h]

CTRLMMR_P2_CLAIM5 is shown in Figure 5-169 and described in Table 5-354.

Return to Summary Table.

Claim bits for Partition2 Registers.

Table 5-353 CTRLMMR_P2_CLAIM5 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9114h	4300 B114h

Figure 5-169 CTRLMMR_P2_CLAIM5 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-354 CTRLMMR_P2_CLAIM5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (5 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (5 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.154 CTRLMMR_P2_CLAIM6 Register (Proxy0 Offset = 9118h; Proxy1 Offset = B118h) [reset = 0h]

CTRLMMR_P2_CLAIM6 is shown in Figure 5-170 and described in Table 5-356.

Return to Summary Table.

Claim bits for Partition2 Registers.

Table 5-355 CTRLMMR_P2_CLAIM6 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9118h	4300 B118h

Figure 5-170 CTRLMMR_P2_CLAIM6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-356 CTRLMMR_P2_CLAIM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (6 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (6 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.155 CTRLMMR_P2_CLAIM7 Register (Proxy0 Offset = 911Ch; Proxy1 Offset = B11Ch) [reset = 0h]

CTRLMMR_P2_CLAIM7 is shown in Figure 5-171 and described in Table 5-358.

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Claim bits for Partition2 Registers.

Table 5-357 CTRLMMR_P2_CLAIM7 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 911Ch	4300 B11Ch

Figure 5-171 CTRLMMR_P2_CLAIM7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-358 CTRLMMR_P2_CLAIM7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (7 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (7 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.156 CTRLMMR_P2_CLAIM8 Register (Proxy0 Offset = 9120h; Proxy1 Offset = B120h) [reset = 0h]

CTRLMMR_P2_CLAIM8 is shown in Figure 5-172 and described in Table 5-360.

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Claim bits for Partition2 Registers.

Table 5-359 CTRLMMR_P2_CLAIM8 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9120h	4300 B120h

Figure 5-172 CTRLMMR_P2_CLAIM8 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-360 CTRLMMR_P2_CLAIM8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (8 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (8 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.157 CTRLMMR_P2_CLAIM9 Register (Proxy0 Offset = 9124h; Proxy1 Offset = B124h) [reset = 0h]

CTRLMMR_P2_CLAIM9 is shown in Figure 5-173 and described in Table 5-362.

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Claim bits for Partition2 Registers.

Table 5-361 CTRLMMR_P2_CLAIM9 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9124h	4300 B124h

Figure 5-173 CTRLMMR_P2_CLAIM9 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-362 CTRLMMR_P2_CLAIM9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (9 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (9 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.158 CTRLMMR_P2_CLAIM10 Register (Proxy0 Offset = 9128h; Proxy1 Offset = B128h) [reset = 0h]

CTRLMMR_P2_CLAIM10 is shown in Figure 5-174 and described in Table 5-364.

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Claim bits for Partition2 Registers.

Table 5-363 CTRLMMR_P2_CLAIM10 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 9128h	4300 B128h

Figure 5-174 CTRLMMR_P2_CLAIM10 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-364 CTRLMMR_P2_CLAIM10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x8000 + (10 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xA000 + (10 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.159 CTRLMMR_FUSE_CRC_STAT Register (Proxy0 Offset = C320h; Proxy1 Offset = E320h) [reset = X]

CTRLMMR_FUSE_CRC_STAT is shown in Figure 5-175 and described in Table 5-366.

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Indicates status of fuse chain CRC.

Table 5-365 CTRLMMR_FUSE_CRC_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 C320h	4300 E320h

Figure 5-175 CTRLMMR_FUSE_CRC_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
CRC_ERR_7	CRC_ERR_6	CRC_ERR_5	CRC_ERR_4	CRC_ERR_3	CRC_ERR_2	CRC_ERR_1	RESERVED
R-X	R-X	R-X	R-X	R-X	R-X	R-X	R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-366 CTRLMMR_FUSE_CRC_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	CRC_ERR_7	R	X	Indicates eFuse CRC error on chain 7
6	CRC_ERR_6	R	X	Indicates eFuse CRC error on chain 6
5	CRC_ERR_5	R	X	Indicates eFuse CRC error on chain 5
4	CRC_ERR_4	R	X	Indicates eFuse CRC error on chain 4
3	CRC_ERR_3	R	X	Indicates eFuse CRC error on chain 3
2	CRC_ERR_2	R	X	Indicates eFuse CRC error on chain 2
1	CRC_ERR_1	R	X	Indicates eFuse CRC error on chain 1
0	RESERVED	R	0h	Reserved

1.1.5.160 CTRLMMR_PBIST_EN Register (Proxy0 Offset = C400h; Proxy1 Offset = E400h) [reset = 0h]

CTRLMMR_PBIST_EN is shown in Figure 5-176 and described in Table 5-368.

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Enables PBIST Config Modes access to memories.

Table 5-367 CTRLMMR_PBIST_EN Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 C400h	4300 E400h

Figure 5-176 CTRLMMR_PBIST_EN Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							PCIE0
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED			USB0	RESERVED		EMMC1	EMMC0
R-0h			R/W-0h	R-0h		R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-368 CTRLMMR_PBIST_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	PCIE0	R/W	0h	Enables PBIST Access to PCIE0 Memories
7-5	RESERVED	R	0h	Reserved
4	USB0	R/W	0h	Enables PBIST Access to USB0 Memories
3-2	RESERVED	R	0h	Reserved
1	EMMC1	R/W	0h	Enables PBIST Access to MMC1 Memories
0	EMMC0	R/W	0h	Enables PBIST Access to MMC0 Memories

1.1.5.161 CTRLMMR_LOCK3_KICK0 Register (Proxy0 Offset = D008h; Proxy1 Offset = F008h) [reset = 0h]

CTRLMMR_LOCK3_KICK0 is shown in Figure 5-177 and described in Table 5-370.

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Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written.

Table 5-369 CTRLMMR_LOCK3_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 D008h	4300 F008h

Figure 5-177 CTRLMMR_LOCK3_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-370 CTRLMMR_LOCK3_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.162 CTRLMMR_LOCK3_KICK1 Register (Proxy0 Offset = D00Ch; Proxy1 Offset = F00Ch) [reset = 0h]

CTRLMMR_LOCK3_KICK1 is shown in Figure 5-178 and described in Table 5-372.

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Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written.

Table 5-371 CTRLMMR_LOCK3_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 D00Ch	4300 F00Ch

Figure 5-178 CTRLMMR_LOCK3_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-372 CTRLMMR_LOCK3_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers

1.1.5.163 CTRLMMR_P3_CLAIM6 Register (Proxy0 Offset = D118h; Proxy1 Offset = F118h) [reset = 0h]

CTRLMMR_P3_CLAIM6 is shown in Figure 5-179 and described in Table 5-374.

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Claim bits for Partition3 Registers.

Table 5-373 CTRLMMR_P3_CLAIM6 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4300 D118h	4300 F118h

Figure 5-179 CTRLMMR_P3_CLAIM6 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-374 CTRLMMR_P3_CLAIM6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0xC000 + (6 x 0x80) + (b x 0x4) and register Proxy1 address of: 0xE000 + (6 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.164 CTRLMMR_CHNG_DDR4_FSP_REQ Register (Proxy0 Offset = 14000h; Proxy1 Offset = 16000h) [reset = 0h]

CTRLMMR_CHNG_DDR4_FSP_REQ is shown in Figure 5-180 and described in Table 5-376.

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This register is used to initiate a LPDDR4 frequency set point change to the DDR Controller.

Table 5-375 CTRLMMR_CHNG_DDR4_FSP_REQ Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 4000h	4301 6000h

Figure 5-180 CTRLMMR_CHNG_DDR4_FSP_REQ Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							REQ
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED						REQ_TYPE
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-376 CTRLMMR_CHNG_DDR4_FSP_REQ Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	REQ	R/W	0h	Initiate FSP frequency change
7-2	RESERVED	R	0h	Reserved
1-0	REQ_TYPE	R/W	0h	Frequency request type Indicates which DDR4 frequency set point to change to

1.1.5.165 CTRLMMR_CHNG_DDR4_FSP_ACK Register (Proxy0 Offset = 14004h; Proxy1 Offset = 16004h) [reset = X]

CTRLMMR_CHNG_DDR4_FSP_ACK is shown in Figure 5-181 and described in Table 5-378.

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This register is used by the DDR Controller to acknowledge the LPDDR4 frequency set point shange request.

Table 5-377 CTRLMMR_CHNG_DDR4_FSP_ACK Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 4004h	4301 6004h

Figure 5-181 CTRLMMR_CHNG_DDR4_FSP_ACK Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
ACK	RESERVED						ERROR
R-X	R-0h						R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-378 CTRLMMR_CHNG_DDR4_FSP_ACK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	ACK	R	X	Frequency change acknowledge. This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 Indication from the DDR Controller that the FSP change operation is complete 0h - FSP change operation in progress 1h - FSP change operation complete
6-1	RESERVED	R	0h	Reserved
0	ERROR	R	X	Frequency change error This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1 0h - FSP change was sucessful 1h - FSP change was not sucessful

1.1.5.166 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register (Proxy0 Offset = 14080h; Proxy1 Offset = 16080h) [reset = X]

CTRLMMR_DDR4_FSP_CLKCHNG_REQ is shown in Figure 5-182 and described in Table 5-380.

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This register is used by the DDR Controller to request the DDR PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request.

Table 5-379 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 4080h	4301 6080h

Figure 5-182 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
REQ	RESERVED					REQ_TYPE
R-X	R-0h					R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-380 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7	REQ	R	X	DDR Controller FSP clock change request Indicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set.
6-2	RESERVED	R	0h	Reserved
1-0	REQ_TYPE	R	X	Frequency request type Indicates which DDR4 FSP frequency to which the DDR Controller wants the DDR clock set

1.1.5.167 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register (Proxy0 Offset = 140C0h; Proxy1 Offset = 160C0h) [reset = 0h]

CTRLMMR_DDR4_FSP_CLKCHNG_ACK is shown in Figure 5-183 and described in Table 5-382.

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This register is used to acknowledge a DDR PLL clock frequency change to the DDR Controller.

Table 5-381 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 40C0h	4301 60C0h

Figure 5-183 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							ACK
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-382 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	ACK	R/W	0h	DDR FSP clock change ackowledge This bit should be set once the DDR clock has been sucessfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit and the associated change request interrupt.

1.1.5.168 CTRLMMR_LOCK5_KICK0 Register (Proxy0 Offset = 15008h; Proxy1 Offset = 17008h) [reset = 0h]

CTRLMMR_LOCK5_KICK0 is shown in Figure 5-184 and described in Table 5-384.

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Lower 32-bits of Partition5 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK5_KICK1 with its key value before write-protected Partition 5 registers can be written.

Table 5-383 CTRLMMR_LOCK5_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 5008h	4301 7008h

Figure 5-184 CTRLMMR_LOCK5_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-384 CTRLMMR_LOCK5_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.169 CTRLMMR_LOCK5_KICK1 Register (Proxy0 Offset = 1500Ch; Proxy1 Offset = 1700Ch) [reset = 0h]

CTRLMMR_LOCK5_KICK1 is shown in Figure 5-185 and described in Table 5-386.

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Upper 32-bits of Partition 5 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK5_KICK0 with its key value before write-protected Partition 5 registers can be written.

Table 5-385 CTRLMMR_LOCK5_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 500Ch	4301 700Ch

Figure 5-185 CTRLMMR_LOCK5_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-386 CTRLMMR_LOCK5_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers

1.1.5.170 CTRLMMR_P5_CLAIM0 Register (Proxy0 Offset = 15100h; Proxy1 Offset = 17100h) [reset = 0h]

CTRLMMR_P5_CLAIM0 is shown in Figure 5-186 and described in Table 5-388.

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Claim bits for Partition5 Registers.

Table 5-387 CTRLMMR_P5_CLAIM0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 5100h	4301 7100h

Figure 5-186 CTRLMMR_P5_CLAIM0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-388 CTRLMMR_P5_CLAIM0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x14000 + (0 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x16000 + (0 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.171 CTRLMMR_P5_CLAIM1 Register (Proxy0 Offset = 15104h; Proxy1 Offset = 17104h) [reset = 0h]

CTRLMMR_P5_CLAIM1 is shown in Figure 5-187 and described in Table 5-390.

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Claim bits for Partition5 Registers.

Table 5-389 CTRLMMR_P5_CLAIM1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 5104h	4301 7104h

Figure 5-187 CTRLMMR_P5_CLAIM1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-390 CTRLMMR_P5_CLAIM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x14000 + (1 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x16000 + (1 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

1.1.5.172 CTRLMMR_RST_CTRL Register (Proxy0 Offset = 18170h; Proxy1 Offset = 1A170h) [reset = 200FFh]

CTRLMMR_RST_CTRL is shown in Figure 5-188 and described in Table 5-392.

Return to Summary Table.

Controls Reset Assertion and Propogation.

Table 5-391 CTRLMMR_RST_CTRL Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 8170h	4301 A170h

Figure 5-188 CTRLMMR_RST_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED					MAIN_RESET_ISO_DONE_Z	MAIN_ESM_ERROR_RST_EN_Z	DMSC_COLD_RESET_EN_Z
R-0h					R/W-0h	R/W-1h	R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
SW_MAIN_POR				SW_MAIN_WARMRST
R/W-Fh				R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-392 CTRLMMR_RST_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	0h	Reserved
18	MAIN_RESET_ISO_DONE_Z	R/W	0h	MAIN domain CPUs can set this bit to block warm reset in the main domain which is useful when the MAIN domain may be accessing main domain resources (peripherals, memory..). In this case, the main domain cpus will be notified via an interrupt that there is an outstanding warm reset request for the main domain. Once notified, Main needs to finish any outstanding operations in has with main domain resources and then clear this bit. After this bit is cleared, the main domain warm reset will unblocked and the warm reset sequence may continue. 0h - Reset of MAIN domain is not Blocked by MAIN domain 1h - Reset of MAIN domain is Blocked by MAIN domain
17	MAIN_ESM_ERROR_RST_EN_Z	R/W	1h	Disable Reset of Main by ESM 0h - Enabled 1h - Disabled
16	DMSC_COLD_RESET_EN_Z	R/W	0h	Disable Reset of Main by DMSC 0h - Enabled 1h - Disabled
15-8	RESERVED	R	0h	Reserved
7-4	SW_MAIN_POR	R/W	Fh	Causes MAIN domain Power On Reset when set to 4'b0110, Bits will reset to 4'b1111
3-0	SW_MAIN_WARMRST	R/W	Fh	Causes MAIN domain Warm Reset when set to 4'b0110, Bits will reset to 4'b1111

1.1.5.173 CTRLMMR_RST_STAT Register (Proxy0 Offset = 18174h; Proxy1 Offset = 1A174h) [reset = X]

CTRLMMR_RST_STAT is shown in Figure 5-189 and described in Table 5-394.

Return to Summary Table.

Reset Status.

Table 5-393 CTRLMMR_RST_STAT Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 8174h	4301 A174h

Figure 5-189 CTRLMMR_RST_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							MCU_RESET_ISO_DONE_Z
R-0h							R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-394 CTRLMMR_RST_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	MCU_RESET_ISO_DONE_Z	R	X	is an outstanding warm reset request for the main domain. Once notified, MCU needs to finish any outstanding

1.1.5.174 CTRLMMR_RST_SRC Register (Proxy0 Offset = 18178h; Proxy1 Offset = 1A178h) [reset = X]

CTRLMMR_RST_SRC is shown in Figure 5-190 and described in Table 5-396.

Return to Summary Table.

Captures Reason for Warm and MAIN domain Power On Resets Read Only Mirror of MCU CTRL MMR version.

Table 5-395 CTRLMMR_RST_SRC Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 8178h	4301 A178h

Figure 5-190 CTRLMMR_RST_SRC Register

31	30	29	28	27	26	25	24
SAFETY_ERROR	MAIN_ESM_ERROR	RESERVED				SW_MAIN_POR_FROM_MAIN	SW_MAIN_POR_FROM_MCU
R-X	R-X	R-0h				R-X	R-X

23	22	21	20	19	18	17	16
RESERVED		SW_MAIN_WARMRST_FROM_MAIN	SW_MAIN_WARMRST_FROM_MCU	RESERVED			SW_MCU_WARMRST
R-0h		R-X	R-X	R-0h			R-X

15	14	13	12	11	10	9	8
RESERVED		WARM_OUT_RST	COLD_OUT_RST	RESERVED			DEBUG_RST
R-0h		R-X	R-X	R-0h			R-X

7	6	5	4	3	2	1	0
RESERVED			THERMAL_RST	RESERVED	MAIN_RESET_REQ	RESERVED	MCU_RESET_PIN
R-0h			R-X	R-0h	R-X	R-0h	R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-396 CTRLMMR_RST_SRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SAFETY_ERROR	R	X	Reset Caused by MCU ESM Error
30	MAIN_ESM_ERROR	R	X	Reset Caused by Main ESM Error
29-26	RESERVED	R	0h	Reserved
25	SW_MAIN_POR_FROM_MAIN	R	X	Software Main Power On Reset From MAIN CTRL MMR
24	SW_MAIN_POR_FROM_MCU	R	X	Software Main Power On Reset From MCU CTRL MMR
23-22	RESERVED	R	0h	Reserved
21	SW_MAIN_WARMRST_FROM_MAIN	R	X	Software Main Warm Reset from MAIN CTRL MMR
20	SW_MAIN_WARMRST_FROM_MCU	R	X	Software Main Warm Reset From MCU CTRL MMR
19-17	RESERVED	R	0h	Reserved
16	SW_MCU_WARMRST	R	X	Software Warm Reset
15-14	RESERVED	R	0h	Reserved
13	WARM_OUT_RST	R	X	DMSC Warm Reset
12	COLD_OUT_RST	R	X	DMSC Cold Reset
11-9	RESERVED	R	0h	Reserved
8	DEBUG_RST	R	X	Debug Subsystem Initiated Reset
7-5	RESERVED	R	0h	Reserved
4	THERMAL_RST	R	X	Thermal Reset
3	RESERVED	R	0h	Reserved
2	MAIN_RESET_REQ	R	X	MAIN Domain Reset Pin Initiated Reset
1	RESERVED	R	0h	Reserved
0	MCU_RESET_PIN	R	X	MCU Domain Reset Pin Initiated Reset

1.1.5.175 CTRLMMR_RST_MAGIC_WORD Register (Proxy0 Offset = 1817Ch; Proxy1 Offset = 1A17Ch) [reset = X]

CTRLMMR_RST_MAGIC_WORD is shown in Figure 5-191 and described in Table 5-398.

Return to Summary Table.

Read Only Mirror of MCU CTRL MMR version. After an MCU_PORz reset this bit field resets to 0x00000000. While this bit field remains 0x00000000 any warm reset from the MAIN domain also propagates through the MCU domain. If the application does not require reset isolation of the MCU domain, it may leave this bit field with a value of 0x00000000. If the application does require reset isolation of the MCU domain after the initial boot, then the M4FSS CPU must write a nonzero value to the magic word. The actual value is left to software and different values may be used to convey information, but in order to isolate the MCU domain from all MAIN domain warm reset sources that trigger main_resetz, the value must be non-zero. If the value is nonzero and one of the MAIN domain warm reset sources triggers main_resetz occurs in the main domain, the M4FSS will not be reset. The MAIN domain bootloader must read this value to determine that the M4FSS is already initialized, and has configured reset isolation. The MAIN domain bootloader then also skips any initialization steps involving bootstrapping the M4FSS as it is is already running. Note that MCU_PORz reset is never blocked by a nonzero magic word.

Table 5-397 CTRLMMR_RST_MAGIC_WORD Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 817Ch	4301 A17Ch

Figure 5-191 CTRLMMR_RST_MAGIC_WORD Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MCU_MAGIC_WORD
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-398 CTRLMMR_RST_MAGIC_WORD Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MCU_MAGIC_WORD	R	X	Magic Word Indicating Status of MCU Subsystem Boot

1.1.5.176 CTRLMMR_LOCK6_KICK0 Register (Proxy0 Offset = 19008h; Proxy1 Offset = 1B008h) [reset = 0h]

CTRLMMR_LOCK6_KICK0 is shown in Figure 5-192 and described in Table 5-400.

Return to Summary Table.

Lower 32-bits of Partition6 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK6_KICK1 with its key value before write-protected Partition 6 registers can be written.

Table 5-399 CTRLMMR_LOCK6_KICK0 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 9008h	4301 B008h

Figure 5-192 CTRLMMR_LOCK6_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-400 CTRLMMR_LOCK6_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition6 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.1.5.177 CTRLMMR_LOCK6_KICK1 Register (Proxy0 Offset = 1900Ch; Proxy1 Offset = 1B00Ch) [reset = 0h]

CTRLMMR_LOCK6_KICK1 is shown in Figure 5-193 and described in Table 5-402.

Return to Summary Table.

Upper 32-bits of Partition 6 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK6_KICK0 with its key value before write-protected Partition 6 registers can be written.

Table 5-401 CTRLMMR_LOCK6_KICK1 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 900Ch	4301 B00Ch

Figure 5-193 CTRLMMR_LOCK6_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-402 CTRLMMR_LOCK6_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition6 registers

1.1.5.178 CTRLMMR_P6_CLAIM2 Register (Proxy0 Offset = 19108h; Proxy1 Offset = 1B108h) [reset = 0h]

CTRLMMR_P6_CLAIM2 is shown in Figure 5-194 and described in Table 5-404.

Return to Summary Table.

Claim bits for Partition6 Registers.

Table 5-403 CTRLMMR_P6_CLAIM2 Instances

Instance	Proxy0 Physical Address	Proxy1 Physical Address
CTRL_MMR0	4301 9108h	4301 B108h

Figure 5-194 CTRLMMR_P6_CLAIM2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PROXY1_CLAIMED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-404 CTRLMMR_P6_CLAIM2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PROXY1_CLAIMED	R/W	0h	Proxy1 register claim bit Bit position b corresponds to register Proxy0 address of: 0x18000 + (2 x 0x80) + (b x 0x4) and register Proxy1 address of: 0x1A000 + (2 x 0x80) + (b x 0x4) Write 1 through Proxy1 address to claim the associated register. This will disable all write accesses through the Proxy0 address of the register. Write 0 through Proxy1 address to release the claim and allow Proxy0 writes of the associated register.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

5.1.1.5 CTRL_MMR0 Registers

1.1.5.1 CTRLMMR_PID Register (Proxy0 Offset = 0h; Proxy1 Offset = 2000h) [reset = 61800000h]

1.1.5.2 CTRLMMR_MMR_CFG1 Register (Proxy0 Offset = 8h; Proxy1 Offset = 2008h) [reset = 800000BFh]

1.1.5.3 CTRLMMR_JTAGID Register (Proxy0 Offset = 14h; Proxy1 Offset = 2014h) [reset = BB3802Fh]

1.1.5.4 CTRLMMR_JTAG_USER_ID Register (Proxy0 Offset = 18h; Proxy1 Offset = 2018h) [reset = BB3802Fh]

1.1.5.5 CTRLMMR_MAIN_DEVSTAT Register (Proxy0 Offset = 30h; Proxy1 Offset = 2030h) [reset = X]

1.1.5.6 CTRLMMR_MAIN_BOOTCFG Register (Proxy0 Offset = 34h; Proxy1 Offset = 2034h) [reset = X]

1.1.5.7 CTRLMMR_DEVICE_FEATURE0 Register (Proxy0 Offset = 60h; Proxy1 Offset = 2060h) [reset = X]

1.1.5.8 CTRLMMR_DEVICE_FEATURE2 Register (Proxy0 Offset = 68h; Proxy1 Offset = 2068h) [reset = X]

1.1.5.9 CTRLMMR_DEVICE_FEATURE6 Register (Proxy0 Offset = 78h; Proxy1 Offset = 2078h) [reset = X]

1.1.5.10 CTRLMMR_MAC_ID0 Register (Proxy0 Offset = 200h; Proxy1 Offset = 2200h) [reset = X]

1.1.5.11 CTRLMMR_MAC_ID1 Register (Proxy0 Offset = 204h; Proxy1 Offset = 2204h) [reset = X]

1.1.5.12 CTRLMMR_PCI_DEVICE_ID0 Register (Proxy0 Offset = 210h; Proxy1 Offset = 2210h) [reset = B010104Ch]

1.1.5.13 CTRLMMR_PCI_DEVICE_ID1 Register (Proxy0 Offset = 214h; Proxy1 Offset = 2214h) [reset = B010104Ch]

1.1.5.14 CTRLMMR_USB_DEVICE_ID0 Register (Proxy0 Offset = 220h; Proxy1 Offset = 2220h) [reset = 61650451h]

1.1.5.15 CTRLMMR_USB_DEVICE_ID1 Register (Proxy0 Offset = 224h; Proxy1 Offset = 2224h) [reset = 61650451h]

1.1.5.16 CTRLMMR_GP_SW0 Register (Proxy0 Offset = 230h; Proxy1 Offset = 2230h) [reset = X]

1.1.5.17 CTRLMMR_GP_SW1 Register (Proxy0 Offset = 234h; Proxy1 Offset = 2234h) [reset = X]

1.1.5.18 CTRLMMR_GP_SW2 Register (Proxy0 Offset = 238h; Proxy1 Offset = 2238h) [reset = X]

1.1.5.19 CTRLMMR_GP_SW3 Register (Proxy0 Offset = 23Ch; Proxy1 Offset = 223Ch) [reset = X]

1.1.5.20 CTRLMMR_CBA_ERR_STAT Register (Proxy0 Offset = 270h; Proxy1 Offset = 2270h) [reset = X]

1.1.5.21 CTRLMMR_LOCK0_KICK0 Register (Proxy0 Offset = 1008h; Proxy1 Offset = 3008h) [reset = 0h]

1.1.5.22 CTRLMMR_LOCK0_KICK1 Register (Proxy0 Offset = 100Ch; Proxy1 Offset = 300Ch) [reset = 0h]

1.1.5.23 CTRLMMR_INTR_RAW_STAT Register (Proxy0 Offset = 1010h; Proxy1 Offset = 3010h) [reset = 0h]

1.1.5.24 CTRLMMR_INTR_STAT_CLR Register (Proxy0 Offset = 1014h; Proxy1 Offset = 3014h) [reset = 0h]

1.1.5.25 CTRLMMR_INTR_EN_SET Register (Proxy0 Offset = 1018h; Proxy1 Offset = 3018h) [reset = 0h]

1.1.5.26 CTRLMMR_INTR_EN_CLR Register (Proxy0 Offset = 101Ch; Proxy1 Offset = 301Ch) [reset = 0h]

1.1.5.27 CTRLMMR_EOI Register (Proxy0 Offset = 1020h; Proxy1 Offset = 3020h) [reset = 0h]

1.1.5.28 CTRLMMR_FAULT_ADDR Register (Proxy0 Offset = 1024h; Proxy1 Offset = 3024h) [reset = 0h]

1.1.5.29 CTRLMMR_FAULT_TYPE Register (Proxy0 Offset = 1028h; Proxy1 Offset = 3028h) [reset = 0h]

1.1.5.30 CTRLMMR_FAULT_ATTR Register (Proxy0 Offset = 102Ch; Proxy1 Offset = 302Ch) [reset = 0h]

1.1.5.31 CTRLMMR_FAULT_CLR Register (Proxy0 Offset = 1030h; Proxy1 Offset = 3030h) [reset = 0h]

1.1.5.32 CTRLMMR_P0_CLAIM0 Register (Proxy0 Offset = 1100h; Proxy1 Offset = 3100h) [reset = 0h]

1.1.5.33 CTRLMMR_P0_CLAIM4 Register (Proxy0 Offset = 1110h; Proxy1 Offset = 3110h) [reset = 0h]

1.1.5.34 CTRLMMR_USB0_PHY_CTRL Register (Proxy0 Offset = 4008h; Proxy1 Offset = 6008h) [reset = 80000004h]

1.1.5.35 CTRLMMR_ENET1_CTRL Register (Proxy0 Offset = 4044h; Proxy1 Offset = 6044h) [reset = 2h]

1.1.5.36 CTRLMMR_ENET2_CTRL Register (Proxy0 Offset = 4048h; Proxy1 Offset = 6048h) [reset = 2h]

1.1.5.37 CTRLMMR_PCIE0_CTRL Register (Proxy0 Offset = 4070h; Proxy1 Offset = 6070h) [reset = 1h]

1.1.5.38 CTRLMMR_SERDES0_LN0_CTRL Register (Proxy0 Offset = 4080h; Proxy1 Offset = 6080h) [reset = 0h]

1.1.5.39 CTRLMMR_ADC0_TRIM Register (Proxy0 Offset = 40C0h; Proxy1 Offset = 60C0h) [reset = X]

1.1.5.40 CTRLMMR_SERDES0_CTRL Register (Proxy0 Offset = 40E0h; Proxy1 Offset = 60E0h) [reset = 0h]

1.1.5.41 CTRLMMR_ICSSG0_CTRL0 Register (Proxy0 Offset = 4100h; Proxy1 Offset = 6100h) [reset = 0h]

1.1.5.42 CTRLMMR_ICSSG0_CTRL1 Register (Proxy0 Offset = 4104h; Proxy1 Offset = 6104h) [reset = 0h]

1.1.5.43 CTRLMMR_ICSSG1_CTRL0 Register (Proxy0 Offset = 4110h; Proxy1 Offset = 6110h) [reset = 0h]

1.1.5.44 CTRLMMR_ICSSG1_CTRL1 Register (Proxy0 Offset = 4114h; Proxy1 Offset = 6114h) [reset = 0h]

1.1.5.45 CTRLMMR_EPWM_TB_CLKEN Register (Proxy0 Offset = 4130h; Proxy1 Offset = 6130h) [reset = 0h]

1.1.5.46 CTRLMMR_EPWM_TB_CLKEN_SET Register (Proxy0 Offset = 4134h; Proxy1 Offset = 6134h) [reset = 0h]

1.1.5.47 CTRLMMR_EPWM_TB_CLKEN_CLR Register (Proxy0 Offset = 4138h; Proxy1 Offset = 6138h) [reset = 0h]

1.1.5.48 CTRLMMR_EPWM0_CTRL Register (Proxy0 Offset = 4140h; Proxy1 Offset = 6140h) [reset = 0h]

1.1.5.49 CTRLMMR_EPWM1_CTRL Register (Proxy0 Offset = 4144h; Proxy1 Offset = 6144h) [reset = 0h]

1.1.5.50 CTRLMMR_EPWM2_CTRL Register (Proxy0 Offset = 4148h; Proxy1 Offset = 6148h) [reset = 0h]

1.1.5.51 CTRLMMR_EPWM3_CTRL Register (Proxy0 Offset = 414Ch; Proxy1 Offset = 614Ch) [reset = 0h]

1.1.5.52 CTRLMMR_EPWM4_CTRL Register (Proxy0 Offset = 4150h; Proxy1 Offset = 6150h) [reset = 0h]

1.1.5.53 CTRLMMR_EPWM5_CTRL Register (Proxy0 Offset = 4154h; Proxy1 Offset = 6154h) [reset = 0h]

1.1.5.54 CTRLMMR_EPWM6_CTRL Register (Proxy0 Offset = 4158h; Proxy1 Offset = 6158h) [reset = 0h]

1.1.5.55 CTRLMMR_EPWM7_CTRL Register (Proxy0 Offset = 415Ch; Proxy1 Offset = 615Ch) [reset = 0h]

1.1.5.56 CTRLMMR_EPWM8_CTRL Register (Proxy0 Offset = 4160h; Proxy1 Offset = 6160h) [reset = 0h]

1.1.5.57 CTRLMMR_SOCA_SEL Register (Proxy0 Offset = 4170h; Proxy1 Offset = 6170h) [reset = 0h]

1.1.5.58 CTRLMMR_SOCB_SEL Register (Proxy0 Offset = 4174h; Proxy1 Offset = 6174h) [reset = 0h]

1.1.5.59 CTRLMMR_EQEP0_CTRL Register (Proxy0 Offset = 4180h; Proxy1 Offset = 6180h) [reset = 0h]

1.1.5.60 CTRLMMR_EQEP1_CTRL Register (Proxy0 Offset = 4184h; Proxy1 Offset = 6184h) [reset = 0h]

1.1.5.61 CTRLMMR_EQEP2_CTRL Register (Proxy0 Offset = 4188h; Proxy1 Offset = 6188h) [reset = 0h]

1.1.5.62 CTRLMMR_EQEP_STAT Register (Proxy0 Offset = 41A0h; Proxy1 Offset = 61A0h) [reset = X]

1.1.5.63 CTRLMMR_SDIO1_CTRL Register (Proxy0 Offset = 41B4h; Proxy1 Offset = 61B4h) [reset = X]

1.1.5.64 CTRLMMR_TIMER1_CTRL Register (Proxy0 Offset = 4204h; Proxy1 Offset = 6204h) [reset = 0h]

1.1.5.65 CTRLMMR_TIMER3_CTRL Register (Proxy0 Offset = 420Ch; Proxy1 Offset = 620Ch) [reset = 0h]

1.1.5.66 CTRLMMR_TIMER5_CTRL Register (Proxy0 Offset = 4214h; Proxy1 Offset = 6214h) [reset = 0h]

1.1.5.67 CTRLMMR_TIMER7_CTRL Register (Proxy0 Offset = 421Ch; Proxy1 Offset = 621Ch) [reset = 0h]

1.1.5.68 CTRLMMR_TIMER9_CTRL Register (Proxy0 Offset = 4224h; Proxy1 Offset = 6224h) [reset = 0h]

1.1.5.69 CTRLMMR_TIMER11_CTRL Register (Proxy0 Offset = 422Ch; Proxy1 Offset = 622Ch) [reset = 0h]

1.1.5.70 CTRLMMR_I2C0_CTRL Register (Proxy0 Offset = 42E0h; Proxy1 Offset = 62E0h) [reset = 0h]

1.1.5.71 CTRLMMR_FSS_CTRL Register (Proxy0 Offset = 4700h; Proxy1 Offset = 6700h) [reset = 0h]

1.1.5.72 CTRLMMR_ADC0_CTRL Register (Proxy0 Offset = 4710h; Proxy1 Offset = 6710h) [reset = 0h]

1.1.5.73 CTRLMMR_DCC_STAT Register (Proxy0 Offset = 4750h; Proxy1 Offset = 6750h) [reset = X]

1.1.5.74 CTRLMMR_LOCK1_KICK0 Register (Proxy0 Offset = 5008h; Proxy1 Offset = 7008h) [reset = 0h]

1.1.5.75 CTRLMMR_LOCK1_KICK1 Register (Proxy0 Offset = 500Ch; Proxy1 Offset = 700Ch) [reset = 0h]

1.1.5.76 CTRLMMR_P1_CLAIM0 Register (Proxy0 Offset = 5100h; Proxy1 Offset = 7100h) [reset = 0h]

1.1.5.77 CTRLMMR_P1_CLAIM1 Register (Proxy0 Offset = 5104h; Proxy1 Offset = 7104h) [reset = 0h]

1.1.5.78 CTRLMMR_P1_CLAIM2 Register (Proxy0 Offset = 5108h; Proxy1 Offset = 7108h) [reset = 0h]

1.1.5.79 CTRLMMR_P1_CLAIM3 Register (Proxy0 Offset = 510Ch; Proxy1 Offset = 710Ch) [reset = 0h]

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VAL
R-X