SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes OSPI Global Control registers, OSPI Configuration registers, and OSPI_ECC_AGGR registers.
Table 12-3080 lists the memory-mapped registers for the OSPI Global Control Registers. All register offset addresses not listed in Table 12-3080 should be considered as reserved locations and the register contents should not be modified.
The Global Control Registers region is accessed by setting the Region Select signal to 0 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
FSS0_OSPI0_SS_CFG | 0FC4 4000h |
OSPI_PID is shown in Figure 12-1543 and described in Table 12-3082.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
FSS0_OSPI0_SS_CFG | 0FC4 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-874h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-Fh | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | OSPI_PID register scheme |
29-28 | BU | R | 2h | Business Unit: 10 = Processors |
27-16 | MODULE_ID | R | 874h | Module ID |
15-11 | RTL | R | Fh | RTL revision. Will vary depending on release. |
10-8 | MAJOR | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |
OSPI_CTRL is shown in Figure 12-1544 and described in Table 12-3084.
Return to Summary Table.
The Control Register contains general control bits for the OSPI.
Instance | Physical Address |
---|---|
FSS0_OSPI0_SS_CFG | 0FC4 4004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PIPELINE_MODE_FLUSH | RESERVED | |||||
R-0h | R/W-0h | R-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | PIPELINE_MODE_FLUSH | R/W | 0h | 1h = Flush Flash Controller FIFO by forcing data interface slave select signal low. 0h = Data interface slave select signal to Controller is 1. |
2-0 | RESERVED | R | 0h | Reserved |
OSPI_STAT is shown in Figure 12-1545 and described in Table 12-3086.
Return to Summary Table.
The Status register provide general status bits for the OSPI.
Instance | Physical Address |
---|---|
FSS0_OSPI0_SS_CFG | 0FC4 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MEM_INIT_DONE | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | MEM_INIT_DONE | R | 0h | 0h = Memory initialization is in progress, 1h = Memory intialization is done. |
0 | RESERVED | R | 0h | Reserved |
OSPI_EOI is shown in Figure 12-1546 and described in Table 12-3088.
Return to Summary Table.
End of Interrupt Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.
Instance | Physical Address |
---|---|
FSS0_OSPI0_SS_CFG | 0FC4 4020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI | ||||||||||||||||||||||||||||||
R-0h | W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EOI | W | 0h | Write with bit position of targetted interrupt. (that is Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. |
Table 12-3090 lists the memory-mapped registers for the OSPI Module Configuration registers. All register offset addresses not listed in Table 12-3090 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0000h |
Offset | Acronym | Register Name | FSS0_OSPI0_CTRL Physical Address |
---|---|---|---|
0h | OSPI_CONFIG_REG | OSPI configuration register | 0FC4 0000h |
4h | OSPI_DEV_INSTR_RD_CONFIG_REG | Read instruction configuration register | 0FC4 0004h |
8h | OSPI_DEV_INSTR_WR_CONFIG_REG | Write instruction configuration register | 0FC4 0008h |
Ch | OSPI_DEV_DELAY_REG | OSPI delay register | 0FC4 000Ch |
10h | OSPI_RD_DATA_CAPTURE_REG | Read data capture register | 0FC4 0010h |
14h | OSPI_DEV_SIZE_CONFIG_REG | Device size configuration register | 0FC4 0014h |
18h | OSPI_SRAM_PARTITION_CFG_REG | SRAM partition configuration register | 0FC4 0018h |
1Ch | OSPI_IND_AHB_ADDR_TRIGGER_REG | Indirect trigger address register | 0FC4 001Ch |
20h | OSPI_DMA_PERIPH_CONFIG_REG | DMA configuration register | 0FC4 0020h |
24h | OSPI_REMAP_ADDR_REG | Address remapping register | 0FC4 0024h |
28h | OSPI_MODE_BIT_CONFIG_REG | Mode bit configuration register | 0FC4 0028h |
2Ch | OSPI_SRAM_FILL_REG | SRAM fill level register | 0FC4 002Ch |
30h | OSPI_TX_THRESH_REG | TX threshold register | 0FC4 0030h |
34h | OSPI_RX_THRESH_REG | RX threshold register | 0FC4 0034h |
38h | OSPI_WRITE_COMPLETION_CTRL_REG | Write completion control register | 0FC4 0038h |
3Ch | OSPI_NO_OF_POLLS_BEF_EXP_REG | Polling expiration register | 0FC4 003Ch |
40h | OSPI_IRQ_STATUS_REG | Interrupt status register | 0FC4 0040h |
44h | OSPI_IRQ_MASK_REG | Interrupt mask register | 0FC4 0044h |
50h | OSPI_LOWER_WR_PROT_REG | Lower write protection register | 0FC4 0050h |
54h | OSPI_UPPER_WR_PROT_REG | Upper write protection register | 0FC4 0054h |
58h | OSPI_WR_PROT_CTRL_REG | Write protection control register | 0FC4 0058h |
60h | OSPI_INDIRECT_READ_XFER_CTRL_REG | Indirect read transfer control register | 0FC4 0060h |
64h | OSPI_INDIRECT_READ_XFER_WATERMARK_REG | Indirect read transfer watermark register | 0FC4 0064h |
68h | OSPI_INDIRECT_READ_XFER_START_REG | Indirect read transfer start address register | 0FC4 0068h |
6Ch | OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG | Indirect read transfer number bytes register | 0FC4 006Ch |
70h | OSPI_INDIRECT_WRITE_XFER_CTRL_REG | Indirect write transfer control register | 0FC4 0070h |
74h | OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG | Indirect write transfer watermark register | 0FC4 0074h |
78h | OSPI_INDIRECT_WRITE_XFER_START_REG | Indirect write transfer start address register | 0FC4 0078h |
7Ch | OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG | Indirect write transfer number bytes register | 0FC4 007Ch |
80h | OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG | Indirect trigger address range register | 0FC4 0080h |
8Ch | OSPI_FLASH_COMMAND_CTRL_MEM_REG | Flash command control memory register | 0FC4 008Ch |
90h | OSPI_FLASH_CMD_CTRL_REG | Flash command control register | 0FC4 0090h |
94h | OSPI_FLASH_CMD_ADDR_REG | Flash command address register | 0FC4 0094h |
A0h | OSPI_FLASH_RD_DATA_LOWER_REG | Flash command read data register (lower) | 0FC4 00A0h |
A4h | OSPI_FLASH_RD_DATA_UPPER_REG | Flash command read data register (upper) | 0FC4 00A4h |
A8h | OSPI_FLASH_WR_DATA_LOWER_REG | Flash command write data register (lower) | 0FC4 00A8h |
ACh | OSPI_FLASH_WR_DATA_UPPER_REG | Flash command write data register (upper) | 0FC4 00ACh |
B0h | OSPI_POLLING_FLASH_STATUS_REG | Polling Flash status register | 0FC4 00B0h |
B4h | OSPI_PHY_CONFIGURATION_REG | PHY configuration register | 0FC4 00B4h |
B8h | OSPI_PHY_MASTER_CONTROL_REG | PHY DLL master control register | 0FC4 00B8h |
BCh | OSPI_DLL_OBSERVABLE_LOWER_REG | DLL observable register (lower) | 0FC4 00BCh |
C0h | OSPI_DLL_OBSERVABLE_UPPER_REG | DLL observable register (upper) | 0FC4 00C0h |
E0h | OSPI_OPCODE_EXT_LOWER_REG | Opcode extension register (lower) | 0FC4 00E0h |
E4h | OSPI_OPCODE_EXT_UPPER_REG | Opcode extension register (upper) | 0FC4 00E4h |
FCh | OSPI_MODULE_ID_REG | Module ID register | 0FC4 00FCh |
OSPI_CONFIG_REG is shown in Figure 12-1547 and described in Table 12-3092.
Return to Summary Table.
OSPI Configuration Register
This register contains basic configuration fields of the controller.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IDLE_FLD | DUAL_BYTE_OPCODE_EN_FLD | CRC_ENABLE_FLD | CONFIG_RESV2_FLD | PIPELINE_PHY_FLD | ENABLE_DTR_PROTOCOL_FLD | ||
R-1h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENABLE_AHB_DECODER_FLD | MSTR_BAUD_DIV_FLD | ENTER_XIP_MODE_IMM_FLD | ENTER_XIP_MODE_FLD | ENB_AHB_ADDR_REMAP_FLD | |||
R/W-0h | R/W-Fh | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENB_DMA_IF_FLD | WR_PROT_FLASH_FLD | PERIPH_CS_LINES_FLD | PERIPH_SEL_DEC_FLD | ENB_LEGACY_IP_MODE_FLD | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENB_DIR_ACC_CTLR_FLD | RESET_CFG_FLD | RESET_PIN_FLD | HOLD_PIN_FLD | PHY_MODE_ENABLE_FLD | SEL_CLK_PHASE_FLD | SEL_CLK_POL_FLD | ENB_SPI_FLD |
R/W-1h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description | |
---|---|---|---|---|---|
31 | IDLE_FLD | R | 1h | Serial interface and low level SPI pipeline is IDLE. | |
30 | DUAL_BYTE_OPCODE_EN_FLD | R/W | 0h | Dual-byte Opcode Mode enable bit. | |
29 | CRC_ENABLE_FLD | R/W | 0h | CRC enable bit. | |
28-26 | CONFIG_RESV2_FLD | R | 0h | Reserved | |
25 | PIPELINE_PHY_FLD | R/W | 0h | Pipeline PHY Mode enable. | |
24 | ENABLE_DTR_PROTOCOL_FLD | R/W | 0h | Enable DTR Protocol. | |
23 | ENABLE_AHB_DECODER_FLD | R/W | 0h | Enable AHB Decoder. 0h = Active slave is selected based on the OSPI_CONFIG_REG[13:10] PERIPH_CS_LINES_FLD. 1h = Active slave is selected based on actual data interface address (the partition is calculated with respect to bits OSPI_DEV_SIZE_CONFIG_REG[28:21]). | |
22-19 | MSTR_BAUD_DIV_FLD | R/W | Fh | Master mode baud rate divisor (2 to 32), | |
18 | ENTER_XIP_MODE_IMM_FLD | R/W | 0h | Enter XIP Mode immediately. 0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction Value= 1h = Operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode [as per the contents of its non-volatile configuration register]. The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited. | |
17 | ENTER_XIP_MODE_FLD | R/W | 0h | Enter XIP Mode on next READ. 0h = If XIP is enabled, then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. 1h = If XIP is disabled, then setting to 1 will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited | |
16 | ENB_AHB_ADDR_REMAP_FLD | R/W | 0h | Enable Data Interface Address Remapping [Direct Access Mode Only] | |
15 | ENB_DMA_IF_FLD | R/W | 0h | Enable DMA Peripheral Interface. CAUTION: This bit should be left at 0 as feature is not supported. | |
14 | WR_PROT_FLASH_FLD | R/W | 0h | Write Protect Flash Pin. | |
13-10 | PERIPH_CS_LINES_FLD | R/W | 0h | Peripheral Chip Select Lines. If OSPI_CONFIG_REG[9] PERIPH_SEL_DEC_FLD = 0, ss[3:0] are output thus: | |
ss[3-0] xxx0 xx01 x011 0111 1111 | N_SS_OUT[3:0] 1110 1101 1011 0111 1111 [no peripheral selected] | ||||
else ss[3-0] directly drives N_SS_OUT[3-0] | |||||
9 | PERIPH_SEL_DEC_FLD | R/W | 0h | Peripheral select decode. 0h = only 1 of 4 selects N_SS_OUT[3:0] is active, 1h = allow external 4-to-16 decode [N_SS_OUT = ss] | |
8 | ENB_LEGACY_IP_MODE_FLD | R/W | 0h | Legacy IP Mode Enable. 0h = Use Direct Access Controller/Indirect Access Controller 1h = Legacy Mode is enabled. In this mode, any write to the controller via the data interface is serialized and sent to the FLASH device. Any valid data read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, 4, 2 or 1 byte transfers are permitted and controlled. | |
7 | ENB_DIR_ACC_CTLR_FLD | R/W | 1h | Enable Direct Access Controller. 0h = Disable the Direct Access Controller once current transfer of the data word is complete. 1h = Enable the Direct Access Controller. When the Direct Access Controller and Indirect Access Controller are both disabled, all data requests are completed with an error response. | |
6 | RESET_CFG_FLD | R/W | 0h | RESET pin configuration. 0h = RESET feature on DQ3 pin of the device 1h = RESET feature on dedicated pin of the device [controlling of 5th bit influences on reset_out output]. | |
5 | RESET_PIN_FLD | R/W | 0h | Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature. | |
4 | HOLD_PIN_FLD | R/W | 0h | Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature. | |
3 | PHY_MODE_ENABLE_FLD | R/W | 0h | PHY mode enable. | |
2 | SEL_CLK_PHASE_FLD | R/W | 0h | Select Clock Phase. Selects whether the clock is in an active or inactive phase outside the SPI word 0h = The SPI clock is active outside the word 1h = The SPI clock is inactive outside the word | |
1 | SEL_CLK_POL_FLD | R/W | 0h | Clock polarity outside SPI word. 0h = The SPI clock is quiescent low 1h = The SPI clock is quiescent high | |
0 | ENB_SPI_FLD | R/W | 1h | OSPI Enable. 0h = Disable the OSPI, once current transfer of the data word is complete. 1h = Enable the OSPI, when this bit is set to 0, all output enables are inactive and all pins are set to input mode. |
OSPI_DEV_INSTR_RD_CONFIG_REG is shown in Figure 12-1548 and described in Table 12-3094.
Return to Summary Table.
Device Read Instruction Configuration Register.
This register defines the configuration of Multiple-SPI READ instruction. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RD_INSTR_RESV5_FLD | DUMMY_RD_CLK_CYCLES_FLD | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_INSTR_RESV4_FLD | MODE_BIT_ENABLE_FLD | RD_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | RD_INSTR_RESV1_FLD | DDR_EN_FLD | INSTR_TYPE_FLD | |||
R-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_OPCODE_NON_XIP_FLD | |||||||
R/W-3h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RD_INSTR_RESV5_FLD | R | 0h | Reserved |
28-24 | DUMMY_RD_CLK_CYCLES_FLD | R/W | 0h | Dummy Read Clock Cycles. |
23-21 | RD_INSTR_RESV4_FLD | R | 0h | Reserved |
20 | MODE_BIT_ENABLE_FLD | R/W | 0h | Mode Bit Enable. |
19-18 | RD_INSTR_RESV3_FLD | R | 0h | Reserved |
17-16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes. 0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Octal Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs |
15-14 | RD_INSTR_RESV2_FLD | R | 0h | Reserved |
13-12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes. 0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2, and DQ3 3h = Addresses can be shifted to the device on DQ[7:0] |
11 | RD_INSTR_RESV1_FLD | R | 0h | Reserved |
10 | DDR_EN_FLD | R/W | 0h | DDR Enable. |
9-8 | INSTR_TYPE_FLD | R/W | 0h | Instruction Type. 0h = Use Standard SPI mode [instruction always shifted into the device on DQ0 only] 1h = Use DIO-SPI mode [Instructions, Address and Data always sent on DQ0 and DQ1] 2h = Use QIO-SPI mode [Instructions, Address and Data always sent on DQ0, DQ1, DQ2, and DQ3] 3h = Use Octal-IO-SPI mode [Instructions, Address and Data always sent on DQ[7:0]] |
7-0 | RD_OPCODE_NON_XIP_FLD | R/W | 3h | Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode |
OSPI_DEV_INSTR_WR_CONFIG_REG is shown in Figure 12-1549 and described in Table 12-3096.
Return to Summary Table.
Device Write Instruction Configuration Register.
This register defines the configuration of Multiple-SPI WRITE (Program Page) instruction. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WR_INSTR_RESV4_FLD | DUMMY_WR_CLK_CYCLES_FLD | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WR_INSTR_RESV3_FLD | DATA_XFER_TYPE_EXT_MODE_FLD | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WR_INSTR_RESV2_FLD | ADDR_XFER_TYPE_STD_MODE_FLD | WR_INSTR_RESV1_FLD | WEL_DIS_FLD | ||||
R-0h | R/W-0h | R-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WR_OPCODE_FLD | |||||||
R/W-2h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | WR_INSTR_RESV4_FLD | R | 0h | Reserved |
28-24 | DUMMY_WR_CLK_CYCLES_FLD | R/W | 0h | Dummy Write Clock Cycles. |
23-18 | WR_INSTR_RESV3_FLD | R | 0h | Reserved |
17-16 | DATA_XFER_TYPE_EXT_MODE_FLD | R/W | 0h | Data Transfer Type for Standard SPI modes. 0h = SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1h = Used for Dual Input/Output instructions For data transfers, DQ0 and DQ1 are used as both inputs and outputs 2h = Used for Quad Input/Output instructions For data transfers, DQ0, DQ1, DQ2, and DQ3 are used as both inputs and outputs 3h = Used for Octal Input/Output instructions For data transfers, DQ[7:0] are used as both inputs and outputs |
15-14 | WR_INSTR_RESV2_FLD | R | 0h | Reserved |
13-12 | ADDR_XFER_TYPE_STD_MODE_FLD | R/W | 0h | Address Transfer Type for Standard SPI modes. 0h = Addresses can be shifted to the device on DQ0 only 1h = Addresses can be shifted to the device on DQ0 and DQ1 only 2h = Addresses can be shifted to the device on DQ0, DQ1, DQ2. and DQ3 3h = Addresses can be shifted to the device on DQ[7:0] |
11-9 | WR_INSTR_RESV1_FLD | R | 0h | Reserved |
8 | WEL_DIS_FLD | R/W | 0h | WEL Disable. |
7-0 | WR_OPCODE_FLD | R/W | 2h | Write Opcode |
OSPI_DEV_DELAY_REG is shown in Figure 12-1550 and described in Table 12-3098.
Return to Summary Table.
OSPI Device Delay Register. This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the OSPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.
This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
D_NSS_FLD | D_BTWN_FLD | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D_AFTER_FLD | D_INIT_FLD | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | D_NSS_FLD | R/W | 0h | Clock Delay for Chip Select Deassert. |
23-16 | D_BTWN_FLD | R/W | 0h | Clock Delay for Chip Select Deactivation. |
15-8 | D_AFTER_FLD | R/W | 0h | Clock Delay for Last Transaction Bit. |
7-0 | D_INIT_FLD | R/W | 0h | Clock Delay with N_SS_OUT. |
OSPI_RD_DATA_CAPTURE_REG is shown in Figure 12-1551 and described in Table 12-3100.
Return to Summary Table.
Read Data Capture Register.
This register is used to adjust SPI transfer conditions in order to fetch and capture data reliably. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RD_DATA_RESV3_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_DATA_RESV3_FLD | DDR_READ_DELAY_FLD | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_DATA_RESV2_FLD | DQS_ENABLE_FLD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RD_DATA_RESV1_FLD | SAMPLE_EDGE_SEL_FLD | DELAY_FLD | BYPASS_FLD | ||||
R-0h | R/W-0h | R/W-0h | R/W-1h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RD_DATA_RESV3_FLD | R | 0h | Reserved |
19-16 | DDR_READ_DELAY_FLD | R/W | 0h | DDR read delay. |
15-9 | RD_DATA_RESV2_FLD | R | 0h | Reserved |
8 | DQS_ENABLE_FLD | R/W | 0h | DQS enable bit. |
7-6 | RD_DATA_RESV1_FLD | R | 0h | Reserved |
5 | SAMPLE_EDGE_SEL_FLD | R/W | 0h | Sample edge selection. |
4-1 | DELAY_FLD | R/W | 0h | Read Delay. |
0 | BYPASS_FLD | R/W | 1h | Bypass. |
OSPI_DEV_SIZE_CONFIG_REG is shown in Figure 12-1552 and described in Table 12-3102.
Return to Summary Table.
Device Size Configuration Register.
This register allows to define the memory organization of using Flash Devices. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DEV_SIZE_RESV_FLD | MEM_SIZE_ON_CS3_FLD | MEM_SIZE_ON_CS2_FLD | MEM_SIZE_ON_CS1_FLD | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MEM_SIZE_ON_CS1_FLD | MEM_SIZE_ON_CS0_FLD | BYTES_PER_SUBSECTOR_FLD | |||||
R/W-0h | R/W-0h | R/W-10h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BYTES_PER_DEVICE_PAGE_FLD | |||||||
R/W-100h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BYTES_PER_DEVICE_PAGE_FLD | NUM_ADDR_BYTES_FLD | ||||||
R/W-100h | R/W-2h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | DEV_SIZE_RESV_FLD | R | 0h | Reserved |
28-27 | MEM_SIZE_ON_CS3_FLD | R/W | 0h | Size of Flash Device connected to CS[3] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb |
26-25 | MEM_SIZE_ON_CS2_FLD | R/W | 0h | Size of Flash Device connected to CS[2] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb |
24-23 | MEM_SIZE_ON_CS1_FLD | R/W | 0h | Size of Flash Device connected to CS[1] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb |
22-21 | MEM_SIZE_ON_CS0_FLD | R/W | 0h | Size of Flash Device connected to CS[0] pin: 0h = size of 512Mb 1h = size of 1Gb 2h = size of 2Gb 3h = size of 4Gb |
20-16 | BYTES_PER_SUBSECTOR_FLD | R/W | 10h | Number of bytes per Block. |
15-4 | BYTES_PER_DEVICE_PAGE_FLD | R/W | 100h | Number of bytes per device page. |
3-0 | NUM_ADDR_BYTES_FLD | R/W | 2h | Number of address bytes. |
OSPI_SRAM_PARTITION_CFG_REG is shown in Figure 12-1553 and described in Table 12-3104.
Return to Summary Table.
SRAM Partition Configuration Register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRAM_PARTITION_RESV_FLD | ADDR_FLD | ||||||||||||||||||||||||||||||
R-0h | R/W-80h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | SRAM_PARTITION_RESV_FLD | R | 0h | Reserved |
7-0 | ADDR_FLD | R/W | 80h | Indirect Read Partition Size. |
OSPI_IND_AHB_ADDR_TRIGGER_REG is shown in Figure 12-1554 and described in Table 12-3106.
Return to Summary Table.
Indirect AHB Address Trigger Register.
This register allowsto define the address distinguishing DAC access from triggered INDAC one. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_FLD | R/W | 0h | Indirect Trigger Address. |
OSPI_DMA_PERIPH_CONFIG_REG is shown in Figure 12-1555 and described in Table 12-3108.
Return to Summary Table.
DMA Peripheral Configuration Register.
This register allows to define the parameters of DMA peripheral controller. This register should be setup while the controller is idle.
Note: Reserved. This feature is not supported.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DMA_PERIPH_RESV2_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DMA_PERIPH_RESV2_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DMA_PERIPH_RESV2_FLD | NUM_BURST_REQ_BYTES_FLD | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMA_PERIPH_RESV1_FLD | NUM_SINGLE_REQ_BYTES_FLD | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | DMA_PERIPH_RESV2_FLD | R | 0h | Reserved |
11-8 | NUM_BURST_REQ_BYTES_FLD | R/W | 0h | Number of Burst Bytes. |
7-4 | DMA_PERIPH_RESV1_FLD | R | 0h | Reserved |
3-0 | NUM_SINGLE_REQ_BYTES_FLD | R/W | 0h | Number of Single Bytes. |
OSPI_REMAP_ADDR_REG is shown in Figure 12-1556 and described in Table 12-3110.
Return to Summary Table.
Remap Address Register.
This register allows to define the address offset for DAC accesses. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE_FLD | R/W | 0h | This register is used to remap an incoming data address to a different address used by the FLASH device. |
OSPI_MODE_BIT_CONFIG_REG is shown in Figure 12-1557 and described in Table 12-3112.
Return to Summary Table.
Mode Bit Configuration Register.
This register allows to define the mode bits for corresponding Flash Device. It also provides configuration for CRC aware SPI transfers. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RX_CRC_DATA_LOW_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_CRC_DATA_UP_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CRC_OUT_ENABLE_FLD | MODE_BIT_RESV1_FLD | CHUNK_SIZE_FLD | |||||
R/W-0h | R-0h | R/W-2h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODE_FLD | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RX_CRC_DATA_LOW_FLD | R | 0h | RX CRC data [lower]. |
23-16 | RX_CRC_DATA_UP_FLD | R | 0h | RX CRC data [upper]. |
15 | CRC_OUT_ENABLE_FLD | R/W | 0h | CRC# output enable bit. |
14-11 | MODE_BIT_RESV1_FLD | R | 0h | Reserved |
10-8 | CHUNK_SIZE_FLD | R/W | 2h | It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers. |
7-0 | MODE_FLD | R/W | 0h | These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled. |
OSPI_SRAM_FILL_REG is shown in Figure 12-1558 and described in Table 12-3114.
Return to Summary Table.
SRAM Fill Register.
This register keeps the values of current fill levels of both SRAM partitions.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SRAM_FILL_INDAC_WRITE_FLD | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRAM_FILL_INDAC_READ_FLD | |||||||||||||||
R-0h | |||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SRAM_FILL_INDAC_WRITE_FLD | R | 0h | SRAM Fill Level [Indirect Write Partition]. |
15-0 | SRAM_FILL_INDAC_READ_FLD | R | 0h | SRAM Fill Level [Indirect Read Partition]. |
OSPI_TX_THRESH_REG is shown in Figure 12-1559 and described in Table 12-3116.
Return to Summary Table.
TX Threshold Register.
This register allows to define the TX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_THRESH_RESV_FLD | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_THRESH_RESV_FLD | LEVEL_FLD | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | TX_THRESH_RESV_FLD | R | 0h | Reserved |
4-0 | LEVEL_FLD | R/W | 1h | Defines the level at which the small TX FIFO not full interrupt is generated |
OSPI_RX_THRESH_REG is shown in Figure 12-1560 and described in Table 12-3118.
Return to Summary Table.
RX Threshold Register.
This register allows to define the RX FIFO level arousing the corresponding interrupt. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_THRESH_RESV_FLD | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_THRESH_RESV_FLD | LEVEL_FLD | ||||||||||||||
R-0h | R/W-1h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RX_THRESH_RESV_FLD | R | 0h | Reserved |
4-0 | LEVEL_FLD | R/W | 1h | Defines the level at which the small RX FIFO not empty interrupt is generated. |
OSPI_WRITE_COMPLETION_CTRL_REG is shown in Figure 12-1561 and described in Table 12-3120.
Return to Summary Table.
Write Completion Control Register. This register defines how the controller will poll the device following a write transfer.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
POLL_REP_DELAY_FLD | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
POLL_COUNT_FLD | |||||||
R/W-1h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENABLE_POLLING_EXP_FLD | DISABLE_POLLING_FLD | POLLING_POLARITY_FLD | WR_COMP_CTRL_RESV1_FLD | POLLING_BIT_INDEX_FLD | |||
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPCODE_FLD | |||||||
R/W-5h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | POLL_REP_DELAY_FLD | R/W | 0h | Polling repetition delay. |
23-16 | POLL_COUNT_FLD | R/W | 1h | Polling count. |
15 | ENABLE_POLLING_EXP_FLD | R/W | 0h | Enable polling expiration. |
14 | DISABLE_POLLING_FLD | R/W | 0h | Disable polling. |
13 | POLLING_POLARITY_FLD | R/W | 0h | Polling polarity. |
12-11 | WR_COMP_CTRL_RESV1_FLD | R | 0h | Reserved |
10-8 | POLLING_BIT_INDEX_FLD | R/W | 0h | Polling bit index. |
7-0 | OPCODE_FLD | R/W | 5h | Polling opcode. |
OSPI_NO_OF_POLLS_BEF_EXP_REG is shown in Figure 12-1562 and described in Table 12-3122.
Return to Summary Table.
Polling Expiration Register.
This register defines maximum number of poll cycles. If the expected value of the bit being polled is not gotten after number defined in this register, the auto-polling is done on the next phase.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NO_OF_POLLS_BEF_EXP_FLD | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NO_OF_POLLS_BEF_EXP_FLD | R/W | FFFFFFFFh | Defines the numbers of poll cycles after which auto-polling phase terminates and polling expiration interrupt is generated. |
OSPI_IRQ_STATUS_REG is shown in Figure 12-1563 and described in Table 12-3124.
Return to Summary Table.
Interrupt Status Register. The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 6 through 10 are only valid when legacy SPI mode is active.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IRQ_STAT_RESV_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQ_STAT_RESV_FLD | ECC_FAIL_FLD | TX_CRC_CHUNK_BRK_FLD | RX_CRC_DATA_VAL_FLD | RX_CRC_DATA_ERR_FLD | |||
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IRQ_STAT_RESV1_FLD | STIG_REQ_INT_FLD | POLL_EXP_INT_FLD | INDRD_SRAM_FULL_FLD | RX_FIFO_FULL_FLD | RX_FIFO_NOT_EMPTY_FLD | TX_FIFO_FULL_FLD | TX_FIFO_NOT_FULL_FLD |
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RECV_OVERFLOW_FLD | INDIRECT_XFER_LEVEL_BREACH_FLD | ILLEGAL_ACCESS_DET_FLD | PROT_WR_ATTEMPT_FLD | INDIRECT_READ_REJECT_FLD | INDIRECT_OP_DONE_FLD | UNDERFLOW_DET_FLD | MODE_M_FAIL_FLD |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | IRQ_STAT_RESV_FLD | R | 0h | Reserved |
19 | ECC_FAIL_FLD | R/W1C | 0h | ECC failure. |
18 | TX_CRC_CHUNK_BRK_FLD | R/W1C | 0h | TX CRC chunk was broken. |
17 | RX_CRC_DATA_VAL_FLD | R/W1C | 0h | RX CRC data valid. |
16 | RX_CRC_DATA_ERR_FLD | R/W1C | 0h | RX CRC data error. |
15 | IRQ_STAT_RESV1_FLD | R | 0h | Reserved |
14 | STIG_REQ_INT_FLD | R/W1C | 0h | The controller is ready for getting another STIG request. |
13 | POLL_EXP_INT_FLD | R/W1C | 0h | The maximum number of programmed polls cycles is expired. |
12 | INDRD_SRAM_FULL_FLD | R/W1C | 0h | Indirect Read Partition overflow. |
11 | RX_FIFO_FULL_FLD | R/W1C | 0h | Small RX FIFO full. Current FIFO status can be ignored in non-SPI legacy mode. 0h = FIFO is not full 1h = FIFO is full |
10 | RX_FIFO_NOT_EMPTY_FLD | R/W1C | 0h | Small RX FIFO not empty. Current FIFO status can be ignored in non-SPI legacy mode. 0h = FIFO has less than RX THRESHOLD entries. 1h = FIFO has >= THRESHOLD entries. |
9 | TX_FIFO_FULL_FLD | R/W1C | 0h | Small TX FIFO full. Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO is not full 1h = FIFO is full |
8 | TX_FIFO_NOT_FULL_FLD | R/W1C | 0h | Small TX FIFO not full. Current FIFO status can be ignored in non-SPI legacy mode 0h = FIFO has >= THRESHOLD entries. 1h = FIFO has less than THRESHOLD entries. |
7 | RECV_OVERFLOW_FLD | R/W1C | 0h | Receive Overflow. This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0h = no overflow has been detected. 1h = an overflow has occurred. |
6 | INDIRECT_XFER_LEVEL_BREACH_FLD | R/W1C | 0h | Indirect Transfer Watermark Level Breached. |
5 | ILLEGAL_ACCESS_DET_FLD | R/W1C | 0h | Illegal AHB access has been detected AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger. |
4 | PROT_WR_ATTEMPT_FLD | R/W1C | 0h | Write to protected area was attempted and rejected. |
3 | INDIRECT_READ_REJECT_FLD | R/W1C | 0h | Indirect operation was requested but could not be accepted. Two indirect operations already in storage. |
2 | INDIRECT_OP_DONE_FLD | R/W1C | 0h | Indirect Operation Complete: Controller has completed last triggered indirect operation. |
1 | UNDERFLOW_DET_FLD | R/W1C | 0h | Underflow Detected: 0h = no underflow has been detected 1h = underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with the requested write operation. This bit is reset only by a system reset and cleared only when the register is read. |
0 | MODE_M_FAIL_FLD | R/W1C | 0h | Mode M Failure. Mode M failure indicates the voltage on pin N_SS_IN is inconsistent with the SPI mode. Set =1 if N_SS_IN is low in master mode [multi-master contention]. These conditions will clear the spi_enable bit and disable the SPI. This bit is reset only by a system reset and cleared only when this register is: Read 0h = no mode fault has been detected. Read 1h = a mode fault has occurred. |
OSPI_IRQ_MASK_REG is shown in Figure 12-1564 and described in Table 12-3126.
Return to Summary Table.
Interrupt Mask Register.
This register allows the user to mask/unmask particular interrupt sources. This register should be setup while the controller is idle.
0h = the interrupt for the corresponding interrupt status register bit is disabled.
1h = the interrupt for the corresponding interrupt status register bit is enabled.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IRQ_MASK_RESV_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IRQ_MASK_RESV_FLD | ECC_FAIL_MASK_FLD | TX_CRC_CHUNK_BRK_MASK_FLD | RX_CRC_DATA_VAL_MASK_FLD | RX_CRC_DATA_ERR_MASK_FLD | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IRQ_MASK_RESV1_FLD | STIG_REQ_MASK_FLD | POLL_EXP_INT_MASK_FLD | INDRD_SRAM_FULL_MASK_FLD | RX_FIFO_FULL_MASK_FLD | RX_FIFO_NOT_EMPTY_MASK_FLD | TX_FIFO_FULL_MASK_FLD | TX_FIFO_NOT_FULL_MASK_FLD |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RECV_OVERFLOW_MASK_FLD | INDIRECT_XFER_LEVEL_BREACH_MASK_FLD | ILLEGAL_ACCESS_DET_MASK_FLD | PROT_WR_ATTEMPT_MASK_FLD | INDIRECT_READ_REJECT_MASK_FLD | INDIRECT_OP_DONE_MASK_FLD | UNDERFLOW_DET_MASK_FLD | MODE_M_FAIL_MASK_FLD |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | IRQ_MASK_RESV_FLD | R | 0h | Reserved |
19 | ECC_FAIL_MASK_FLD | R/W | 0h | ECC failure Mask |
18 | TX_CRC_CHUNK_BRK_MASK_FLD | R/W | 0h | TX CRC chunk was broken Mask |
17 | RX_CRC_DATA_VAL_MASK_FLD | R/W | 0h | RX CRC data valid Mask |
16 | RX_CRC_DATA_ERR_MASK_FLD | R/W | 0h | RX CRC data error Mask |
15 | IRQ_MASK_RESV1_FLD | R | 0h | Reserved |
14 | STIG_REQ_MASK_FLD | R/W | 0h | STIG request completion Mask |
13 | POLL_EXP_INT_MASK_FLD | R/W | 0h | Polling expiration detected Mask |
12 | INDRD_SRAM_FULL_MASK_FLD | R/W | 0h | Indirect Read Partition overflow mask |
11 | RX_FIFO_FULL_MASK_FLD | R/W | 0h | Small RX FIFO full Mask |
10 | RX_FIFO_NOT_EMPTY_MASK_FLD | R/W | 0h | Small RX FIFO not empty Mask |
9 | TX_FIFO_FULL_MASK_FLD | R/W | 0h | Small TX FIFO full Mask |
8 | TX_FIFO_NOT_FULL_MASK_FLD | R/W | 0h | Small TX FIFO not full Mask |
7 | RECV_OVERFLOW_MASK_FLD | R/W | 0h | Receive Overflow Mask |
6 | INDIRECT_XFER_LEVEL_BREACH_MASK_FLD | R/W | 0h | Transfer Watermark Breach Mask |
5 | ILLEGAL_ACCESS_DET_MASK_FLD | R/W | 0h | Illegal Access Detected Mask |
4 | PROT_WR_ATTEMPT_MASK_FLD | R/W | 0h | Protected Area Write Attempt Mask |
3 | INDIRECT_READ_REJECT_MASK_FLD | R/W | 0h | Indirect Read Reject Mask |
2 | INDIRECT_OP_DONE_MASK_FLD | R/W | 0h | Indirect Complete Mask |
1 | UNDERFLOW_DET_MASK_FLD | R/W | 0h | Underflow Detected Mask |
0 | MODE_M_FAIL_MASK_FLD | R/W | 0h | Mode M Failure Mask |
OSPI_LOWER_WR_PROT_REG is shown in Figure 12-1565 and described in Table 12-3128.
Return to Summary Table.
Lower Write Protection Register.
This register allows to define lower boundary of the write protection area. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUBSECTOR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SUBSECTOR_FLD | R/W | 0h | Lower Block Number. The block number that defines the lower block in
the range of blocks that is to be locked from writing. |
OSPI_UPPER_WR_PROT_REG is shown in Figure 12-1566 and described in Table 12-3130.
Return to Summary Table.
Upper Write Protection Register.
This register allows to define upper boundary of the write protection area. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUBSECTOR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SUBSECTOR_FLD | R/W | 0h | Lower Block Number. |
OSPI_WR_PROT_CTRL_REG is shown in Figure 12-1567 and described in Table 12-3132.
Return to Summary Table.
Write Protection Control Register.
This register allows to define the configuration of write protection settings. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WR_PROT_CTRL_RESV_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WR_PROT_CTRL_RESV_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WR_PROT_CTRL_RESV_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WR_PROT_CTRL_RESV_FLD | ENB_FLD | INV_FLD | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | WR_PROT_CTRL_RESV_FLD | R | 0h | Reserved |
1 | ENB_FLD | R/W | 0h | Write Protection Enable Bit. |
0 | INV_FLD | R/W | 0h | Write Protection Inversion Bit. |
OSPI_INDIRECT_READ_XFER_CTRL_REG is shown in Figure 12-1568 and described in Table 12-3134.
Return to Summary Table.
Indirect Read Transfer Control Register.
This register allows control of the Indirect Read Transfer logic.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INDIR_RD_XFER_RESV_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INDIR_RD_XFER_RESV_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INDIR_RD_XFER_RESV_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM_IND_OPS_DONE_FLD | IND_OPS_DONE_STATUS_FLD | RD_QUEUED_FLD | SRAM_FULL_FLD | RD_STATUS_FLD | CANCEL_FLD | START_FLD | |
R-0h | R/W1C-0h | R-0h | R/W1C-0h | R-0h | W-0h | W-0h | |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | INDIR_RD_XFER_RESV_FLD | R | 0h | Reserved |
7-6 | NUM_IND_OPS_DONE_FLD | R | 0h | This field contains the number of indirect
operations which have been completed. |
5 | IND_OPS_DONE_STATUS_FLD | R/W1C | 0h | Indirect Completion Status. |
4 | RD_QUEUED_FLD | R | 0h | Queued Indirect Read Operations. |
3 | SRAM_FULL_FLD | R/W1C | 0h | SRAM Full. SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it indirect operation [status]. |
2 | RD_STATUS_FLD | R | 0h | Indirect Read Status. |
1 | CANCEL_FLD | W | 0h | Cancel Indirect Read. |
0 | START_FLD | W | 0h | Start Indirect Read. |
OSPI_INDIRECT_READ_XFER_WATERMARK_REG is shown in Figure 12-1569 and described in Table 12-3136.
Return to Summary Table.
Indirect Read Transfer Watermark Register.
This register allows to define watermark level for Indirect read transfers. This register should be setup before an indirect read transfer is triggered.
Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LEVEL_FLD | R/W | 0h | Watermark Value. |
OSPI_INDIRECT_READ_XFER_START_REG is shown in Figure 12-1570 and described in Table 12-3138.
Return to Summary Table.
Indirect Read Transfer Start Address Register.
This register allows to define start address of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_FLD | R/W | 0h | Start of Indirect Access. |
OSPI_INDIRECT_READ_XFER_NUM_BYTES_REG is shown in Figure 12-1571 and described in Table 12-3140.
Return to Summary Table.
Indirect Read Transfer Number Bytes Register.
This register allows to define number of bytes to be read of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE_FLD | R/W | 0h | Indirect Number of Bytes. |
OSPI_INDIRECT_WRITE_XFER_CTRL_REG is shown in Figure 12-1572 and described in Table 12-3142.
Return to Summary Table.
Indirect Write Transfer Control Register.
This register allows control of the Indirect Write Transfer logic.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
INDIR_WR_XFER_RESV2_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INDIR_WR_XFER_RESV2_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INDIR_WR_XFER_RESV2_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM_IND_OPS_DONE_FLD | IND_OPS_DONE_STATUS_FLD | WR_QUEUED_FLD | INDIR_WR_XFER_RESV1_FLD | WR_STATUS_FLD | CANCEL_FLD | START_FLD | |
R-0h | R/W1C-0h | R-0h | R-0h | R-0h | W-0h | W-0h | |
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | INDIR_WR_XFER_RESV2_FLD | R | 0h | Reserved |
7-6 | NUM_IND_OPS_DONE_FLD | R | 0h | This field contains the number of indirect
operations which have been completed. |
5 | IND_OPS_DONE_STATUS_FLD | R/W1C | 0h | Indirect Completion Status. |
4 | WR_QUEUED_FLD | R | 0h | Two indirect write operations have been queued. |
3 | INDIR_WR_XFER_RESV1_FLD | R | 0h | Reserved |
2 | WR_STATUS_FLD | R | 0h | Indirect Write Status. |
1 | CANCEL_FLD | W | 0h | Cancel Indirect Write. |
0 | START_FLD | W | 0h | Start Indirect Write. |
OSPI_INDIRECT_WRITE_XFER_WATERMARK_REG is shown in Figure 12-1573 and described in Table 12-3144.
Return to Summary Table.
Indirect Write Transfer Watermark Register.
This register allows to define watermark level for Indirect write transfers. This register should be setup before an indirect write transfer is triggered.
Some of the OSPI features described in this section may not be supported on this family of devices. For more information, see OSPI Not Supported Features.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL_FLD | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LEVEL_FLD | R/W | FFFFFFFFh | Watermark Value. |
OSPI_INDIRECT_WRITE_XFER_START_REG is shown in Figure 12-1574 and described in Table 12-3146.
Return to Summary Table.
Indirect Write Transfer Start Address Register.
This register allows to define start address of indirect write transfer which is about to be triggered. This register should be setup before an indirect write transfer is triggered.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_FLD | R/W | 0h | Start of Indirect Access. |
OSPI_INDIRECT_WRITE_XFER_NUM_BYTES_REG is shown in Figure 12-1575 and described in Table 12-3148.
Return to Summary Table.
Indirect Write Transfer Number Bytes Register.
This register allows to define number of bytes to be written of indirect read transfer which is about to be triggered. This register should be setup before an indirect read transfer is triggered.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 007Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VALUE_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VALUE_FLD | R/W | 0h | Indirect Number of Bytes. |
OSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG is shown in Figure 12-1576 and described in Table 12-3150.
Return to Summary Table.
Indirect Trigger Address Range Register.
This register allows the user to define the indirect trigger address range. If the configured range exceeds number of bytes programmed for particular indirect transfer, there is no need to detect indirect trigger address boundaries by software. This register should be setup before an indirect read transfer is triggered.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IND_RANGE_RESV1_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IND_RANGE_RESV1_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IND_RANGE_RESV1_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IND_RANGE_RESV1_FLD | IND_RANGE_WIDTH_FLD | ||||||
R-0h | R/W-4h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | IND_RANGE_RESV1_FLD | R | 0h | Reserved |
3-0 | IND_RANGE_WIDTH_FLD | R/W | 4h | Indirect Range Width. |
OSPI_FLASH_COMMAND_CTRL_MEM_REG is shown in Figure 12-1577 and described in Table 12-3152.
Return to Summary Table.
Flash Command Control Memory Register.
This register controls the Memory Bank accesses. It also defines the number of bytes intended to get by STIG access configured to use the STIG Memory Bank.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 008Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FLASH_COMMAND_CTRL_MEM_RESV1_FLD | MEM_BANK_ADDR_FLD | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MEM_BANK_ADDR_FLD | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | NB_OF_STIG_READ_BYTES_FLD | |||||
R/W-0h | R-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MEM_BANK_READ_DATA_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLASH_COMMAND_CTRL_MEM_RESV3_FLD | MEM_BANK_REQ_IN_PROGRESS_FLD | TRIGGER_MEM_BANK_REQ_FLD | |||||
R-0h | R-0h | W-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | FLASH_COMMAND_CTRL_MEM_RESV1_FLD | R | 0h | Reserved |
28-20 | MEM_BANK_ADDR_FLD | R/W | 0h | Memory Bank Address. |
19 | FLASH_COMMAND_CTRL_MEM_RESV2_FLD | R | 0h | Reserved |
18-16 | NB_OF_STIG_READ_BYTES_FLD | R/W | 0h | Number of STIG Memory Bank Read Bytes. |
15-8 | MEM_BANK_READ_DATA_FLD | R | 0h | Memory Bank Read Data. |
7-2 | FLASH_COMMAND_CTRL_MEM_RESV3_FLD | R | 0h | Reserved |
1 | MEM_BANK_REQ_IN_PROGRESS_FLD | R | 0h | Memory Bank data request in progress. |
0 | TRIGGER_MEM_BANK_REQ_FLD | W | 0h | Trigger the Memory Bank data request. |
OSPI_FLASH_CMD_CTRL_REG is shown in Figure 12-1578 and described in Table 12-3154.
Return to Summary Table.
Flash Command Control Register.
This register controls SPI transactions generated by STIG. It allows to define corresponding SPI frame to particular command, triggering the transfer and polling for its completion.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMD_OPCODE_FLD | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
ENB_READ_DATA_FLD | NUM_RD_DATA_BYTES_FLD | ENB_COMD_ADDR_FLD | ENB_MODE_BIT_FLD | NUM_ADDR_BYTES_FLD | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ENB_WRITE_DATA_FLD | NUM_WR_DATA_BYTES_FLD | NUM_DUMMY_CYCLES_FLD | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM_DUMMY_CYCLES_FLD | FLASH_CMD_CTRL_RESV1_FLD | STIG_MEM_BANK_EN_FLD | CMD_EXEC_STATUS_FLD | CMD_EXEC_FLD | |||
R/W-0h | R-0h | R/W-0h | R-0h | W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | CMD_OPCODE_FLD | R/W | 0h | Command Opcode. |
23 | ENB_READ_DATA_FLD | R/W | 0h | Read Data Enable. Set to 1 if the command specified in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires read data bytes to be received from the device. |
22-20 | NUM_RD_DATA_BYTES_FLD | R/W | 0h | Number of Read Data Bytes: Up to 8 data bytes may be read using this command Set to 0 for 1 byte and 7 for 8 bytes |
19 | ENB_COMD_ADDR_FLD | R/W | 0h | Command Address Enable. Set to 1 if the command specified in OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD requires an address This should be setup before triggering the command via writing a 1 to the execute field. |
18 | ENB_MODE_BIT_FLD | R/W | 0h | Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes |
17-16 | NUM_ADDR_BYTES_FLD | R/W | 0h | Number of Address Bytes. Set to the number of address bytes required [the address itself is programmed in the OSPI_FLASH_CMD_ADDR_REG. This should be setup before triggering the command via the OSPI_FLASH_CMD_CTRL_REG[0] CMD_EXEC_FLD: 0h = 1 address byte 1h = 2 address bytes 2h = 3 address bytes 3h = 4 address bytes |
15 | ENB_WRITE_DATA_FLD | R/W | 0h | Write Data Enable. |
14-12 | NUM_WR_DATA_BYTES_FLD | R/W | 0h | Number of Write Data Bytes. |
11-7 | NUM_DUMMY_CYCLES_FLD | R/W | 0h | Number of Dummy cycles. |
6-3 | FLASH_CMD_CTRL_RESV1_FLD | R | 0h | Reserved |
2 | STIG_MEM_BANK_EN_FLD | R/W | 0h | STIG Memory Bank enable bit. |
1 | CMD_EXEC_STATUS_FLD | R | 0h | Command execution in progress. |
0 | CMD_EXEC_FLD | W | 0h | Execute the command. |
OSPI_FLASH_CMD_ADDR_REG is shown in Figure 12-1579 and described in Table 12-3156.
Return to Summary Table.
Flash Command Address Register.
This register allows to define the address of the command using by the STIG controller. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | ADDR_FLD | R/W | 0h | Command Address. |
OSPI_FLASH_RD_DATA_LOWER_REG is shown in Figure 12-1580 and described in Table 12-3158.
Return to Summary Table.
Flash Command Read Data Register (Lower).
This register keeps the last 4 bytes read by STIG SPI access.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA_FLD | R | 0h | Command Read Data (Lower). |
OSPI_FLASH_RD_DATA_UPPER_REG is shown in Figure 12-1581 and described in Table 12-3160.
Return to Summary Table.
Flash Command Read Data Register (Upper).
This register keeps the last but 4 bytes read by STIG SPI access. This register in conjunction with the OSPI_FLASH_RD_DATA_LOWER_REG register enables the controller to keep 8 last bytes read from the Flash Device using STIG.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA_FLD | R | 0h | Command Read Data (Upper). |
OSPI_FLASH_WR_DATA_LOWER_REG is shown in Figure 12-1582 and described in Table 12-3162.
Return to Summary Table.
Flash Command Write Data Register (Lower).
This register takes the first 4 bytes to be written by STIG.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA_FLD | R/W | 0h | Command Write Data Lower Byte. |
OSPI_FLASH_WR_DATA_UPPER_REG is shown in Figure 12-1583 and described in Table 12-3164.
Return to Summary Table.
Flash Command Write Data Register (Upper).
This register takes the bytes ranging from 5 to 8 to be written by STIG.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA_FLD | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA_FLD | R/W | 0h | Command Write Data Upper Byte. |
OSPI_POLLING_FLASH_STATUS_REG is shown in Figure 12-1584 and described in Table 12-3166.
Return to Summary Table.
Polling Flash Status Register.
This register provides auto-polling data. It acts as the extension for the OSPI_WRITE_COMPLETION_CTRL_REG register where full status is not available and any action can be taken only relying on the indication of single bit being polled for.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DEVICE_STATUS_RSVD_FLD2 | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEVICE_STATUS_RSVD_FLD2 | DEVICE_STATUS_NB_DUMMY | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DEVICE_STATUS_RSVD_FLD1 | DEVICE_STATUS_VALID_FLD | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEVICE_STATUS_FLD | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | DEVICE_STATUS_RSVD_FLD2 | R | 0h | Reserved |
19-16 | DEVICE_STATUS_NB_DUMMY | R/W | 0h | Number of dummy cycles for auto-polling. |
15-9 | DEVICE_STATUS_RSVD_FLD1 | R | 0h | Reserved |
8 | DEVICE_STATUS_VALID_FLD | R | 0h | Device Status Valid. |
7-0 | DEVICE_STATUS_FLD | R | 0h | Defines actual Status Register of Device. |
OSPI_PHY_CONFIGURATION_REG is shown in Figure 12-1585 and described in Table 12-3168.
Return to Summary Table.
PHY Configuration Register.
This register defines the configuration of PHY Module and controls the internal DLL. This register should be setup while the controller is idle.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PHY_CONFIG_RESYNC_FLD | PHY_CONFIG_RESET_FLD | PHY_CONFIG_RX_DLL_BYPASS_FLD | PHY_CONFIG_RESV2_FLD | ||||
W-0h | W-1h | R/W-0h | R-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PHY_CONFIG_RESV2_FLD | PHY_CONFIG_TX_DLL_DELAY_FLD | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHY_CONFIG_RESV1_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_CONFIG_RESV1_FLD | PHY_CONFIG_RX_DLL_DELAY_FLD | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PHY_CONFIG_RESYNC_FLD | W | 0h | Re-synchronisation DLL. |
30 | PHY_CONFIG_RESET_FLD | W | 1h | DLL Reset. |
29 | PHY_CONFIG_RX_DLL_BYPASS_FLD | R/W | 0h | RX DLL Bypass. |
28-23 | PHY_CONFIG_RESV2_FLD | R | 0h | Reserved |
22-16 | PHY_CONFIG_TX_DLL_DELAY_FLD | R/W | 0h | TX DLL Delay. |
15-7 | PHY_CONFIG_RESV1_FLD | R | 0h | Reserved |
6-0 | PHY_CONFIG_RX_DLL_DELAY_FLD | R/W | 0h | RX DLL Delay. |
OSPI_PHY_MASTER_CONTROL_REG is shown in Figure 12-1586 and described in Table 12-3170.
Return to Summary Table.
PHY DLL Master Control Register.
This register defines the configuration and control logic of DLL intended to work in DLL Master Mode.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PHY_MASTER_CONTROL_RESV3_FLD | PHY_MASTER_LOCK_MODE_FLD | ||||||
R-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PHY_MASTER_BYPASS_MODE_FLD | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | PHY_MASTER_CONTROL_RESV2_FLD | PHY_MASTER_NB_INDICATIONS_FLD | ||||
R/W-1h | R/W-0h | R-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PHY_MASTER_CONTROL_RESV1_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PHY_MASTER_CONTROL_RESV1_FLD | PHY_MASTER_INITIAL_DELAY_FLD | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | PHY_MASTER_CONTROL_RESV3_FLD | R | 0h | Reserved |
24 | PHY_MASTER_LOCK_MODE_FLD | R/W | 0h | Determines if the master delay line locks on a full cycle or half cycle of delay. This bit need not be written by software. If DLL does not lock in full cycle, it will automatically try to lock in half cycle mode. |
23 | PHY_MASTER_BYPASS_MODE_FLD | R/W | 1h | Controls the bypass mode of the master and slave DLLs.
Master DLL is disabled with only 1 delay element in its delay line. The slave delay lines decode delays in absolute delay elements rather than as fractional delays. Delays are defined in OSPI_PHY_CONFIGURATION_REG[22-16] PHY_CONFIG_TX_DLL_DELAY_FLD and OSPI_PHY_CONFIGURATION_REG[6-0] PHY_CONFIG_RX_DLL_ DELAY_FLD bit fields. |
22-20 | PHY_MASTER_PHASE_DETECT_SELECTOR_FLD | R/W | 0h | Selects the number of delay elements to be inserted between the phase detect flip-flops. |
19 | PHY_MASTER_CONTROL_RESV2_FLD | R | 0h | Reserved |
18-16 | PHY_MASTER_NB_INDICATIONS_FLD | R/W | 0h | Holds the number of consecutive increment or decrement indications. |
15-7 | PHY_MASTER_CONTROL_RESV1_FLD | R | 0h | Reserved |
6-0 | PHY_MASTER_INITIAL_DELAY_FLD | R/W | 0h | This value is the initial delay value for the Master DLL. |
OSPI_DLL_OBSERVABLE_LOWER_REG is shown in Figure 12-1587 and described in Table 12-3172.
Return to Summary Table.
DLL Observable Register Lower.
This register allows to observe and debug DLL status.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD | DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD | DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD | DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD | |||||
R-0h | R-0h | R-0h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD | R | 0h | Holds the state of the cumulative lock incremental steps when the OSPI_DLL_OBSERVABLE_LOWER_REG[7-3] DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD of this parameter was triggered to increment or was last saturated at a value of 1Fh. |
23-16 | DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD | R | 0h | Holds the state of the cumulative lock decremental steps when the OSPI_DLL_OBSERVABLE_LOWER_REG[7-3] DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD of this parameter was triggered to decrement or was last saturated at a value of 1Fh. |
15 | DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD | R | 0h | This bit indicates that lock of loopback is done. |
14-8 | DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD | R | 0h | DLL Lock Value. |
7-3 | DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD | R | 0h | DLL Unlock Counter. |
2-1 | DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD | R | 0h | DLL Locked Mode. |
0 | DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD | R | 0h | DLL Lock. |
OSPI_DLL_OBSERVABLE_UPPER_REG is shown in Figure 12-1588 and described in Table 12-3174.
Return to Summary Table.
DLL Observable Register Upper.
This register allows to observe and debug DLL status.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DLL_OBSERVABLE_UPPER_RESV2_FLD | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DLL_OBSERVABLE_UPPER_RESV2_FLD | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DLL_OBSERVABLE_UPPER_RESV1_FLD | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLL_OBSERVABLE_UPPER_RESV1_FLD | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | DLL_OBSERVABLE_UPPER_RESV2_FLD | R | 0h | Reserved |
22-16 | DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD | R | 0h | TX DLL decoder output. |
15-7 | DLL_OBSERVABLE_UPPER_RESV1_FLD | R | 0h | Reserved |
6-0 | DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD | R | 0h | RX DLL decoder output. |
OSPI_OPCODE_EXT_LOWER_REG is shown in Figure 12-1589 and described in Table 12-3176.
Return to Summary Table.
Opcode Extension Register (Lower).
This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by OSPI_CONFIG_REG[30] DUAL_BYTE_OPCODE_EN_FLD bit.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EXT_READ_OPCODE_FLD | EXT_WRITE_OPCODE_FLD | ||||||||||||||
R/W-13h | R/W-EDh | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXT_POLL_OPCODE_FLD | EXT_STIG_OPCODE_FLD | ||||||||||||||
R/W-FAh | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | EXT_READ_OPCODE_FLD | R/W | 13h | Supplement byte of any Read Opcoded defined in the OSPI_DEV_INSTR_RD_CONFIG_REG[7-0] RD_OPCODE_NON_XIP_FLD bit field. |
23-16 | EXT_WRITE_OPCODE_FLD | R/W | EDh | Supplement byte of any Write Opcode defined in the OSPI_DEV_INSTR_WR_CONFIG_REG[7-0] WR_OPCODE_FLD bit field. |
15-8 | EXT_POLL_OPCODE_FLD | R/W | FAh | Supplement byte of any Polling Opcode defined in the OSPI_WRITE_COMPLETION_CTRL_REG[7-0] OPCODE_FLD bit field. |
7-0 | EXT_STIG_OPCODE_FLD | R/W | 0h | Supplement byte of any STIG Opcode defined in the OSPI_FLASH_CMD_CTRL_REG[31-24] CMD_OPCODE_FLD bit field. |
OSPI_OPCODE_EXT_UPPER_REG is shown in Figure 12-1590 and described in Table 12-3178.
Return to Summary Table.
Opcode Extension Register (Upper).
This register provides the supplementing opcodes for Dual Byte Opcode Mode activated by OSPI_CONFIG_REG[30] DUAL_BYTE_OPCODE_EN_FLD bit.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WEL_OPCODE_FLD | EXT_WEL_OPCODE_FLD | ||||||||||||||
R/W-6h | R/W-F9h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPCODE_EXT_UPPER_RESV1_FLD | |||||||||||||||
R-0h | |||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | WEL_OPCODE_FLD | R/W | 6h | WEL Opcode byte 1. |
23-16 | EXT_WEL_OPCODE_FLD | R/W | F9h | WEL Opcode byte 2 (Optional). |
15-0 | OPCODE_EXT_UPPER_RESV1_FLD | R | 0h | Reserved |
OSPI_MODULE_ID_REG is shown in Figure 12-1591 and described in Table 12-3180.
Return to Summary Table.
Module ID Register.
This register provides the IP release number and the configuration data.
Instance | Physical Address |
---|---|
FSS0_OSPI0_CTRL | 0FC4 00FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FIX_PATCH_FLD | |||||||
R-3h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODULE_ID_FLD | |||||||
R-3h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MODULE_ID_FLD | |||||||
R-3h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MODULE_ID_RESV_FLD | CONF_FLD | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | FIX_PATCH_FLD | R | 3h | Fix/path number related to revision described by 3 LSBs of this register |
23-8 | MODULE_ID_FLD | R | 3h | Module/Revision ID number |
7-2 | MODULE_ID_RESV_FLD | R | 0h | Reserved |
1-0 | CONF_FLD | R | 0h | Configuration ID number: 0h = OCTAL + PHY Configuration 1h = OCTAL Configuration 2h = QUAD + PHY Configuration 3h = QUAD Configuration |
Table 12-3182 lists the memory-mapped registers for the OSPI ECC Aggregator. All register offset addresses not listed in Table 12-3182 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8000h |
Offset | Acronym | Register Name | FSS0_OSPI0_ECC_AGGR Physical Address |
---|---|---|---|
0h | OSPI_ECC_REV | Aggregator revision register | 0071 8000h |
8h | OSPI_ECC_VECTOR | ECC vector register | 0071 8008h |
Ch | OSPI_ECC_STAT | Miscellaneous status register | 0071 800Ch |
10h + formula | OSPI_RESERVED_SVBUS_Y | Reserved area for serial VBUS registers | 0071 8010h + formula |
3Ch | OSPI_ECC_SEC_EOI_REG | SEC end of interrupt register | 0071 803Ch |
40h | OSPI_ECC_SEC_STATUS_REG0 | SEC interrupt status register 0 | 0071 8040h |
80h | OSPI_ECC_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 0071 8080h |
C0h | OSPI_ECC_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 0071 80C0h |
13Ch | OSPI_ECC_DED_EOI_REG | DED end of interrupt register | 0071 813Ch |
140h | OSPI_ECC_DED_STATUS_REG0 | DED interrupt status register 0 | 0071 8140h |
180h | OSPI_ECC_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 0071 8180h |
1C0h | OSPI_ECC_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 0071 81C0h |
200h | OSPI_ECC_AGGR_ENABLE_SET | Aggregator interrupt enable set register | 0071 8200h |
204h | OSPI_ECC_AGGR_ENABLE_CLR | Aggregator interrupt enable clear register | 0071 8204h |
208h | OSPI_ECC_AGGR_STATUS_SET | Aggregator interrupt status set register | 0071 8208h |
20Ch | OSPI_ECC_AGGR_STATUS_CLR | Aggregator interrupt status clear register | 0071 820Ch |
OSPI_ECC_REV is shown in Figure 12-1592 and described in Table 12-3184.
Return to Summary Table.
Revision parameters.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
OSPI_ECC_VECTOR is shown in Figure 12-1593 and described in Table 12-3186.
Return to Summary Table.
ECC Vector Register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
OSPI_ECC_STAT is shown in Figure 12-1594 and described in Table 12-3188.
Return to Summary Table.
Miscellaneous status register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 800Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-1h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 1h | Indicates the number of RAMs serviced by the ECC aggregator. |
OSPI_RESERVED_SVBUS_Y is shown in Figure 12-1595 and described in .
Return to Summary Table.
Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8010h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
OSPI_ECC_SEC_EOI_REG is shown in Figure 12-1596 and described in Table 12-3192.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 803Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
OSPI_ECC_SEC_STATUS_REG0 is shown in Figure 12-1597 and described in Table 12-3194.
Return to Summary Table.
Interrupt Status Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_PEND | R/W1S | 0h | Interrupt Pending Status for sram_pend |
OSPI_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-1598 and described in Table 12-3196.
Return to Summary Table.
Interrupt Enable Set Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for sram_pend |
OSPI_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-1599 and described in Table 12-3198.
Return to Summary Table.
Interrupt Enable Clear Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 80C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for sram_pend |
OSPI_ECC_DED_EOI_REG is shown in Figure 12-1600 and described in Table 12-3200.
Return to Summary Table.
EOI Register.
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 813Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
OSPI_ECC_DED_STATUS_REG0 is shown in Figure 12-1601 and described in Table 12-3202.
Return to Summary Table.
Interrupt Status Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_PEND | R/W1S | 0h | Interrupt Pending Status for sram_pend. |
OSPI_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-1602 and described in Table 12-3204.
Return to Summary Table.
Interrupt Enable Set Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for sram_pend. |
OSPI_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-1603 and described in Table 12-3206.
Return to Summary Table.
Interrupt Enable Clear Register 0.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 81C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SRAM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRAM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for sram_pend. |
OSPI_ECC_AGGR_ENABLE_SET is shown in Figure 12-1604 and described in Table 12-3208.
Return to Summary Table.
AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors. |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors. |
OSPI_ECC_AGGR_ENABLE_CLR is shown in Figure 12-1605 and described in Table 12-3210.
Return to Summary Table.
AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors. |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors. |
OSPI_ECC_AGGR_STATUS_SET is shown in Figure 12-1606 and described in Table 12-3212.
Return to Summary Table.
AGGR interrupt status set register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 8208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for svbus timeout errors. |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors. |
OSPI_ECC_AGGR_STATUS_CLR is shown in Figure 12-1607 and described in Table 12-3214.
Return to Summary Table.
AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
FSS0_OSPI0_ECC_AGGR | 0071 820Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for svbus timeout errors. |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors. |