SPRUIM2 User guide

SPRUIM2H May 2020 – October 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

5.1.1.4.3 PADCFG_CTRL0_CFG0 Registers

Table 5-16 lists the memory-mapped registers for the PADCFG_CTRL0_CFG0. All register offset addresses not listed in Table 5-16 should be considered as reserved locations and the register contents should not be modified.

Table 5-15 PADCFG_CTRL0_CFG0 Instances

Instance	Base Address
PADCFG_CTRL0_CFG0	000F 0000h

Table 5-16 PADCFG_CTRL0_CFG0 Registers

Offset	Acronym	Register Name	PADCFG_CTRL0_CFG0 Physical Address
0h	PADMMR_PID	Peripheral Identification Register	000F 0000h
8h	PADMMR_MMR_CFG1	Configuration register 1	000F 0008h
1008h	PADMMR_LOCK0_KICK0	Partition 0 Lock Key 0 Register	000F 1008h
100Ch	PADMMR_LOCK0_KICK1	Partition 0 Lock Key 1 Register	000F 100Ch
1010h	PADMMR_INTR_RAW_STAT	Interrupt Raw Status Register	000F 1010h
1014h	PADMMR_INTR_STAT_CLR	Interrupt Status and Clear Register	000F 1014h
1018h	PADMMR_INTR_EN_SET	Interrupt Enable Set Register	000F 1018h
101Ch	PADMMR_INTR_EN_CLR	Interrupt Enable Clear Register	000F 101Ch
1020h	PADMMR_EOI	End of Interrupt Register	000F 1020h
1024h	PADMMR_FAULT_ADDR	Fault Address Register	000F 1024h
1028h	PADMMR_FAULT_TYPE	Fault Type Register	000F 1028h
102Ch	PADMMR_FAULT_ATTR	Fault Attribute Register	000F 102Ch
1030h	PADMMR_FAULT_CLR	Fault Clear Register	000F 1030h
5008h	PADMMR_LOCK1_KICK0	Partition 1 Lock Key 0 Register	000F 5008h
500Ch	PADMMR_LOCK1_KICK1	Partition 1 Lock Key 1 Register	000F 500Ch

1.4.3.1 PADMMR_PID Register ( Offset = 0h) [reset = 61800000h]

PADMMR_PID is shown in Figure 5-2 and described in Table 5-18.

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Peripheral release details.

Table 5-17 PADMMR_PID Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 0000h

Figure 5-2 PADMMR_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-180h

23	22	21	20	19	18	17	16
FUNC
R-180h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-18 PADMMR_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	PADMMR_PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	180h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number
10-8	X_MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	Custom revision number
5-0	Y_MINOR	R	0h	Minor revision number

1.4.3.2 PADMMR_MMR_CFG1 Register ( Offset = 8h) [reset = 800000BFh]

PADMMR_MMR_CFG1 is shown in Figure 5-3 and described in Table 5-20.

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Indicates the MMR configuration.

Table 5-19 PADMMR_MMR_CFG1 Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 0008h

Figure 5-3 PADMMR_MMR_CFG1 Register

31	30	29	28	27	26	25	24
RESERVED	RESERVED
R-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
PARTITIONS
R-BFh

LEGEND: R = Read Only; -n = value after reset

Table 5-20 PADMMR_MMR_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	1h	Reserved
30-8	RESERVED	R	0h	Reserved
7-0	PARTITIONS	R	BFh	Indicates present partitions

1.4.3.3 PADMMR_LOCK0_KICK0 Register ( Offset = 1008h) [reset = 0h]

PADMMR_LOCK0_KICK0 is shown in Figure 5-4 and described in Table 5-22.

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Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to PADMMR_LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written.

Table 5-21 PADMMR_LOCK0_KICK0 Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1008h

Figure 5-4 PADMMR_LOCK0_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-22 PADMMR_LOCK0_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.4.3.4 PADMMR_LOCK0_KICK1 Register ( Offset = 100Ch) [reset = 0h]

PADMMR_LOCK0_KICK1 is shown in Figure 5-5 and described in Table 5-24.

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Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to PADMMR_LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written.

Table 5-23 PADMMR_LOCK0_KICK1 Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 100Ch

Figure 5-5 PADMMR_LOCK0_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-24 PADMMR_LOCK0_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

1.4.3.5 PADMMR_INTR_RAW_STAT Register ( Offset = 1010h) [reset = 0h]

PADMMR_INTR_RAW_STAT is shown in Figure 5-6 and described in Table 5-26.

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Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test).

Table 5-25 PADMMR_INTR_RAW_STAT Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1010h

Figure 5-6 PADMMR_INTR_RAW_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR	ADDR_ERR	PROT_ERR
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-26 PADMMR_INTR_RAW_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TS	0h	Reserved
2	LOCK_ERR	W1TS	0h	Lock violation occurred (attempt to write a write-locked register with partition locked) Write 1 to set the status bit (for test) Writing 0 has no effect.
1	ADDR_ERR	W1TS	0h	Address violation occurred (attempt to read or write an invalid register address) Write 1 to set the status bit (for test) Writing 0 has no effect.
0	PROT_ERR	W1TS	0h	Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights) Write 1 to set the status bit (for test) Writing 0 has no effect.

1.4.3.6 PADMMR_INTR_STAT_CLR Register ( Offset = 1014h) [reset = 0h]

PADMMR_INTR_STAT_CLR is shown in Figure 5-7 and described in Table 5-28.

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Shows the enabled interrupt status and allows the interrupt to be cleared.

Table 5-27 PADMMR_INTR_STAT_CLR Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1014h

Figure 5-7 PADMMR_INTR_STAT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	EN_LOCK_ERR	EN_ADDR_ERR	EN_PROT_ERR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-28 PADMMR_INTR_STAT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TC	0h	Reserved
2	EN_LOCK_ERR	W1TC	0h	Enabled lock interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
1	EN_ADDR_ERR	W1TC	0h	Enabled address interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
0	EN_PROT_ERR	W1TC	0h	Enabled protection interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.

1.4.3.7 PADMMR_INTR_EN_SET Register ( Offset = 1018h) [reset = 0h]

PADMMR_INTR_EN_SET is shown in Figure 5-8 and described in Table 5-30.

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Allows interrupt enables to be set.

Table 5-29 PADMMR_INTR_EN_SET Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1018h

Figure 5-8 PADMMR_INTR_EN_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR_EN_SET	ADDR_ERR_EN_SET	PROT_ERR_EN_SET
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-30 PADMMR_INTR_EN_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TS	0h	Reserved
2	LOCK_ERR_EN_SET	W1TS	0h	Lock interrupt enable Write 1 to enable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_SET	W1TS	0h	Address interrupt enable Write 1 to enable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_SET	W1TS	0h	Protection interrupt enable Write 1 to enable protection interrupt events Writing 0 has no effect.

1.4.3.8 PADMMR_INTR_EN_CLR Register ( Offset = 101Ch) [reset = 0h]

PADMMR_INTR_EN_CLR is shown in Figure 5-9 and described in Table 5-32.

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Allows interrupt enables to be cleared.

Table 5-31 PADMMR_INTR_EN_CLR Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 101Ch

Figure 5-9 PADMMR_INTR_EN_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR_EN_CLR	ADDR_ERR_EN_CLR	PROT_ERR_EN_CLR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-32 PADMMR_INTR_EN_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TC	0h	Reserved
2	LOCK_ERR_EN_CLR	W1TC	0h	Lock interrupt disable Write 1 to disable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_CLR	W1TC	0h	Address interrupt disable Write 1 to disable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_CLR	W1TC	0h	Protection interrupt disable Write 1 to disable protection interrupt events Writing 0 has no effect.

1.4.3.9 PADMMR_EOI Register ( Offset = 1020h) [reset = 0h]

PADMMR_EOI is shown in Figure 5-10 and described in Table 5-34.

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PADMMR_EOI Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt.

Table 5-33 PADMMR_EOI Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1020h

Figure 5-10 PADMMR_EOI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								VECTOR
R-0h																								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-34 PADMMR_EOI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	VECTOR	R/W	0h	PADMMR_EOI vector value

1.4.3.10 PADMMR_FAULT_ADDR Register ( Offset = 1024h) [reset = 0h]

PADMMR_FAULT_ADDR is shown in Figure 5-11 and described in Table 5-36.

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Indicates the address of the first transfer that caused a fault to occur.

Table 5-35 PADMMR_FAULT_ADDR Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1024h

Figure 5-11 PADMMR_FAULT_ADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-36 PADMMR_FAULT_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDRESS	R	0h	Address of the faulted access

1.4.3.11 PADMMR_FAULT_TYPE Register ( Offset = 1028h) [reset = 0h]

PADMMR_FAULT_TYPE is shown in Figure 5-12 and described in Table 5-38.

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Indicates the access type of the first transfer that caused a fault to occur.

Table 5-37 PADMMR_FAULT_TYPE Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1028h

Figure 5-12 PADMMR_FAULT_TYPE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										TYPE
R-0h																										R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-38 PADMMR_FAULT_TYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	TYPE	R	0h	Type of access which faulted 0h - No fault 1h - User execute access 2h - User write access 4h - User read access 8h - Supervisor execute access 10h - Supervisor write access 20h - Supervisor read access

Bit

Field

Type

Reset

Description

31-6

RESERVED

Reserved

5-0

TYPE

Type of access which faulted

0h - No fault

1h - User execute access

2h - User write access

4h - User read access

8h - Supervisor execute access

10h - Supervisor write access

20h - Supervisor read access

1.4.3.12 PADMMR_FAULT_ATTR Register ( Offset = 102Ch) [reset = 0h]

PADMMR_FAULT_ATTR is shown in Figure 5-13 and described in Table 5-40.

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Indicates the attributes of the first transfer that caused a fault to occur.

Table 5-39 PADMMR_FAULT_ATTR Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 102Ch

Figure 5-13 PADMMR_FAULT_ATTR Register

31	30	29	28	27	26	25	24
XID
R-0h

23	22	21	20	19	18	17	16
XID				ROUTEID
R-0h				R-0h

15	14	13	12	11	10	9	8
ROUTEID
R-0h

7	6	5	4	3	2	1	0
PRIVID
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-40 PADMMR_FAULT_ATTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	XID	R	0h	Transaction ID
19-8	ROUTEID	R	0h	Route ID
7-0	PRIVID	R	0h	Privilege ID

1.4.3.13 PADMMR_FAULT_CLR Register ( Offset = 1030h) [reset = 0h]

PADMMR_FAULT_CLR is shown in Figure 5-14 and described in Table 5-42.

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Allows software to clear the current fault Clearing the current fault allows the PADMMR_FAULT_ADDR, PADMMR_FAULT_TYPE, and PADMMR_FAULT_ATTR registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits.

Table 5-41 PADMMR_FAULT_CLR Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 1030h

Figure 5-14 PADMMR_FAULT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLEAR
R-0h							W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-42 PADMMR_FAULT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLEAR	W1TC	0h	Fault clear Write 1 to clear the current fault Writing 0 has no effect

1.4.3.14 PADMMR_LOCK1_KICK0 Register ( Offset = 5008h) [reset = 0h]

PADMMR_LOCK1_KICK0 is shown in Figure 5-15 and described in Table 5-44.

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Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to PADMMR_LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written.

Table 5-43 PADMMR_LOCK1_KICK0 Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 5008h

Figure 5-15 PADMMR_LOCK1_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-44 PADMMR_LOCK1_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.4.3.15 PADMMR_LOCK1_KICK1 Register ( Offset = 500Ch) [reset = 0h]

PADMMR_LOCK1_KICK1 is shown in Figure 5-16 and described in Table 5-46.

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Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to PADMMR_LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written.

Table 5-45 PADMMR_LOCK1_KICK1 Instances

Instance	Physical Address
PADCFG_CTRL0_CFG0	000F 500Ch

Figure 5-16 PADMMR_LOCK1_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-46 PADMMR_LOCK1_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers