| 10h |
32 |
TOP_CTRL_EFUSE_DIEID0 |
50D8 0010h |
| 14h |
32 |
TOP_CTRL_EFUSE_DIEID1 |
50D8 0014h |
| 18h |
32 |
TOP_CTRL_EFUSE_DIEID2 |
50D8 0018h |
| 1Ch |
32 |
TOP_CTRL_EFUSE_DIEID3 |
50D8 001Ch |
| 20h |
32 |
TOP_CTRL_EFUSE_UID0 |
50D8 0020h |
| 24h |
32 |
TOP_CTRL_EFUSE_UID1 |
50D8 0024h |
| 28h |
32 |
TOP_CTRL_EFUSE_UID2 |
50D8 0028h |
| 2Ch |
32 |
TOP_CTRL_EFUSE_UID3 |
50D8 002Ch |
| 30h |
32 |
TOP_CTRL_EFUSE_DEVICE_TYPE |
50D8 0030h |
| 34h |
32 |
TOP_CTRL_EFUSE_FROM0_CHECKSUM |
50D8 0034h |
| 38h |
32 |
TOP_CTRL_EFUSE_JTAG_USERCODE_ID |
50D8 0038h |
| 428h |
32 |
TOP_CTRL_EFUSE1_ROW_12 |
50D8 0428h |
| 500h |
32 |
TOP_CTRL_MAC_ID0 |
50D8 0500h |
| 504h |
32 |
TOP_CTRL_MAC_ID1 |
50D8 0504h |
| C00h |
32 |
TOP_CTRL_ADC_REFBUF0_CTRL |
50D8 0C00h |
| C04h |
32 |
TOP_CTRL_ADC_REFBUF1_CTRL |
50D8 0C04h |
| C08h |
32 |
TOP_CTRL_ADC_REF_COMP_CTRL |
50D8 0C08h |
| C0Ch |
32 |
TOP_CTRL_ADC_REF_GOOD_STATUS |
50D8 0C0Ch |
| C10h |
32 |
TOP_CTRL_VMON_CTRL |
50D8 0C10h |
| C14h |
32 |
TOP_CTRL_VMON_STAT |
50D8 0C14h |
| C18h |
32 |
TOP_CTRL_PMU_COARSE_STAT |
50D8 0C18h |
| C20h |
32 |
TOP_CTRL_MASK_VMON_ERROR_ESM_H |
50D8 0C20h |
| C24h |
32 |
TOP_CTRL_MASK_VMON_ERROR_ESM_L |
50D8 0C24h |
| C34h |
32 |
TOP_CTRL_VMON_FILTER_CTRL |
50D8 0C34h |
| D00h |
32 |
TOP_CTRL_TSENSE_CFG |
50D8 0D00h |
| D04h |
32 |
TOP_CTRL_TSENSE_STATUS |
50D8 0D04h |
| D08h |
32 |
TOP_CTRL_TSENSE_STATUS_RAW |
50D8 0D08h |
| D10h |
32 |
TOP_CTRL_TSENSE0_TSHUT |
50D8 0D10h |
| D14h |
32 |
TOP_CTRL_TSENSE0_ALERT |
50D8 0D14h |
| D18h |
32 |
TOP_CTRL_TSENSE0_CNTL |
50D8 0D18h |
| D1Ch |
32 |
TOP_CTRL_TSENSE0_RESULT |
50D8 0D1Ch |
| D20h |
32 |
TOP_CTRL_TSENSE0_DATA0 |
50D8 0D20h |
| D24h |
32 |
TOP_CTRL_TSENSE0_DATA1 |
50D8 0D24h |
| D28h |
32 |
TOP_CTRL_TSENSE0_DATA2 |
50D8 0D28h |
| D2Ch |
32 |
TOP_CTRL_TSENSE0_DATA3 |
50D8 0D2Ch |
| D30h |
32 |
TOP_CTRL_TSENSE0_ACCU |
50D8 0D30h |
| D40h |
32 |
TOP_CTRL_TSENSE1_TSHUT |
50D8 0D40h |
| D44h |
32 |
TOP_CTRL_TSENSE1_ALERT |
50D8 0D44h |
| D48h |
32 |
TOP_CTRL_TSENSE1_CNTL |
50D8 0D48h |
| D4Ch |
32 |
TOP_CTRL_TSENSE1_RESULT |
50D8 0D4Ch |
| D50h |
32 |
TOP_CTRL_TSENSE1_DATA0 |
50D8 0D50h |
| D54h |
32 |
TOP_CTRL_TSENSE1_DATA1 |
50D8 0D54h |
| D58h |
32 |
TOP_CTRL_TSENSE1_DATA2 |
50D8 0D58h |
| D5Ch |
32 |
TOP_CTRL_TSENSE1_DATA3 |
50D8 0D5Ch |
| D60h |
32 |
TOP_CTRL_TSENSE1_ACCU |
50D8 0D60h |
| D7Ch |
32 |
TOP_CTRL_TSENSE2_RESULT |
50D8 0D7Ch |
| DACh |
32 |
TOP_CTRL_TSENSE3_RESULT |
50D8 0DACh |
| FD0h |
32 |
TOP_CTRL_HW_SPARE_RW0 |
50D8 0FD0h |
| FD4h |
32 |
TOP_CTRL_HW_SPARE_RW1 |
50D8 0FD4h |
| FD8h |
32 |
TOP_CTRL_HW_SPARE_RW2 |
50D8 0FD8h |
| FDCh |
32 |
TOP_CTRL_HW_SPARE_RW3 |
50D8 0FDCh |
| FE0h |
32 |
TOP_CTRL_HW_SPARE_RO0 |
50D8 0FE0h |
| FE4h |
32 |
TOP_CTRL_HW_SPARE_RO1 |
50D8 0FE4h |
| FE8h |
32 |
TOP_CTRL_HW_SPARE_RO2 |
50D8 0FE8h |
| FECh |
32 |
TOP_CTRL_HW_SPARE_RO3 |
50D8 0FECh |
| FF0h |
32 |
TOP_CTRL_HW_SPARE_WPH |
50D8 0FF0h |
| FF4h |
32 |
TOP_CTRL_HW_SPARE_REC |
50D8 0FF4h |
| FF8h |
32 |
TOP_CTRL_HW_SPARE_REC0 |
50D8 0FF8h |
| FFCh |
32 |
TOP_CTRL_HW_SPARE_REC1 |
50D8 0FFCh |
| 1008h |
32 |
TOP_CTRL_LOCK0_KICK0 |
50D8 1008h |
| 100Ch |
32 |
TOP_CTRL_LOCK0_KICK1 |
50D8 100Ch |
| 1010h |
32 |
TOP_CTRL_INTR_RAW_STATUS |
50D8 1010h |
| 1014h |
32 |
TOP_CTRL_INTR_ENABLED_STATUS_CLEAR |
50D8 1014h |
| 1018h |
32 |
TOP_CTRL_INTR_ENABLE |
50D8 1018h |
| 101Ch |
32 |
TOP_CTRL_INTR_ENABLE_CLEAR |
50D8 101Ch |
| 1020h |
32 |
TOP_CTRL_EOI |
50D8 1020h |
| 1024h |
32 |
TOP_CTRL_FAULT_ADDRESS |
50D8 1024h |
| 1028h |
32 |
TOP_CTRL_FAULT_TYPE_STATUS |
50D8 1028h |
| 102Ch |
32 |
TOP_CTRL_FAULT_ATTR_STATUS |
50D8 102Ch |
| 1030h |
32 |
TOP_CTRL_FAULT_CLEAR |
50D8 1030h |