SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
I2C Mode register
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| Instance Name | Physical Address |
|---|---|
| I2C0 | 5250 0024h |
| I2C1 | 5250 1024h |
| I2C2 | 5250 2024h |
| I2C3 | 5250 3024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU2 | |||||||
| NU2 | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU2 | |||||||
| NU2 | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NACKMOD | FREE | STT | NU1 | STP | MST | TRX | XA |
| R/W | R/W | R/W | NU1 | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RM | DLB | IRS | STB | FDF | BC2_BC1_BC0 | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | NU2 | NU2 | 0h | Reserved |
| 15 | NACKMOD | R/W | 0h | No Acknowledge [NACK] mode. This bit is used to send an Acknowledge [ACK] or a No Acknowledge [NACK] to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit [bit 8] if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle. |
| 14 | FREE | R/W | 0h | Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE 0:[default] Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a target it will stop when the transmission/receiving completes. FREE 1:The I2C runs free. |
| 13 | STT | R/W | 0h | Start Condition [Master only mode]. This bit can be set to a"1" by the CPU to generate a Start condition. In master mode when setting Start to"1" generates a Start condition. It is reset to "0" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop [ICCNT= n]______S-A-D..[n]..D-P _1_____0________Start [ICCNT= n]__________S-A-D..[n]..D ____________________________________________________ |
| 12 | NU1 | NU1 | 0h | Reserved for IDLEEN [IDLE Enable on 5509. - [RW ] |
| 11 | STP | R/W | 0h | Stop Condition [Master mode only]. This bit can be set to a"1" by the CPU to generate a Stop condition. It is reset to "0" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode[RM=0]. |
| 10 | MST | R/W | 0h | Master. MST 0:The I 2 C peripheral is in the"target" mode and clock is received from the"master" device. MST 1:The I 2 C peripheral is in the"master" mode and it generates the clock. This bit is clear when the transfer completed. |
| 9 | TRX | R/W | 0h | Transmitter. TRX 0:The I 2 C is in the"receiver" mode and data on data line SDA is shifted into the data register ICDRR. TRX 1:The I 2 C is in the"transmitter" mode and the data in ICDXR is shifted out on data line SDA. The operating modes [not in FDF mode] are defined as follows. In FDF mode TRX must be configured even if the I2C is in target mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____"target receiver" _0______x_____"target transmitter" _1______0_____"master receiver" _1______1_____"master transmitter" ______________________________ |
| 8 | XA | R/W | 0h | Expanded Address. XA 0:[default] 7-bit address mode [normal address mode]. XA 1:10-bit address mode [expanded address mode] Please note that XA needs to be configured even if the I2C is in target mode. |
| 7 | RM | R/W | 0h | Repeat Mode. This bit is set to a"1" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to"1" regardless of ICCNT value. This bit is don"t care if the I2C is configured in target mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____[Re]Start_______S-A-D..[n]..D____Repeat n _0_____1_____1_____[Re]Start-Stop___S-A-D..[n]..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____[Re]Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________ |
| 6 | DLB | R/W | 0h | Digital Loop Back [in master transmit mode only]. This bit is set to a"1" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after [[CPU freq/I2C freq]8] CPU cycles via an internal path. The address of the ICOAR is output on SDA. |
| 5 | IRS | R/W | 0h | I2C Reset Not. This can be set to a"0" by the CPU to put the I2C in reset or to a"1" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang [SDA and SCL are tri-stated]. |
| 4 | STB | R/W | 0h | Start Byte [Master only mode]. The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends "00000001" regardless ICSAR value. Refer to the Philip I2C spec for more details. |
| 3 | FDF | R/W | 0h | Free Data Format. This bit can be set to"1" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Target in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Target receiver in FDF mode _1______0_____1____Target transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________ |
| 2:0 | BC2_BC1_BC0 | R/W | 0h | Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb [excluding the acknowledge bit] of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA [reserved]____ NA [reserved] _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________ |